blob: d4e3ef5c2c0e2399782531688664eaa0b89fc927 [file] [log] [blame]
Kumar Gala9490a7f2008-07-25 13:31:05 -05001/*
Kumar Gala7c57f3e2011-01-11 00:52:35 -06002 * Copyright 2007-2009,2010-2011 Freescale Semiconductor, Inc.
Kumar Gala9490a7f2008-07-25 13:31:05 -05003 *
4 * See file CREDITS for list of people who contributed to this
5 * project.
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
20 * MA 02111-1307 USA
21 */
22
23/*
24 * mpc8536ds board configuration file
25 *
26 */
27#ifndef __CONFIG_H
28#define __CONFIG_H
29
Kumar Galac7e1a432010-05-21 04:14:49 -050030#include "../board/freescale/common/ics307_clk.h"
31
Wolfgang Denkd24f2d32010-10-04 19:58:00 +020032#ifdef CONFIG_36BIT
Kumar Gala337f9fd2009-07-30 15:54:07 -050033#define CONFIG_PHYS_64BIT 1
34#endif
35
Wolfgang Denkd24f2d32010-10-04 19:58:00 +020036#ifdef CONFIG_NAND
Mingkai Hu9a1a0ae2009-09-23 15:20:37 +080037#define CONFIG_NAND_U_BOOT 1
38#define CONFIG_RAMBOOT_NAND 1
Haiying Wang96196a12010-11-10 15:37:13 -050039#ifdef CONFIG_NAND_SPL
40#define CONFIG_SYS_TEXT_BASE_SPL 0xfff00000
41#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE_SPL /* start of monitor */
42#else
Kumar Gala00203c62011-01-31 15:57:01 -060043#define CONFIG_SYS_LDSCRIPT $(TOPDIR)/$(CPUDIR)/u-boot-nand.lds
Wolfgang Denk2ae18242010-10-06 09:05:45 +020044#define CONFIG_SYS_TEXT_BASE 0xf8f82000
Haiying Wang96196a12010-11-10 15:37:13 -050045#endif /* CONFIG_NAND_SPL */
Mingkai Hu9a1a0ae2009-09-23 15:20:37 +080046#endif
47
Wolfgang Denkd24f2d32010-10-04 19:58:00 +020048#ifdef CONFIG_SDCARD
Mingkai Hue40ac482009-09-23 15:20:38 +080049#define CONFIG_RAMBOOT_SDCARD 1
Wolfgang Denk2ae18242010-10-06 09:05:45 +020050#define CONFIG_SYS_TEXT_BASE 0xf8f80000
Kumar Gala7a577fd2011-01-12 02:48:53 -060051#define CONFIG_RESET_VECTOR_ADDRESS 0xf8fffffc
Mingkai Hue40ac482009-09-23 15:20:38 +080052#endif
53
Wolfgang Denkd24f2d32010-10-04 19:58:00 +020054#ifdef CONFIG_SPIFLASH
Mingkai Hue40ac482009-09-23 15:20:38 +080055#define CONFIG_RAMBOOT_SPIFLASH 1
Wolfgang Denk2ae18242010-10-06 09:05:45 +020056#define CONFIG_SYS_TEXT_BASE 0xf8f80000
Kumar Gala7a577fd2011-01-12 02:48:53 -060057#define CONFIG_RESET_VECTOR_ADDRESS 0xf8fffffc
Wolfgang Denk2ae18242010-10-06 09:05:45 +020058#endif
59
60#ifndef CONFIG_SYS_TEXT_BASE
61#define CONFIG_SYS_TEXT_BASE 0xeff80000
Mingkai Hue40ac482009-09-23 15:20:38 +080062#endif
63
Kumar Gala7a577fd2011-01-12 02:48:53 -060064#ifndef CONFIG_RESET_VECTOR_ADDRESS
65#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
66#endif
67
Haiying Wang96196a12010-11-10 15:37:13 -050068#ifndef CONFIG_SYS_MONITOR_BASE
69#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
70#endif
71
Kumar Gala9490a7f2008-07-25 13:31:05 -050072/* High Level Configuration Options */
73#define CONFIG_BOOKE 1 /* BOOKE */
74#define CONFIG_E500 1 /* BOOKE e500 family */
75#define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48 */
76#define CONFIG_MPC8536 1
77#define CONFIG_MPC8536DS 1
78
Kumar Galac51fc5d2009-01-23 14:22:13 -060079#define CONFIG_FSL_ELBC 1 /* Has Enhanced localbus controller */
Xie Xiaoboae2044d2011-10-03 12:18:39 -070080#define CONFIG_SPI_FLASH 1 /* Has SPI Flash */
Kumar Gala9490a7f2008-07-25 13:31:05 -050081#define CONFIG_PCI 1 /* Enable PCI/PCIE */
82#define CONFIG_PCI1 1 /* Enable PCI controller 1 */
83#define CONFIG_PCIE1 1 /* PCIE controler 1 (slot 1) */
84#define CONFIG_PCIE2 1 /* PCIE controler 2 (slot 2) */
85#define CONFIG_PCIE3 1 /* PCIE controler 3 (ULI bridge) */
86#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
87#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */
Kumar Gala0151cba2008-10-21 11:33:58 -050088#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
Kumar Gala9490a7f2008-07-25 13:31:05 -050089
90#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
Roy Zangf6155c62009-07-09 10:05:48 +080091#define CONFIG_E1000 1 /* Defind e1000 pci Ethernet card*/
Kumar Gala9490a7f2008-07-25 13:31:05 -050092
93#define CONFIG_TSEC_ENET /* tsec ethernet support */
94#define CONFIG_ENV_OVERWRITE
95
Kumar Galac7e1a432010-05-21 04:14:49 -050096#define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */
97#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk()
Kumar Gala9490a7f2008-07-25 13:31:05 -050098#define CONFIG_ICS307_REFCLK_HZ 33333000 /* ICS307 clock chip ref freq */
Kumar Gala9490a7f2008-07-25 13:31:05 -050099
100/*
101 * These can be toggled for performance analysis, otherwise use default.
102 */
103#define CONFIG_L2_CACHE /* toggle L2 cache */
104#define CONFIG_BTB /* toggle branch predition */
Kumar Gala9490a7f2008-07-25 13:31:05 -0500105
Andy Fleming80522dc2008-10-30 16:51:33 -0500106#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
107
Kumar Gala9490a7f2008-07-25 13:31:05 -0500108#define CONFIG_ENABLE_36BIT_PHYS 1
109
Kumar Gala337f9fd2009-07-30 15:54:07 -0500110#ifdef CONFIG_PHYS_64BIT
111#define CONFIG_ADDR_MAP 1
112#define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */
113#endif
114
Mingkai Hu07355702009-09-23 15:19:32 +0800115#define CONFIG_SYS_MEMTEST_START 0x00010000 /* skip exception vectors */
116#define CONFIG_SYS_MEMTEST_END 0x1f000000 /* skip u-boot at top of RAM */
Kumar Gala9490a7f2008-07-25 13:31:05 -0500117#define CONFIG_PANIC_HANG /* do not reset board on panic */
118
119/*
Mingkai Hu9a1a0ae2009-09-23 15:20:37 +0800120 * Config the L2 Cache as L2 SRAM
121 */
122#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
123#ifdef CONFIG_PHYS_64BIT
124#define CONFIG_SYS_INIT_L2_ADDR_PHYS 0xff8f80000ull
125#else
126#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
127#endif
128#define CONFIG_SYS_L2_SIZE (512 << 10)
129#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
130
Timur Tabie46fedf2011-08-04 18:03:41 -0500131#define CONFIG_SYS_CCSRBAR 0xffe00000
132#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
Kumar Gala9490a7f2008-07-25 13:31:05 -0500133
Mingkai Hu9a1a0ae2009-09-23 15:20:37 +0800134#if defined(CONFIG_RAMBOOT_NAND) && !defined(CONFIG_NAND_SPL)
Timur Tabie46fedf2011-08-04 18:03:41 -0500135#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
Mingkai Hu9a1a0ae2009-09-23 15:20:37 +0800136#endif
137
Kumar Gala9490a7f2008-07-25 13:31:05 -0500138/* DDR Setup */
Kumar Gala337f9fd2009-07-30 15:54:07 -0500139#define CONFIG_VERY_BIG_RAM
Kumar Gala9490a7f2008-07-25 13:31:05 -0500140#define CONFIG_FSL_DDR2
141#undef CONFIG_FSL_DDR_INTERACTIVE
142#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
143#define CONFIG_DDR_SPD
Kumar Gala9490a7f2008-07-25 13:31:05 -0500144
Dave Liu9b0ad1b2008-10-28 17:53:38 +0800145#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */
Kumar Gala9490a7f2008-07-25 13:31:05 -0500146#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
147
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200148#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
149#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
Kumar Gala9490a7f2008-07-25 13:31:05 -0500150
151#define CONFIG_NUM_DDR_CONTROLLERS 1
152#define CONFIG_DIMM_SLOTS_PER_CTLR 1
153#define CONFIG_CHIP_SELECTS_PER_CTRL 2
154
155/* I2C addresses of SPD EEPROMs */
156#define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200157#define CONFIG_SYS_SPD_BUS_NUM 1
Kumar Gala9490a7f2008-07-25 13:31:05 -0500158
159/* These are used when DDR doesn't use SPD. */
Mingkai Hu07355702009-09-23 15:19:32 +0800160#define CONFIG_SYS_SDRAM_SIZE 256 /* DDR is 256MB */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200161#define CONFIG_SYS_DDR_CS0_BNDS 0x0000001F
Mingkai Hu07355702009-09-23 15:19:32 +0800162#define CONFIG_SYS_DDR_CS0_CONFIG 0x80010102 /* Enable, no interleaving */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200163#define CONFIG_SYS_DDR_TIMING_3 0x00000000
164#define CONFIG_SYS_DDR_TIMING_0 0x00260802
165#define CONFIG_SYS_DDR_TIMING_1 0x3935d322
166#define CONFIG_SYS_DDR_TIMING_2 0x14904cc8
167#define CONFIG_SYS_DDR_MODE_1 0x00480432
168#define CONFIG_SYS_DDR_MODE_2 0x00000000
169#define CONFIG_SYS_DDR_INTERVAL 0x06180100
170#define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
171#define CONFIG_SYS_DDR_CLK_CTRL 0x03800000
172#define CONFIG_SYS_DDR_OCD_CTRL 0x00000000
173#define CONFIG_SYS_DDR_OCD_STATUS 0x00000000
Mingkai Hu07355702009-09-23 15:19:32 +0800174#define CONFIG_SYS_DDR_CONTROL 0xC3008000 /* Type = DDR2 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200175#define CONFIG_SYS_DDR_CONTROL2 0x04400010
Kumar Gala9490a7f2008-07-25 13:31:05 -0500176
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200177#define CONFIG_SYS_DDR_ERR_INT_EN 0x0000000d
178#define CONFIG_SYS_DDR_ERR_DIS 0x00000000
179#define CONFIG_SYS_DDR_SBE 0x00010000
Kumar Gala9490a7f2008-07-25 13:31:05 -0500180
Kumar Gala9490a7f2008-07-25 13:31:05 -0500181/* Make sure required options are set */
182#ifndef CONFIG_SPD_EEPROM
183#error ("CONFIG_SPD_EEPROM is required")
184#endif
185
186#undef CONFIG_CLOCKS_IN_MHZ
187
188
189/*
190 * Memory map -- xxx -this is wrong, needs updating
191 *
192 * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable
193 * 0x8000_0000 0xbfff_ffff PCI Express Mem 1G non-cacheable
194 * 0xc000_0000 0xdfff_ffff PCI 512M non-cacheable
195 * 0xe100_0000 0xe3ff_ffff PCI IO range 4M non-cacheable
196 *
197 * Localbus cacheable (TBD)
198 * 0xXXXX_XXXX 0xXXXX_XXXX SRAM YZ M Cacheable
199 *
200 * Localbus non-cacheable
Jason Jinc57fc282008-10-31 05:07:04 -0500201 * 0xe000_0000 0xe7ff_ffff Promjet/free 128M non-cacheable
Kumar Gala9490a7f2008-07-25 13:31:05 -0500202 * 0xe800_0000 0xefff_ffff FLASH 128M non-cacheable
Jason Jinc57fc282008-10-31 05:07:04 -0500203 * 0xffa0_0000 0xffaf_ffff NAND 1M non-cacheable
Kumar Gala9490a7f2008-07-25 13:31:05 -0500204 * 0xffdf_0000 0xffdf_7fff PIXIS 32K non-cacheable TLB0
205 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0
206 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable
207 */
208
209/*
210 * Local Bus Definitions
211 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200212#define CONFIG_SYS_FLASH_BASE 0xe0000000 /* start of FLASH 128M */
Kumar Gala337f9fd2009-07-30 15:54:07 -0500213#ifdef CONFIG_PHYS_64BIT
214#define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull
215#else
Kumar Galac953ddf2008-12-02 14:19:34 -0600216#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
Kumar Gala337f9fd2009-07-30 15:54:07 -0500217#endif
Kumar Gala9490a7f2008-07-25 13:31:05 -0500218
Mingkai Hu9a1a0ae2009-09-23 15:20:37 +0800219#define CONFIG_FLASH_BR_PRELIM \
Mingkai Hu07355702009-09-23 15:19:32 +0800220 (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000)) \
221 | BR_PS_16 | BR_V)
Mingkai Hu9a1a0ae2009-09-23 15:20:37 +0800222#define CONFIG_FLASH_OR_PRELIM 0xf8000ff7
Kumar Gala9490a7f2008-07-25 13:31:05 -0500223
Mingkai Hu07355702009-09-23 15:19:32 +0800224#define CONFIG_SYS_BR1_PRELIM \
225 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \
226 | BR_PS_16 | BR_V)
Kumar Galac953ddf2008-12-02 14:19:34 -0600227#define CONFIG_SYS_OR1_PRELIM 0xf8000ff7
Kumar Gala9490a7f2008-07-25 13:31:05 -0500228
Mingkai Hu07355702009-09-23 15:19:32 +0800229#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, \
230 CONFIG_SYS_FLASH_BASE_PHYS }
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200231#define CONFIG_SYS_FLASH_QUIET_TEST
Kumar Gala9490a7f2008-07-25 13:31:05 -0500232#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
233
Mingkai Hu07355702009-09-23 15:19:32 +0800234#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
235#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200236#undef CONFIG_SYS_FLASH_CHECKSUM
Mingkai Hu07355702009-09-23 15:19:32 +0800237#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
238#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
Kumar Gala9490a7f2008-07-25 13:31:05 -0500239
Kumar Galaa55bb832010-11-29 14:32:11 -0600240#if defined(CONFIG_RAMBOOT_NAND) || defined(CONFIG_RAMBOOT_SDCARD) || \
241 defined(CONFIG_RAMBOOT_SPIFLASH)
Mingkai Hu9a1a0ae2009-09-23 15:20:37 +0800242#define CONFIG_SYS_RAMBOOT
Kumar Galaa55bb832010-11-29 14:32:11 -0600243#define CONFIG_SYS_EXTRA_ENV_RELOC
Mingkai Hu9a1a0ae2009-09-23 15:20:37 +0800244#else
245#undef CONFIG_SYS_RAMBOOT
246#endif
247
Kumar Gala9490a7f2008-07-25 13:31:05 -0500248#define CONFIG_FLASH_CFI_DRIVER
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200249#define CONFIG_SYS_FLASH_CFI
250#define CONFIG_SYS_FLASH_EMPTY_INFO
251#define CONFIG_SYS_FLASH_AMD_CHECK_DQ7
Kumar Gala9490a7f2008-07-25 13:31:05 -0500252
253#define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */
254
Ramneek Mehresh68d42302011-06-07 10:10:43 +0000255#define CONFIG_HWCONFIG /* enable hwconfig */
Kumar Gala9490a7f2008-07-25 13:31:05 -0500256#define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */
257#define PIXIS_BASE 0xffdf0000 /* PIXIS registers */
Kumar Gala337f9fd2009-07-30 15:54:07 -0500258#ifdef CONFIG_PHYS_64BIT
259#define PIXIS_BASE_PHYS 0xfffdf0000ull
260#else
Kumar Gala52b565f2008-12-02 14:19:33 -0600261#define PIXIS_BASE_PHYS PIXIS_BASE
Kumar Gala337f9fd2009-07-30 15:54:07 -0500262#endif
Kumar Gala9490a7f2008-07-25 13:31:05 -0500263
Kumar Gala52b565f2008-12-02 14:19:33 -0600264#define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V)
Mingkai Hu07355702009-09-23 15:19:32 +0800265#define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */
Kumar Gala9490a7f2008-07-25 13:31:05 -0500266
267#define PIXIS_ID 0x0 /* Board ID at offset 0 */
268#define PIXIS_VER 0x1 /* Board version at offset 1 */
269#define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */
270#define PIXIS_CSR 0x3 /* PIXIS General control/status register */
271#define PIXIS_RST 0x4 /* PIXIS Reset Control register */
272#define PIXIS_PWR 0x5 /* PIXIS Power status register */
273#define PIXIS_AUX 0x6 /* Auxiliary 1 register */
274#define PIXIS_SPD 0x7 /* Register for SYSCLK speed */
275#define PIXIS_AUX2 0x8 /* Auxiliary 2 register */
276#define PIXIS_VCTL 0x10 /* VELA Control Register */
277#define PIXIS_VSTAT 0x11 /* VELA Status Register */
278#define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */
279#define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */
280#define PIXIS_VCORE0 0x14 /* VELA VCORE0 Register */
281#define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */
Kumar Gala6bb5b412009-07-14 22:42:01 -0500282#define PIXIS_VBOOT_LBMAP 0xe0 /* VBOOT - CFG_LBMAP */
283#define PIXIS_VBOOT_LBMAP_NOR0 0x00 /* cfg_lbmap - boot from NOR 0 */
284#define PIXIS_VBOOT_LBMAP_NOR1 0x01 /* cfg_lbmap - boot from NOR 1 */
285#define PIXIS_VBOOT_LBMAP_NOR2 0x02 /* cfg_lbmap - boot from NOR 2 */
286#define PIXIS_VBOOT_LBMAP_NOR3 0x03 /* cfg_lbmap - boot from NOR 3 */
287#define PIXIS_VBOOT_LBMAP_PJET 0x04 /* cfg_lbmap - boot from projet */
288#define PIXIS_VBOOT_LBMAP_NAND 0x05 /* cfg_lbmap - boot from NAND */
Kumar Gala9490a7f2008-07-25 13:31:05 -0500289#define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */
290#define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */
291#define PIXIS_VSPEED2 0x19 /* VELA VSpeed 2 */
292#define PIXIS_VSYSCLK0 0x1A /* VELA SYSCLK0 Register */
293#define PIXIS_VSYSCLK1 0x1B /* VELA SYSCLK1 Register */
294#define PIXIS_VSYSCLK2 0x1C /* VELA SYSCLK2 Register */
295#define PIXIS_VDDRCLK0 0x1D /* VELA DDRCLK0 Register */
296#define PIXIS_VDDRCLK1 0x1E /* VELA DDRCLK1 Register */
297#define PIXIS_VDDRCLK2 0x1F /* VELA DDRCLK2 Register */
298#define PIXIS_VWATCH 0x24 /* Watchdog Register */
299#define PIXIS_LED 0x25 /* LED Register */
300
Mingkai Hu9a1a0ae2009-09-23 15:20:37 +0800301#define PIXIS_SPD_SYSCLK 0x7 /* SYSCLK option */
302
Kumar Gala9490a7f2008-07-25 13:31:05 -0500303/* old pixis referenced names */
304#define PIXIS_VCLKH 0x19 /* VELA VCLKH register */
305#define PIXIS_VCLKL 0x1A /* VELA VCLKL register */
Matthew McClintock509e19c2011-02-25 16:20:11 -0600306#define CONFIG_SYS_PIXIS_VBOOT_MASK 0x4e
Kumar Gala9490a7f2008-07-25 13:31:05 -0500307
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200308#define CONFIG_SYS_INIT_RAM_LOCK 1
309#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */
Wolfgang Denk553f0982010-10-26 13:32:32 +0200310#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */
Kumar Gala9490a7f2008-07-25 13:31:05 -0500311
Mingkai Hu07355702009-09-23 15:19:32 +0800312#define CONFIG_SYS_GBL_DATA_OFFSET \
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200313 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200314#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
Kumar Gala9490a7f2008-07-25 13:31:05 -0500315
Mingkai Hu07355702009-09-23 15:19:32 +0800316#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
317#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */
Kumar Gala9490a7f2008-07-25 13:31:05 -0500318
Mingkai Hu9a1a0ae2009-09-23 15:20:37 +0800319#ifndef CONFIG_NAND_SPL
Kumar Gala337f9fd2009-07-30 15:54:07 -0500320#define CONFIG_SYS_NAND_BASE 0xffa00000
321#ifdef CONFIG_PHYS_64BIT
322#define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull
323#else
324#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
325#endif
Mingkai Hu9a1a0ae2009-09-23 15:20:37 +0800326#else
327#define CONFIG_SYS_NAND_BASE 0xfff00000
328#ifdef CONFIG_PHYS_64BIT
329#define CONFIG_SYS_NAND_BASE_PHYS 0xffff00000ull
330#else
331#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
332#endif
333#endif
Jason Jinc57fc282008-10-31 05:07:04 -0500334#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE,\
335 CONFIG_SYS_NAND_BASE + 0x40000, \
336 CONFIG_SYS_NAND_BASE + 0x80000, \
337 CONFIG_SYS_NAND_BASE + 0xC0000}
338#define CONFIG_SYS_MAX_NAND_DEVICE 4
Jason Jinc57fc282008-10-31 05:07:04 -0500339#define CONFIG_MTD_NAND_VERIFY_WRITE
340#define CONFIG_CMD_NAND 1
341#define CONFIG_NAND_FSL_ELBC 1
342#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
343
Mingkai Hu9a1a0ae2009-09-23 15:20:37 +0800344/* NAND boot: 4K NAND loader config */
345#define CONFIG_SYS_NAND_SPL_SIZE 0x1000
346#define CONFIG_SYS_NAND_U_BOOT_SIZE ((512 << 10) - 0x2000)
347#define CONFIG_SYS_NAND_U_BOOT_DST (CONFIG_SYS_INIT_L2_ADDR)
348#define CONFIG_SYS_NAND_U_BOOT_START \
349 (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_NAND_SPL_SIZE)
350#define CONFIG_SYS_NAND_U_BOOT_OFFS (0)
351#define CONFIG_SYS_NAND_U_BOOT_RELOC (CONFIG_SYS_INIT_L2_END - 0x2000)
352#define CONFIG_SYS_NAND_U_BOOT_RELOC_SP ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
353
Jason Jinc57fc282008-10-31 05:07:04 -0500354/* NAND flash config */
Matthew McClintocka3055c52011-04-05 14:39:33 -0500355#define CONFIG_SYS_NAND_BR_PRELIM \
Mingkai Hu07355702009-09-23 15:19:32 +0800356 (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
357 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
358 | BR_PS_8 /* Port Size = 8 bit */ \
359 | BR_MS_FCM /* MSEL = FCM */ \
360 | BR_V) /* valid */
Matthew McClintocka3055c52011-04-05 14:39:33 -0500361#define CONFIG_SYS_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \
Mingkai Hu07355702009-09-23 15:19:32 +0800362 | OR_FCM_PGS /* Large Page*/ \
363 | OR_FCM_CSCT \
364 | OR_FCM_CST \
365 | OR_FCM_CHT \
366 | OR_FCM_SCY_1 \
367 | OR_FCM_TRLX \
368 | OR_FCM_EHTR)
Jason Jinc57fc282008-10-31 05:07:04 -0500369
Mingkai Hu9a1a0ae2009-09-23 15:20:37 +0800370#ifdef CONFIG_RAMBOOT_NAND
Matthew McClintocka3055c52011-04-05 14:39:33 -0500371#define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
372#define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
Mingkai Hu9a1a0ae2009-09-23 15:20:37 +0800373#define CONFIG_SYS_BR2_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
374#define CONFIG_SYS_OR2_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
375#else
376#define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
377#define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
Matthew McClintocka3055c52011-04-05 14:39:33 -0500378#define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
379#define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
Mingkai Hu9a1a0ae2009-09-23 15:20:37 +0800380#endif
Jason Jinc57fc282008-10-31 05:07:04 -0500381
Mingkai Hu07355702009-09-23 15:19:32 +0800382#define CONFIG_SYS_BR4_PRELIM \
383 (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0x40000)) \
384 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
385 | BR_PS_8 /* Port Size = 8 bit */ \
386 | BR_MS_FCM /* MSEL = FCM */ \
387 | BR_V) /* valid */
Matthew McClintocka3055c52011-04-05 14:39:33 -0500388#define CONFIG_SYS_OR4_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
Mingkai Hu07355702009-09-23 15:19:32 +0800389#define CONFIG_SYS_BR5_PRELIM \
390 (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0x80000)) \
391 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
392 | BR_PS_8 /* Port Size = 8 bit */ \
393 | BR_MS_FCM /* MSEL = FCM */ \
394 | BR_V) /* valid */
Matthew McClintocka3055c52011-04-05 14:39:33 -0500395#define CONFIG_SYS_OR5_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
Jason Jinc57fc282008-10-31 05:07:04 -0500396
Mingkai Hu07355702009-09-23 15:19:32 +0800397#define CONFIG_SYS_BR6_PRELIM \
398 (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0xc0000)) \
399 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
400 | BR_PS_8 /* Port Size = 8 bit */ \
401 | BR_MS_FCM /* MSEL = FCM */ \
402 | BR_V) /* valid */
Matthew McClintocka3055c52011-04-05 14:39:33 -0500403#define CONFIG_SYS_OR6_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
Jason Jinc57fc282008-10-31 05:07:04 -0500404
Kumar Gala9490a7f2008-07-25 13:31:05 -0500405/* Serial Port - controlled on board with jumper J8
406 * open - index 2
407 * shorted - index 1
408 */
409#define CONFIG_CONS_INDEX 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200410#define CONFIG_SYS_NS16550
411#define CONFIG_SYS_NS16550_SERIAL
412#define CONFIG_SYS_NS16550_REG_SIZE 1
413#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
Kumar Gala93341902010-04-07 01:34:11 -0500414#ifdef CONFIG_NAND_SPL
415#define CONFIG_NS16550_MIN_FUNCTIONS
416#endif
Kumar Gala9490a7f2008-07-25 13:31:05 -0500417
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200418#define CONFIG_SYS_BAUDRATE_TABLE \
Kumar Gala9490a7f2008-07-25 13:31:05 -0500419 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
420
Mingkai Hu07355702009-09-23 15:19:32 +0800421#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR + 0x4500)
422#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR + 0x4600)
Kumar Gala9490a7f2008-07-25 13:31:05 -0500423
424/* Use the HUSH parser */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200425#define CONFIG_SYS_HUSH_PARSER
426#ifdef CONFIG_SYS_HUSH_PARSER
427#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
Kumar Gala9490a7f2008-07-25 13:31:05 -0500428#endif
429
430/*
431 * Pass open firmware flat tree
432 */
433#define CONFIG_OF_LIBFDT 1
434#define CONFIG_OF_BOARD_SETUP 1
435#define CONFIG_OF_STDOUT_VIA_ALIAS 1
436
Kumar Gala9490a7f2008-07-25 13:31:05 -0500437/*
438 * I2C
439 */
440#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
441#define CONFIG_HARD_I2C /* I2C with hardware support */
442#undef CONFIG_SOFT_I2C /* I2C bit-banged */
443#define CONFIG_I2C_MULTI_BUS
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200444#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
445#define CONFIG_SYS_I2C_SLAVE 0x7F
446#define CONFIG_SYS_I2C_NOPROBES {{0, 0x29}} /* Don't probe these addrs */
447#define CONFIG_SYS_I2C_OFFSET 0x3000
448#define CONFIG_SYS_I2C2_OFFSET 0x3100
Kumar Gala9490a7f2008-07-25 13:31:05 -0500449
450/*
451 * I2C2 EEPROM
452 */
Jean-Christophe PLAGNIOL-VILLARD32628c52008-08-30 23:54:58 +0200453#define CONFIG_ID_EEPROM
454#ifdef CONFIG_ID_EEPROM
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200455#define CONFIG_SYS_I2C_EEPROM_NXID
Kumar Gala9490a7f2008-07-25 13:31:05 -0500456#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200457#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
458#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
459#define CONFIG_SYS_EEPROM_BUS_NUM 1
Kumar Gala9490a7f2008-07-25 13:31:05 -0500460
461/*
Xie Xiaoboae2044d2011-10-03 12:18:39 -0700462 * eSPI - Enhanced SPI
463 */
464#define CONFIG_HARD_SPI
465#define CONFIG_FSL_ESPI
466
467#if defined(CONFIG_SPI_FLASH)
468#define CONFIG_SPI_FLASH_SPANSION
469#define CONFIG_CMD_SF
470#define CONFIG_SF_DEFAULT_SPEED 10000000
471#define CONFIG_SF_DEFAULT_MODE 0
472#endif
473
474/*
Kumar Gala9490a7f2008-07-25 13:31:05 -0500475 * General PCI
476 * Memory space is mapped 1-1, but I/O space must start from 0.
477 */
478
Kumar Gala5af0fdd2008-12-02 16:08:39 -0600479#define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000
Kumar Gala337f9fd2009-07-30 15:54:07 -0500480#ifdef CONFIG_PHYS_64BIT
481#define CONFIG_SYS_PCI1_MEM_BUS 0xf0000000
482#define CONFIG_SYS_PCI1_MEM_PHYS 0xc00000000ull
483#else
Kumar Gala5af0fdd2008-12-02 16:08:39 -0600484#define CONFIG_SYS_PCI1_MEM_BUS 0x80000000
485#define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000
Kumar Gala337f9fd2009-07-30 15:54:07 -0500486#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200487#define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
Kumar Gala337f9fd2009-07-30 15:54:07 -0500488#define CONFIG_SYS_PCI1_IO_VIRT 0xffc00000
489#define CONFIG_SYS_PCI1_IO_BUS 0x00000000
490#ifdef CONFIG_PHYS_64BIT
491#define CONFIG_SYS_PCI1_IO_PHYS 0xfffc00000ull
492#else
493#define CONFIG_SYS_PCI1_IO_PHYS 0xffc00000
494#endif
495#define CONFIG_SYS_PCI1_IO_SIZE 0x00010000 /* 64k */
Kumar Gala9490a7f2008-07-25 13:31:05 -0500496
497/* controller 1, Slot 1, tgtid 1, Base address a000 */
Kumar Gala5f7b31b2010-12-17 15:14:54 -0600498#define CONFIG_SYS_PCIE1_NAME "Slot 1"
Kumar Gala5af0fdd2008-12-02 16:08:39 -0600499#define CONFIG_SYS_PCIE1_MEM_VIRT 0x90000000
Kumar Gala337f9fd2009-07-30 15:54:07 -0500500#ifdef CONFIG_PHYS_64BIT
501#define CONFIG_SYS_PCIE1_MEM_BUS 0xf8000000
502#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc10000000ull
503#else
Kumar Gala10795f42008-12-02 16:08:36 -0600504#define CONFIG_SYS_PCIE1_MEM_BUS 0x90000000
Kumar Gala5af0fdd2008-12-02 16:08:39 -0600505#define CONFIG_SYS_PCIE1_MEM_PHYS 0x90000000
Kumar Gala337f9fd2009-07-30 15:54:07 -0500506#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200507#define CONFIG_SYS_PCIE1_MEM_SIZE 0x08000000 /* 128M */
Kumar Galaaca5f012008-12-02 16:08:40 -0600508#define CONFIG_SYS_PCIE1_IO_VIRT 0xffc10000
Kumar Gala337f9fd2009-07-30 15:54:07 -0500509#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
510#ifdef CONFIG_PHYS_64BIT
511#define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc10000ull
512#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200513#define CONFIG_SYS_PCIE1_IO_PHYS 0xffc10000
Kumar Gala337f9fd2009-07-30 15:54:07 -0500514#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200515#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
Kumar Gala9490a7f2008-07-25 13:31:05 -0500516
517/* controller 2, Slot 2, tgtid 2, Base address 9000 */
Kumar Gala5f7b31b2010-12-17 15:14:54 -0600518#define CONFIG_SYS_PCIE2_NAME "Slot 2"
Kumar Gala5af0fdd2008-12-02 16:08:39 -0600519#define CONFIG_SYS_PCIE2_MEM_VIRT 0x98000000
Kumar Gala337f9fd2009-07-30 15:54:07 -0500520#ifdef CONFIG_PHYS_64BIT
521#define CONFIG_SYS_PCIE2_MEM_BUS 0xf8000000
522#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc18000000ull
523#else
Kumar Gala10795f42008-12-02 16:08:36 -0600524#define CONFIG_SYS_PCIE2_MEM_BUS 0x98000000
Kumar Gala5af0fdd2008-12-02 16:08:39 -0600525#define CONFIG_SYS_PCIE2_MEM_PHYS 0x98000000
Kumar Gala337f9fd2009-07-30 15:54:07 -0500526#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200527#define CONFIG_SYS_PCIE2_MEM_SIZE 0x08000000 /* 128M */
Kumar Galaaca5f012008-12-02 16:08:40 -0600528#define CONFIG_SYS_PCIE2_IO_VIRT 0xffc20000
Kumar Gala337f9fd2009-07-30 15:54:07 -0500529#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
530#ifdef CONFIG_PHYS_64BIT
531#define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc20000ull
532#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200533#define CONFIG_SYS_PCIE2_IO_PHYS 0xffc20000
Kumar Gala337f9fd2009-07-30 15:54:07 -0500534#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200535#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
Kumar Gala9490a7f2008-07-25 13:31:05 -0500536
537/* controller 3, direct to uli, tgtid 3, Base address 8000 */
Kumar Gala5f7b31b2010-12-17 15:14:54 -0600538#define CONFIG_SYS_PCIE3_NAME "Slot 3"
Kumar Gala5af0fdd2008-12-02 16:08:39 -0600539#define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000
Kumar Gala337f9fd2009-07-30 15:54:07 -0500540#ifdef CONFIG_PHYS_64BIT
541#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
542#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull
543#else
Kumar Gala10795f42008-12-02 16:08:36 -0600544#define CONFIG_SYS_PCIE3_MEM_BUS 0xa0000000
Kumar Gala5af0fdd2008-12-02 16:08:39 -0600545#define CONFIG_SYS_PCIE3_MEM_PHYS 0xa0000000
Kumar Gala337f9fd2009-07-30 15:54:07 -0500546#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200547#define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */
Kumar Galaaca5f012008-12-02 16:08:40 -0600548#define CONFIG_SYS_PCIE3_IO_VIRT 0xffc30000
Kumar Gala337f9fd2009-07-30 15:54:07 -0500549#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
550#ifdef CONFIG_PHYS_64BIT
551#define CONFIG_SYS_PCIE3_IO_PHYS 0xfffc30000ull
552#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200553#define CONFIG_SYS_PCIE3_IO_PHYS 0xffc30000
Kumar Gala337f9fd2009-07-30 15:54:07 -0500554#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200555#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
Kumar Gala9490a7f2008-07-25 13:31:05 -0500556
557#if defined(CONFIG_PCI)
558
Kumar Gala9490a7f2008-07-25 13:31:05 -0500559#define CONFIG_PCI_PNP /* do pci plug-and-play */
560
561/*PCIE video card used*/
Kumar Galaaca5f012008-12-02 16:08:40 -0600562#define VIDEO_IO_OFFSET CONFIG_SYS_PCIE3_IO_VIRT
Kumar Gala9490a7f2008-07-25 13:31:05 -0500563
564/*PCI video card used*/
Kumar Galaaca5f012008-12-02 16:08:40 -0600565/*#define VIDEO_IO_OFFSET CONFIG_SYS_PCI1_IO_VIRT*/
Kumar Gala9490a7f2008-07-25 13:31:05 -0500566
567/* video */
568#define CONFIG_VIDEO
569
570#if defined(CONFIG_VIDEO)
571#define CONFIG_BIOSEMU
572#define CONFIG_CFB_CONSOLE
573#define CONFIG_VIDEO_SW_CURSOR
574#define CONFIG_VGA_AS_SINGLE_DEVICE
575#define CONFIG_ATI_RADEON_FB
576#define CONFIG_VIDEO_LOGO
577/*#define CONFIG_CONSOLE_CURSOR*/
Kumar Galaaca5f012008-12-02 16:08:40 -0600578#define CONFIG_SYS_ISA_IO_BASE_ADDRESS CONFIG_SYS_PCIE3_IO_VIRT
Kumar Gala9490a7f2008-07-25 13:31:05 -0500579#endif
580
581#undef CONFIG_EEPRO100
582#undef CONFIG_TULIP
583#undef CONFIG_RTL8139
584
Kumar Gala9490a7f2008-07-25 13:31:05 -0500585#ifndef CONFIG_PCI_PNP
Kumar Gala5f91ef62008-12-02 16:08:37 -0600586 #define PCI_ENET0_IOADDR CONFIG_SYS_PCI1_IO_BUS
587 #define PCI_ENET0_MEMADDR CONFIG_SYS_PCI1_IO_BUS
Kumar Gala9490a7f2008-07-25 13:31:05 -0500588 #define PCI_IDSEL_NUMBER 0x11 /* IDSEL = AD11 */
589#endif
590
591#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
592
593#endif /* CONFIG_PCI */
594
595/* SATA */
596#define CONFIG_LIBATA
597#define CONFIG_FSL_SATA
598
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200599#define CONFIG_SYS_SATA_MAX_DEVICE 2
Kumar Gala9490a7f2008-07-25 13:31:05 -0500600#define CONFIG_SATA1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200601#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
602#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
Kumar Gala9490a7f2008-07-25 13:31:05 -0500603#define CONFIG_SATA2
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200604#define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
605#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
Kumar Gala9490a7f2008-07-25 13:31:05 -0500606
607#ifdef CONFIG_FSL_SATA
608#define CONFIG_LBA48
609#define CONFIG_CMD_SATA
610#define CONFIG_DOS_PARTITION
611#define CONFIG_CMD_EXT2
612#endif
613
614#if defined(CONFIG_TSEC_ENET)
615
Kumar Gala9490a7f2008-07-25 13:31:05 -0500616#define CONFIG_MII 1 /* MII PHY management */
617#define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */
618#define CONFIG_TSEC1 1
619#define CONFIG_TSEC1_NAME "eTSEC1"
620#define CONFIG_TSEC3 1
621#define CONFIG_TSEC3_NAME "eTSEC3"
622
Jason Jin2e26d832008-10-10 11:41:00 +0800623#define CONFIG_FSL_SGMII_RISER 1
624#define SGMII_RISER_PHY_OFFSET 0x1c
625
Kumar Gala9490a7f2008-07-25 13:31:05 -0500626#define TSEC1_PHY_ADDR 1 /* TSEC1 -> PHY1 */
627#define TSEC3_PHY_ADDR 0 /* TSEC3 -> PHY0 */
628
629#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
630#define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
631
632#define TSEC1_PHYIDX 0
633#define TSEC3_PHYIDX 0
634
635#define CONFIG_ETHPRIME "eTSEC1"
636
637#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
638
639#endif /* CONFIG_TSEC_ENET */
640
641/*
642 * Environment
643 */
Mingkai Hu9a1a0ae2009-09-23 15:20:37 +0800644
645#if defined(CONFIG_SYS_RAMBOOT)
646#if defined(CONFIG_RAMBOOT_NAND)
Xie Xiaobo2d4afd42011-10-03 12:54:21 -0700647#define CONFIG_ENV_IS_IN_NAND 1
648#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
649#define CONFIG_ENV_OFFSET ((512 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE)
650#define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE)
651#elif defined(CONFIG_RAMBOOT_SPIFLASH)
652#define CONFIG_ENV_IS_IN_SPI_FLASH
653#define CONFIG_ENV_SPI_BUS 0
654#define CONFIG_ENV_SPI_CS 0
655#define CONFIG_ENV_SPI_MAX_HZ 10000000
656#define CONFIG_ENV_SPI_MODE 0
657#define CONFIG_ENV_SIZE 0x2000 /* 8KB */
658#define CONFIG_ENV_OFFSET 0xF0000
659#define CONFIG_ENV_SECT_SIZE 0x10000
660#elif defined(CONFIG_RAMBOOT_SDCARD)
661#define CONFIG_ENV_IS_IN_MMC
662#define CONFIG_ENV_SIZE 0x2000
663#define CONFIG_SYS_MMC_ENV_DEV 0
664#else
Mingkai Hue40ac482009-09-23 15:20:38 +0800665 #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
666 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
667 #define CONFIG_ENV_SIZE 0x2000
Kumar Gala9490a7f2008-07-25 13:31:05 -0500668#endif
Mingkai Hu9a1a0ae2009-09-23 15:20:37 +0800669#else
670 #define CONFIG_ENV_IS_IN_FLASH 1
671 #if CONFIG_SYS_MONITOR_BASE > 0xfff80000
672 #define CONFIG_ENV_ADDR 0xfff80000
673 #else
674 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
675 #endif
676 #define CONFIG_ENV_SIZE 0x2000
677 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
678#endif
Kumar Gala9490a7f2008-07-25 13:31:05 -0500679
680#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200681#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
Kumar Gala9490a7f2008-07-25 13:31:05 -0500682
683/*
684 * Command line configuration.
685 */
686#include <config_cmd_default.h>
687
688#define CONFIG_CMD_IRQ
689#define CONFIG_CMD_PING
690#define CONFIG_CMD_I2C
691#define CONFIG_CMD_MII
692#define CONFIG_CMD_ELF
Kumar Gala1c9aa762008-09-22 23:40:42 -0500693#define CONFIG_CMD_IRQ
694#define CONFIG_CMD_SETEXPR
Becky Bruce199e2622010-06-17 11:37:25 -0500695#define CONFIG_CMD_REGINFO
Kumar Gala9490a7f2008-07-25 13:31:05 -0500696
697#if defined(CONFIG_PCI)
698#define CONFIG_CMD_PCI
Kumar Gala9490a7f2008-07-25 13:31:05 -0500699#define CONFIG_CMD_NET
700#endif
701
702#undef CONFIG_WATCHDOG /* watchdog disabled */
703
Andy Fleming80522dc2008-10-30 16:51:33 -0500704#define CONFIG_MMC 1
705
706#ifdef CONFIG_MMC
707#define CONFIG_FSL_ESDHC
708#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
709#define CONFIG_CMD_MMC
710#define CONFIG_GENERIC_MMC
Fanzc1116ebb2011-10-03 12:18:42 -0700711#endif
712
713/*
714 * USB
715 */
716#define CONFIG_USB_EHCI
717
718#ifdef CONFIG_USB_EHCI
719#define CONFIG_CMD_USB
720#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
721#define CONFIG_USB_EHCI_FSL
722#define CONFIG_USB_STORAGE
723#endif
724
725#if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI)
Andy Fleming80522dc2008-10-30 16:51:33 -0500726#define CONFIG_CMD_EXT2
727#define CONFIG_CMD_FAT
728#define CONFIG_DOS_PARTITION
729#endif
730
Kumar Gala9490a7f2008-07-25 13:31:05 -0500731/*
732 * Miscellaneous configurable options
733 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200734#define CONFIG_SYS_LONGHELP /* undef to save memory */
Mingkai Hu07355702009-09-23 15:19:32 +0800735#define CONFIG_CMDLINE_EDITING /* Command-line editing */
Kim Phillips5be58f52010-07-14 19:47:18 -0500736#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200737#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
738#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
Kumar Gala9490a7f2008-07-25 13:31:05 -0500739#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200740#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
Kumar Gala9490a7f2008-07-25 13:31:05 -0500741#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200742#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
Kumar Gala9490a7f2008-07-25 13:31:05 -0500743#endif
Mingkai Hu07355702009-09-23 15:19:32 +0800744#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE \
745 + sizeof(CONFIG_SYS_PROMPT) + 16) /* Print Buffer Size */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200746#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
Mingkai Hu07355702009-09-23 15:19:32 +0800747#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200748#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
Kumar Gala9490a7f2008-07-25 13:31:05 -0500749
750/*
751 * For booting Linux, the board info and command line data
Kumar Galaa832ac42011-04-28 10:13:41 -0500752 * have to be in the first 64 MB of memory, since this is
Kumar Gala9490a7f2008-07-25 13:31:05 -0500753 * the maximum mapped by the Linux kernel during initialization.
754 */
Kumar Galaa832ac42011-04-28 10:13:41 -0500755#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux */
756#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
Kumar Gala9490a7f2008-07-25 13:31:05 -0500757
Kumar Gala9490a7f2008-07-25 13:31:05 -0500758#if defined(CONFIG_CMD_KGDB)
759#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
760#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
761#endif
762
763/*
764 * Environment Configuration
765 */
766
767/* The mac addresses for all ethernet interface */
768#if defined(CONFIG_TSEC_ENET)
769#define CONFIG_HAS_ETH0
770#define CONFIG_ETHADDR 00:E0:0C:02:00:FD
771#define CONFIG_HAS_ETH1
772#define CONFIG_ETH1ADDR 00:E0:0C:02:01:FD
773#define CONFIG_HAS_ETH2
774#define CONFIG_ETH2ADDR 00:E0:0C:02:02:FD
775#define CONFIG_HAS_ETH3
776#define CONFIG_ETH3ADDR 00:E0:0C:02:03:FD
777#endif
778
779#define CONFIG_IPADDR 192.168.1.254
780
781#define CONFIG_HOSTNAME unknown
Joe Hershberger8b3637c2011-10-13 13:03:47 +0000782#define CONFIG_ROOTPATH "/opt/nfsroot"
Joe Hershbergerb3f44c22011-10-13 13:03:48 +0000783#define CONFIG_BOOTFILE "uImage"
Mingkai Hu07355702009-09-23 15:19:32 +0800784#define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
Kumar Gala9490a7f2008-07-25 13:31:05 -0500785
786#define CONFIG_SERVERIP 192.168.1.1
787#define CONFIG_GATEWAYIP 192.168.1.1
788#define CONFIG_NETMASK 255.255.255.0
789
790/* default location for tftp and bootm */
791#define CONFIG_LOADADDR 1000000
792
793#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
794#undef CONFIG_BOOTARGS /* the boot command will set bootargs */
795
796#define CONFIG_BAUDRATE 115200
797
798#define CONFIG_EXTRA_ENV_SETTINGS \
799 "netdev=eth0\0" \
800 "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \
801 "tftpflash=tftpboot $loadaddr $uboot; " \
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200802 "protect off " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
803 "erase " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
804 "cp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize; " \
805 "protect on " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
806 "cmp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize\0" \
Kumar Gala9490a7f2008-07-25 13:31:05 -0500807 "consoledev=ttyS0\0" \
808 "ramdiskaddr=2000000\0" \
809 "ramdiskfile=8536ds/ramdisk.uboot\0" \
810 "fdtaddr=c00000\0" \
811 "fdtfile=8536ds/mpc8536ds.dtb\0" \
Vivek Mahajan4bc6eb72009-05-25 17:23:18 +0530812 "bdev=sda3\0" \
Ramneek Mehresh68d42302011-06-07 10:10:43 +0000813 "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0"
Kumar Gala9490a7f2008-07-25 13:31:05 -0500814
815#define CONFIG_HDBOOT \
816 "setenv bootargs root=/dev/$bdev rw " \
817 "console=$consoledev,$baudrate $othbootargs;" \
818 "tftp $loadaddr $bootfile;" \
819 "tftp $fdtaddr $fdtfile;" \
820 "bootm $loadaddr - $fdtaddr"
821
822#define CONFIG_NFSBOOTCOMMAND \
823 "setenv bootargs root=/dev/nfs rw " \
824 "nfsroot=$serverip:$rootpath " \
825 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
826 "console=$consoledev,$baudrate $othbootargs;" \
827 "tftp $loadaddr $bootfile;" \
828 "tftp $fdtaddr $fdtfile;" \
829 "bootm $loadaddr - $fdtaddr"
830
831#define CONFIG_RAMBOOTCOMMAND \
832 "setenv bootargs root=/dev/ram rw " \
833 "console=$consoledev,$baudrate $othbootargs;" \
834 "tftp $ramdiskaddr $ramdiskfile;" \
835 "tftp $loadaddr $bootfile;" \
836 "tftp $fdtaddr $fdtfile;" \
837 "bootm $loadaddr $ramdiskaddr $fdtaddr"
838
839#define CONFIG_BOOTCOMMAND CONFIG_HDBOOT
840
841#endif /* __CONFIG_H */