blob: 59231d340a54d279526981dce7af6d2879d277b8 [file] [log] [blame]
Ramon Friedc2ccc9e2019-04-27 11:15:22 +03001// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright (c) 2019
4 * Written by Ramon Fried <ramon.fried@gmail.com>
5 */
6
7#include <common.h>
8#include <dm.h>
9#include <errno.h>
10#include <pci_ep.h>
11#include <linux/sizes.h>
12#include <linux/log2.h>
13#include "pcie-cadence.h"
14
15DECLARE_GLOBAL_DATA_PTR;
16
17static int cdns_write_header(struct udevice *dev, uint fn,
18 struct pci_ep_header *hdr)
19{
20 struct cdns_pcie *pcie = dev_get_priv(dev);
21
22 cdns_pcie_ep_fn_writew(pcie, fn, PCI_DEVICE_ID, hdr->deviceid);
23 cdns_pcie_ep_fn_writeb(pcie, fn, PCI_REVISION_ID, hdr->revid);
24 cdns_pcie_ep_fn_writeb(pcie, fn, PCI_CLASS_PROG,
25 hdr->progif_code);
26 cdns_pcie_ep_fn_writew(pcie, fn, PCI_CLASS_DEVICE,
27 hdr->subclass_code |
28 hdr->baseclass_code << 8);
29 cdns_pcie_ep_fn_writeb(pcie, fn, PCI_CACHE_LINE_SIZE,
30 hdr->cache_line_size);
31 cdns_pcie_ep_fn_writew(pcie, fn, PCI_SUBSYSTEM_ID,
32 hdr->subsys_id);
33 cdns_pcie_ep_fn_writeb(pcie, fn, PCI_INTERRUPT_PIN,
34 hdr->interrupt_pin);
35
36 /*
37 * Vendor ID can only be modified from function 0, all other functions
38 * use the same vendor ID as function 0.
39 */
40 if (fn == 0) {
41 /* Update the vendor IDs. */
42 u32 id = CDNS_PCIE_LM_ID_VENDOR(hdr->vendorid) |
43 CDNS_PCIE_LM_ID_SUBSYS(hdr->subsys_vendor_id);
44
45 cdns_pcie_writel(pcie, CDNS_PCIE_LM_ID, id);
46 }
47
48 return 0;
49}
50
51static int cdns_set_bar(struct udevice *dev, uint fn, struct pci_bar *ep_bar)
52{
53 struct cdns_pcie *pcie = dev_get_priv(dev);
54 dma_addr_t bar_phys = ep_bar->phys_addr;
55 enum pci_barno bar = ep_bar->barno;
56 int flags = ep_bar->flags;
57 u32 addr0, addr1, reg, cfg, b, aperture, ctrl;
58 u64 sz;
59
60 /* BAR size is 2^(aperture + 7) */
61 sz = max_t(size_t, ep_bar->size, CDNS_PCIE_EP_MIN_APERTURE);
62 /*
63 * roundup_pow_of_two() returns an unsigned long, which is not suited
64 * for 64bit values.
65 */
66 sz = 1ULL << fls64(sz - 1);
67 aperture = ilog2(sz) - 7; /* 128B -> 0, 256B -> 1, 512B -> 2, ... */
68
69 if ((flags & PCI_BASE_ADDRESS_SPACE) == PCI_BASE_ADDRESS_SPACE_IO) {
70 ctrl = CDNS_PCIE_LM_BAR_CFG_CTRL_IO_32BITS;
71 } else {
72 bool is_prefetch = !!(flags & PCI_BASE_ADDRESS_MEM_PREFETCH);
73 bool is_64bits = (sz > SZ_2G) |
74 !!(ep_bar->flags & PCI_BASE_ADDRESS_MEM_TYPE_64);
75
76 if (is_64bits && (bar & 1))
77 return -EINVAL;
78
79 if (is_64bits && !(flags & PCI_BASE_ADDRESS_MEM_TYPE_64))
80 ep_bar->flags |= PCI_BASE_ADDRESS_MEM_TYPE_64;
81
82 if (is_64bits && is_prefetch)
83 ctrl = CDNS_PCIE_LM_BAR_CFG_CTRL_PREFETCH_MEM_64BITS;
84 else if (is_prefetch)
85 ctrl = CDNS_PCIE_LM_BAR_CFG_CTRL_PREFETCH_MEM_32BITS;
86 else if (is_64bits)
87 ctrl = CDNS_PCIE_LM_BAR_CFG_CTRL_MEM_64BITS;
88 else
89 ctrl = CDNS_PCIE_LM_BAR_CFG_CTRL_MEM_32BITS;
90 }
91
92 addr0 = lower_32_bits(bar_phys);
93 addr1 = upper_32_bits(bar_phys);
94 cdns_pcie_writel(pcie, CDNS_PCIE_AT_IB_EP_FUNC_BAR_ADDR0(fn, bar),
95 addr0);
96 cdns_pcie_writel(pcie, CDNS_PCIE_AT_IB_EP_FUNC_BAR_ADDR1(fn, bar),
97 addr1);
98
99 if (bar < BAR_4) {
100 reg = CDNS_PCIE_LM_EP_FUNC_BAR_CFG0(fn);
101 b = bar;
102 } else {
103 reg = CDNS_PCIE_LM_EP_FUNC_BAR_CFG1(fn);
104 b = bar - BAR_4;
105 }
106
107 cfg = cdns_pcie_readl(pcie, reg);
108 cfg &= ~(CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_APERTURE_MASK(b) |
109 CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_CTRL_MASK(b));
110 cfg |= (CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_APERTURE(b, aperture) |
111 CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_CTRL(b, ctrl));
112 cdns_pcie_writel(pcie, reg, cfg);
113
114 return 0;
115}
116
117static int cdns_set_msi(struct udevice *dev, uint fn, uint mmc)
118{
119 struct cdns_pcie *pcie = dev_get_priv(dev);
120 u32 cap = CDNS_PCIE_EP_FUNC_MSI_CAP_OFFSET;
121
122 /*
123 * Set the Multiple Message Capable bitfield into the Message Control
124 * register.
125 */
126 u16 flags;
127
128 flags = cdns_pcie_ep_fn_readw(pcie, fn, cap + PCI_MSI_FLAGS);
129 flags = (flags & ~PCI_MSI_FLAGS_QMASK) | (mmc << 1);
130 flags |= PCI_MSI_FLAGS_64BIT;
131 flags &= ~PCI_MSI_FLAGS_MASKBIT;
132 cdns_pcie_ep_fn_writew(pcie, fn, cap + PCI_MSI_FLAGS, flags);
133
134 return 0;
135}
136
137static struct pci_ep_ops cdns_pci_ep_ops = {
138 .write_header = cdns_write_header,
139 .set_bar = cdns_set_bar,
140 .set_msi = cdns_set_msi,
141};
142
143static int cdns_pci_ep_probe(struct udevice *dev)
144{
145 struct cdns_pcie *pdata = dev_get_priv(dev);
146
147 pdata->reg_base = (void __iomem *)devfdt_get_addr(dev);
148 if (!pdata->reg_base)
149 return -ENOMEM;
150
151 pdata->max_functions = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
152 "max-functions", 1);
153 pdata->max_regions = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
154 "cdns,max-outbound-regions", 8);
155
156 return 0;
157}
158
159static int cdns_pci_ep_remove(struct udevice *dev)
160{
161 return 0;
162}
163
164const struct udevice_id cadence_pci_ep_of_match[] = {
165 { .compatible = "cdns,cdns-pcie-ep" },
166 { }
167};
168
169U_BOOT_DRIVER(cdns_pcie) = {
170 .name = "cdns,pcie-ep",
171 .id = UCLASS_PCI_EP,
172 .of_match = cadence_pci_ep_of_match,
173 .ops = &cdns_pci_ep_ops,
174 .probe = cdns_pci_ep_probe,
175 .remove = cdns_pci_ep_remove,
176 .priv_auto_alloc_size = sizeof(struct cdns_pcie),
177};