blob: fc8a3ec7dcbff097d264711df2ebb648bc489aeb [file] [log] [blame]
Stefan Roesedd580802014-10-22 12:13:18 +02001/*
Stefan Roesec4be10b2015-12-03 12:39:45 +01002 * Copyright (C) 2014-2015 Stefan Roese <sr@denx.de>
Stefan Roesedd580802014-10-22 12:13:18 +02003 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6
7#ifndef _CONFIG_DB_MV7846MP_GP_H
8#define _CONFIG_DB_MV7846MP_GP_H
9
10/*
11 * High Level Configuration Options (easy to change)
12 */
Stefan Roese25541672015-01-19 11:33:46 +010013#define CONFIG_DB_784MP_GP /* Board target name for DDR training */
14
Stefan Roesedd580802014-10-22 12:13:18 +020015#define CONFIG_DISPLAY_BOARDINFO_LATE
16
Stefan Roese2923c2d2015-08-06 14:27:36 +020017/*
18 * TEXT_BASE needs to be below 16MiB, since this area is scrubbed
19 * for DDR ECC byte filling in the SPL before loading the main
20 * U-Boot into it.
21 */
22#define CONFIG_SYS_TEXT_BASE 0x00800000
Stefan Roesedd580802014-10-22 12:13:18 +020023#define CONFIG_SYS_TCLK 250000000 /* 250MHz */
24
25/*
26 * Commands configuration
27 */
Stefan Roesedd580802014-10-22 12:13:18 +020028#define CONFIG_CMD_ENV
Stefan Roesed6b63032015-07-23 10:26:18 +020029#define CONFIG_CMD_NAND
Stefan Roese41e705a2015-08-11 09:36:15 +020030#define CONFIG_CMD_PCI
Stefan Roesec4be10b2015-12-03 12:39:45 +010031#define CONFIG_CMD_SATA
Stefan Roesedd580802014-10-22 12:13:18 +020032
33/* I2C */
34#define CONFIG_SYS_I2C
35#define CONFIG_SYS_I2C_MVTWSI
Paul Kocialkowskidd822422015-04-10 23:09:51 +020036#define CONFIG_I2C_MVTWSI_BASE0 MVEBU_TWSI_BASE
Stefan Roesedd580802014-10-22 12:13:18 +020037#define CONFIG_SYS_I2C_SLAVE 0x0
38#define CONFIG_SYS_I2C_SPEED 100000
39
Stefan Roese49114c82015-07-22 18:05:43 +020040/* USB/EHCI configuration */
Stefan Roese49114c82015-07-22 18:05:43 +020041#define CONFIG_EHCI_IS_TDI
Anton Schubert8a333712015-07-23 15:02:09 +020042#define CONFIG_USB_MAX_CONTROLLER_COUNT 3
Stefan Roese49114c82015-07-22 18:05:43 +020043
Stefan Roesedd580802014-10-22 12:13:18 +020044/* SPI NOR flash default params, used by sf commands */
45#define CONFIG_SF_DEFAULT_SPEED 1000000
46#define CONFIG_SF_DEFAULT_MODE SPI_MODE_3
Stefan Roesedd580802014-10-22 12:13:18 +020047
48/* Environment in SPI NOR flash */
49#define CONFIG_ENV_IS_IN_SPI_FLASH
50#define CONFIG_ENV_OFFSET (1 << 20) /* 1MiB in */
51#define CONFIG_ENV_SIZE (64 << 10) /* 64KiB */
52#define CONFIG_ENV_SECT_SIZE (64 << 10) /* 64KiB sectors */
53
54#define CONFIG_PHY_MARVELL /* there is a marvell phy */
Stefan Roesedd580802014-10-22 12:13:18 +020055#define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */
Stefan Roesedd580802014-10-22 12:13:18 +020056
Stefan Roesedd580802014-10-22 12:13:18 +020057#define CONFIG_SYS_ALT_MEMTEST
58
Anton Schuberte863f7f2015-07-15 14:50:05 +020059/* SATA support */
Stefan Roesec4be10b2015-12-03 12:39:45 +010060#define CONFIG_SYS_SATA_MAX_DEVICE 2
61#define CONFIG_SATA_MV
62#define CONFIG_LIBATA
63#define CONFIG_LBA48
Anton Schuberte863f7f2015-07-15 14:50:05 +020064
Stefan Roese8c822822015-12-03 12:39:45 +010065/* Additional FS support/configuration */
66#define CONFIG_SUPPORT_VFAT
67
Stefan Roese41e705a2015-08-11 09:36:15 +020068/* PCIe support */
Stefan Roese64512232015-11-25 07:37:00 +010069#ifndef CONFIG_SPL_BUILD
Stefan Roese41e705a2015-08-11 09:36:15 +020070#define CONFIG_PCI_MVEBU
Stefan Roese41e705a2015-08-11 09:36:15 +020071#define CONFIG_PCI_SCAN_SHOW
Stefan Roese64512232015-11-25 07:37:00 +010072#endif
Stefan Roese41e705a2015-08-11 09:36:15 +020073
Stefan Roesed6b63032015-07-23 10:26:18 +020074/* NAND */
75#define CONFIG_SYS_NAND_USE_FLASH_BBT
76#define CONFIG_SYS_NAND_ONFI_DETECTION
77
Stefan Roesedd580802014-10-22 12:13:18 +020078/*
79 * mv-common.h should be defined after CMD configs since it used them
80 * to enable certain macros
81 */
82#include "mv-common.h"
83
Stefan Roese25541672015-01-19 11:33:46 +010084/*
85 * Memory layout while starting into the bin_hdr via the
86 * BootROM:
87 *
88 * 0x4000.4000 - 0x4003.4000 headers space (192KiB)
89 * 0x4000.4030 bin_hdr start address
90 * 0x4003.4000 - 0x4004.7c00 BootROM memory allocations (15KiB)
91 * 0x4007.fffc BootROM stack top
92 *
93 * The address space between 0x4007.fffc and 0x400f.fff is not locked in
94 * L2 cache thus cannot be used.
95 */
96
97/* SPL */
98/* Defines for SPL */
99#define CONFIG_SPL_FRAMEWORK
100#define CONFIG_SPL_TEXT_BASE 0x40004030
101#define CONFIG_SPL_MAX_SIZE ((128 << 10) - 0x4030)
102
103#define CONFIG_SPL_BSS_START_ADDR (0x40000000 + (128 << 10))
104#define CONFIG_SPL_BSS_MAX_SIZE (16 << 10)
105
Stefan Roese64512232015-11-25 07:37:00 +0100106#ifdef CONFIG_SPL_BUILD
107#define CONFIG_SYS_MALLOC_SIMPLE
108#endif
Stefan Roese25541672015-01-19 11:33:46 +0100109
110#define CONFIG_SPL_STACK (0x40000000 + ((192 - 16) << 10))
111#define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4)
112
Stefan Roese25541672015-01-19 11:33:46 +0100113/* SPL related SPI defines */
Stefan Roese25541672015-01-19 11:33:46 +0100114#define CONFIG_SPL_SPI_LOAD
Stefan Roese25541672015-01-19 11:33:46 +0100115#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000
Stefan Roese2bd87112015-08-03 12:13:09 +0200116#define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_SPI_U_BOOT_OFFS
Stefan Roese25541672015-01-19 11:33:46 +0100117
118/* Enable DDR support in SPL (DDR3 training from Marvell bin_hdr) */
Stefan Roese25541672015-01-19 11:33:46 +0100119#define CONFIG_SPD_EEPROM 0x4e
Stefan Roese698ffab2015-12-10 15:02:38 +0100120#define CONFIG_BOARD_ECC_SUPPORT /* this board supports ECC */
Stefan Roese25541672015-01-19 11:33:46 +0100121
Stefan Roesedd580802014-10-22 12:13:18 +0200122#endif /* _CONFIG_DB_MV7846MP_GP_H */