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Michael Schwingen81b20cc2007-12-07 23:35:02 +01001/*
2 * (C) Copyright 2007
3 * Michael Schwingen, <michael@schwingen.org>
4 *
5 * based in great part on jedec_probe.c from linux kernel:
6 * (C) 2000 Red Hat. GPL'd.
7 * Occasionally maintained by Thayne Harbaugh tharbaugh at lnxi dot com
8 *
9 * See file CREDITS for list of people who contributed to this
10 * project.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 * MA 02111-1307 USA
26 *
27 */
28
29/* The DEBUG define must be before common to enable debugging */
30/*#define DEBUG*/
31
32#include <common.h>
33#include <asm/processor.h>
34#include <asm/io.h>
35#include <asm/byteorder.h>
36#include <environment.h>
37
38#define P_ID_AMD_STD CFI_CMDSET_AMD_LEGACY
39
40/* Manufacturers */
41#define MANUFACTURER_AMD 0x0001
42#define MANUFACTURER_SST 0x00BF
43
44/* AMD */
45#define AM29DL800BB 0x22C8
46#define AM29DL800BT 0x224A
47
48#define AM29F800BB 0x2258
49#define AM29F800BT 0x22D6
50#define AM29LV400BB 0x22BA
51#define AM29LV400BT 0x22B9
52#define AM29LV800BB 0x225B
53#define AM29LV800BT 0x22DA
54#define AM29LV160DT 0x22C4
55#define AM29LV160DB 0x2249
56#define AM29F017D 0x003D
57#define AM29F016D 0x00AD
58#define AM29F080 0x00D5
59#define AM29F040 0x00A4
60#define AM29LV040B 0x004F
61#define AM29F032B 0x0041
62#define AM29F002T 0x00B0
63
64/* SST */
65#define SST39LF800 0x2781
66#define SST39LF160 0x2782
67#define SST39VF1601 0x234b
68#define SST39LF512 0x00D4
69#define SST39LF010 0x00D5
70#define SST39LF020 0x00D6
71#define SST39LF040 0x00D7
72#define SST39SF010A 0x00B5
73#define SST39SF020A 0x00B6
74
75
76/*
77 * Unlock address sets for AMD command sets.
78 * Intel command sets use the MTD_UADDR_UNNECESSARY.
79 * Each identifier, except MTD_UADDR_UNNECESSARY, and
80 * MTD_UADDR_NO_SUPPORT must be defined below in unlock_addrs[].
81 * MTD_UADDR_NOT_SUPPORTED must be 0 so that structure
82 * initialization need not require initializing all of the
83 * unlock addresses for all bit widths.
84 */
85enum uaddr {
86 MTD_UADDR_NOT_SUPPORTED = 0, /* data width not supported */
87 MTD_UADDR_0x0555_0x02AA,
88 MTD_UADDR_0x0555_0x0AAA,
89 MTD_UADDR_0x5555_0x2AAA,
90 MTD_UADDR_0x0AAA_0x0555,
91 MTD_UADDR_DONT_CARE, /* Requires an arbitrary address */
92 MTD_UADDR_UNNECESSARY, /* Does not require any address */
93};
94
95
96struct unlock_addr {
97 u32 addr1;
98 u32 addr2;
99};
100
101
102/*
103 * I don't like the fact that the first entry in unlock_addrs[]
104 * exists, but is for MTD_UADDR_NOT_SUPPORTED - and, therefore,
105 * should not be used. The problem is that structures with
106 * initializers have extra fields initialized to 0. It is _very_
107 * desireable to have the unlock address entries for unsupported
108 * data widths automatically initialized - that means that
109 * MTD_UADDR_NOT_SUPPORTED must be 0 and the first entry here
110 * must go unused.
111 */
112static const struct unlock_addr unlock_addrs[] = {
113 [MTD_UADDR_NOT_SUPPORTED] = {
114 .addr1 = 0xffff,
115 .addr2 = 0xffff
116 },
117
118 [MTD_UADDR_0x0555_0x02AA] = {
119 .addr1 = 0x0555,
120 .addr2 = 0x02aa
121 },
122
123 [MTD_UADDR_0x0555_0x0AAA] = {
124 .addr1 = 0x0555,
125 .addr2 = 0x0aaa
126 },
127
128 [MTD_UADDR_0x5555_0x2AAA] = {
129 .addr1 = 0x5555,
130 .addr2 = 0x2aaa
131 },
132
133 [MTD_UADDR_0x0AAA_0x0555] = {
134 .addr1 = 0x0AAA,
135 .addr2 = 0x0555
136 },
137
138 [MTD_UADDR_DONT_CARE] = {
139 .addr1 = 0x0000, /* Doesn't matter which address */
140 .addr2 = 0x0000 /* is used - must be last entry */
141 },
142
143 [MTD_UADDR_UNNECESSARY] = {
144 .addr1 = 0x0000,
145 .addr2 = 0x0000
146 }
147};
148
149
150struct amd_flash_info {
151 const __u16 mfr_id;
152 const __u16 dev_id;
153 const char *name;
154 const int DevSize;
155 const int NumEraseRegions;
156 const int CmdSet;
157 const __u8 uaddr[4]; /* unlock addrs for 8, 16, 32, 64 */
158 const ulong regions[6];
159};
160
161#define ERASEINFO(size,blocks) (size<<8)|(blocks-1)
162
163#define SIZE_64KiB 16
164#define SIZE_128KiB 17
165#define SIZE_256KiB 18
166#define SIZE_512KiB 19
167#define SIZE_1MiB 20
168#define SIZE_2MiB 21
169#define SIZE_4MiB 22
170#define SIZE_8MiB 23
171
172static const struct amd_flash_info jedec_table[] = {
173#ifdef CFG_FLASH_LEGACY_256Kx8
174 {
175 .mfr_id = MANUFACTURER_SST,
176 .dev_id = SST39LF020,
177 .name = "SST 39LF020",
Stefan Roese9692c272007-12-08 08:25:09 +0100178 .uaddr = {
Michael Schwingen81b20cc2007-12-07 23:35:02 +0100179 [0] = MTD_UADDR_0x5555_0x2AAA /* x8 */
180 },
181 .DevSize = SIZE_256KiB,
182 .CmdSet = P_ID_AMD_STD,
183 .NumEraseRegions= 1,
184 .regions = {
185 ERASEINFO(0x01000,64),
186 }
Stefan Roese9692c272007-12-08 08:25:09 +0100187 },
Michael Schwingen81b20cc2007-12-07 23:35:02 +0100188#endif
189#ifdef CFG_FLASH_LEGACY_512Kx8
190 {
191 .mfr_id = MANUFACTURER_AMD,
192 .dev_id = AM29LV040B,
193 .name = "AMD AM29LV040B",
194 .uaddr = {
195 [0] = MTD_UADDR_0x0555_0x02AA /* x8 */
196 },
197 .DevSize = SIZE_512KiB,
198 .CmdSet = P_ID_AMD_STD,
199 .NumEraseRegions= 1,
200 .regions = {
201 ERASEINFO(0x10000,8),
202 }
203 },
204 {
205 .mfr_id = MANUFACTURER_SST,
206 .dev_id = SST39LF040,
207 .name = "SST 39LF040",
Stefan Roese9692c272007-12-08 08:25:09 +0100208 .uaddr = {
Michael Schwingen81b20cc2007-12-07 23:35:02 +0100209 [0] = MTD_UADDR_0x5555_0x2AAA /* x8 */
210 },
211 .DevSize = SIZE_512KiB,
212 .CmdSet = P_ID_AMD_STD,
213 .NumEraseRegions= 1,
214 .regions = {
215 ERASEINFO(0x01000,128),
216 }
Stefan Roese9692c272007-12-08 08:25:09 +0100217 },
Michael Schwingen81b20cc2007-12-07 23:35:02 +0100218#endif
219};
220
Michael Schwingen81b20cc2007-12-07 23:35:02 +0100221static inline void fill_info(flash_info_t *info, const struct amd_flash_info *jedec_entry, ulong base)
222{
223 int i,j;
224 int sect_cnt;
225 int size_ratio;
226 int total_size;
227 enum uaddr uaddr_idx;
228
229 size_ratio = info->portwidth / info->chipwidth;
230
231 debug("Found JEDEC Flash: %s\n", jedec_entry->name);
232 info->vendor = jedec_entry->CmdSet;
233 /* Todo: do we need device-specific timeouts? */
234 info->erase_blk_tout = 30000;
235 info->buffer_write_tout = 1000;
236 info->write_tout = 100;
237 info->name = jedec_entry->name;
238
239 /* copy unlock addresses from device table to CFI info struct. This
240 is just here because the addresses are in the table anyway - if
241 the flash is not detected due to wrong unlock addresses,
242 flash_detect_legacy would have to try all of them before we even
243 get here. */
244 switch(info->chipwidth) {
245 case FLASH_CFI_8BIT:
246 uaddr_idx = jedec_entry->uaddr[0];
247 break;
248 case FLASH_CFI_16BIT:
249 uaddr_idx = jedec_entry->uaddr[1];
250 break;
251 case FLASH_CFI_32BIT:
252 uaddr_idx = jedec_entry->uaddr[2];
253 break;
254 default:
255 uaddr_idx = MTD_UADDR_NOT_SUPPORTED;
256 break;
257 }
258
259 debug("unlock address index %d\n", uaddr_idx);
260 info->addr_unlock1 = unlock_addrs[uaddr_idx].addr1;
261 info->addr_unlock2 = unlock_addrs[uaddr_idx].addr2;
262 debug("unlock addresses are 0x%x/0x%x\n", info->addr_unlock1, info->addr_unlock2);
263
264 sect_cnt = 0;
265 total_size = 0;
266 for (i = 0; i < jedec_entry->NumEraseRegions; i++) {
267 ulong erase_region_size = jedec_entry->regions[i] >> 8;
268 ulong erase_region_count = (jedec_entry->regions[i] & 0xff) + 1;
269
270 total_size += erase_region_size * erase_region_count;
271 debug ("erase_region_count = %d erase_region_size = %d\n",
272 erase_region_count, erase_region_size);
273 for (j = 0; j < erase_region_count; j++) {
274 if (sect_cnt >= CFG_MAX_FLASH_SECT) {
275 printf("ERROR: too many flash sectors\n");
276 break;
277 }
278 info->start[sect_cnt] = base;
279 base += (erase_region_size * size_ratio);
280 sect_cnt++;
281 }
282 }
283 info->sector_count = sect_cnt;
284 info->size = total_size * size_ratio;
285}
286
287/*-----------------------------------------------------------------------
288 * match jedec ids against table. If a match is found, fill flash_info entry
289 */
290int jedec_flash_match(flash_info_t *info, ulong base)
291{
292 int ret = 0;
293 int i;
294 ulong mask = 0xFFFF;
295 if (info->chipwidth == 1)
296 mask = 0xFF;
297
298 for (i = 0; i < ARRAY_SIZE(jedec_table); i++) {
299 if ((jedec_table[i].mfr_id & mask) == (info->manufacturer_id & mask) &&
300 (jedec_table[i].dev_id & mask) == (info->device_id & mask)) {
301 fill_info(info, &jedec_table[i], base);
302 ret = 1;
303 break;
304 }
305 }
306 return ret;
307}