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Matt Porter1d0933e2013-10-07 15:53:02 +05301/*
2 * TI QSPI driver
3 *
4 * Copyright (C) 2013, Texas Instruments, Incorporated
5 *
6 * SPDX-License-Identifier: GPL-2.0+
7 */
8
9#include <common.h>
10#include <asm/io.h>
11#include <asm/arch/omap.h>
12#include <malloc.h>
13#include <spi.h>
Mugunthan V N106f8132015-12-23 20:39:40 +053014#include <dm.h>
Sourav Poddar570533b2013-12-21 12:50:09 +053015#include <asm/gpio.h>
16#include <asm/omap_gpio.h>
Vignesh R8ddd9c42015-08-17 15:20:13 +053017#include <asm/omap_common.h>
18#include <asm/ti-common/ti-edma3.h>
Matt Porter1d0933e2013-10-07 15:53:02 +053019
Mugunthan V N106f8132015-12-23 20:39:40 +053020DECLARE_GLOBAL_DATA_PTR;
21
Matt Porter1d0933e2013-10-07 15:53:02 +053022/* ti qpsi register bit masks */
23#define QSPI_TIMEOUT 2000000
24#define QSPI_FCLK 192000000
25/* clock control */
Jagan Teki847720c2015-10-23 01:39:20 +053026#define QSPI_CLK_EN BIT(31)
Matt Porter1d0933e2013-10-07 15:53:02 +053027#define QSPI_CLK_DIV_MAX 0xffff
28/* command */
29#define QSPI_EN_CS(n) (n << 28)
30#define QSPI_WLEN(n) ((n-1) << 19)
Jagan Teki847720c2015-10-23 01:39:20 +053031#define QSPI_3_PIN BIT(18)
32#define QSPI_RD_SNGL BIT(16)
Matt Porter1d0933e2013-10-07 15:53:02 +053033#define QSPI_WR_SNGL (2 << 16)
34#define QSPI_INVAL (4 << 16)
35#define QSPI_RD_QUAD (7 << 16)
36/* device control */
37#define QSPI_DD(m, n) (m << (3 + n*8))
38#define QSPI_CKPHA(n) (1 << (2 + n*8))
39#define QSPI_CSPOL(n) (1 << (1 + n*8))
40#define QSPI_CKPOL(n) (1 << (n*8))
41/* status */
Jagan Teki847720c2015-10-23 01:39:20 +053042#define QSPI_WC BIT(1)
43#define QSPI_BUSY BIT(0)
Matt Porter1d0933e2013-10-07 15:53:02 +053044#define QSPI_WC_BUSY (QSPI_WC | QSPI_BUSY)
45#define QSPI_XFER_DONE QSPI_WC
46#define MM_SWITCH 0x01
Mugunthan V Nec712f42015-12-23 20:39:33 +053047#define MEM_CS(cs) ((cs + 1) << 8)
Matt Porter1d0933e2013-10-07 15:53:02 +053048#define MEM_CS_UNSELECT 0xfffff0ff
Sourav Poddar570533b2013-12-21 12:50:09 +053049#define MMAP_START_ADDR_DRA 0x5c000000
50#define MMAP_START_ADDR_AM43x 0x30000000
Matt Porter1d0933e2013-10-07 15:53:02 +053051#define CORE_CTRL_IO 0x4a002558
52
53#define QSPI_CMD_READ (0x3 << 0)
Mugunthan V N106f8132015-12-23 20:39:40 +053054#define QSPI_CMD_READ_DUAL (0x6b << 0)
Vignesh R74d49bf2015-11-23 17:43:36 +053055#define QSPI_CMD_READ_QUAD (0x6c << 0)
Matt Porter1d0933e2013-10-07 15:53:02 +053056#define QSPI_CMD_READ_FAST (0x0b << 0)
Vignesh R74d49bf2015-11-23 17:43:36 +053057#define QSPI_SETUP0_NUM_A_BYTES (0x3 << 8)
Matt Porter1d0933e2013-10-07 15:53:02 +053058#define QSPI_SETUP0_NUM_D_BYTES_NO_BITS (0x0 << 10)
59#define QSPI_SETUP0_NUM_D_BYTES_8_BITS (0x1 << 10)
60#define QSPI_SETUP0_READ_NORMAL (0x0 << 12)
Mugunthan V N106f8132015-12-23 20:39:40 +053061#define QSPI_SETUP0_READ_DUAL (0x1 << 12)
Matt Porter1d0933e2013-10-07 15:53:02 +053062#define QSPI_SETUP0_READ_QUAD (0x3 << 12)
Vignesh R74d49bf2015-11-23 17:43:36 +053063#define QSPI_CMD_WRITE (0x12 << 16)
Matt Porter1d0933e2013-10-07 15:53:02 +053064#define QSPI_NUM_DUMMY_BITS (0x0 << 24)
65
66/* ti qspi register set */
67struct ti_qspi_regs {
68 u32 pid;
69 u32 pad0[3];
70 u32 sysconfig;
71 u32 pad1[3];
72 u32 int_stat_raw;
73 u32 int_stat_en;
74 u32 int_en_set;
75 u32 int_en_ctlr;
76 u32 intc_eoi;
77 u32 pad2[3];
78 u32 clk_ctrl;
79 u32 dc;
80 u32 cmd;
81 u32 status;
82 u32 data;
83 u32 setup0;
84 u32 setup1;
85 u32 setup2;
86 u32 setup3;
87 u32 memswitch;
88 u32 data1;
89 u32 data2;
90 u32 data3;
91};
92
Mugunthan V N9c425582015-12-23 20:39:34 +053093/* ti qspi priv */
94struct ti_qspi_priv {
Mugunthan V N106f8132015-12-23 20:39:40 +053095#ifndef CONFIG_DM_SPI
Matt Porter1d0933e2013-10-07 15:53:02 +053096 struct spi_slave slave;
Mugunthan V N106f8132015-12-23 20:39:40 +053097#else
98 void *memory_map;
99 uint max_hz;
100 u32 num_cs;
101#endif
Matt Porter1d0933e2013-10-07 15:53:02 +0530102 struct ti_qspi_regs *base;
Mugunthan V N22309142015-12-23 20:39:35 +0530103 void *ctrl_mod_mmap;
Matt Porter1d0933e2013-10-07 15:53:02 +0530104 unsigned int mode;
105 u32 cmd;
106 u32 dc;
107};
108
Mugunthan V N22309142015-12-23 20:39:35 +0530109static void ti_spi_set_speed(struct ti_qspi_priv *priv, uint hz)
Matt Porter1d0933e2013-10-07 15:53:02 +0530110{
Matt Porter1d0933e2013-10-07 15:53:02 +0530111 uint clk_div;
112
113 debug("ti_spi_set_speed: hz: %d, clock divider %d\n", hz, clk_div);
114
115 if (!hz)
116 clk_div = 0;
117 else
118 clk_div = (QSPI_FCLK / hz) - 1;
119
120 /* disable SCLK */
Mugunthan V N9c425582015-12-23 20:39:34 +0530121 writel(readl(&priv->base->clk_ctrl) & ~QSPI_CLK_EN,
122 &priv->base->clk_ctrl);
Matt Porter1d0933e2013-10-07 15:53:02 +0530123
124 /* assign clk_div values */
125 if (clk_div < 0)
126 clk_div = 0;
127 else if (clk_div > QSPI_CLK_DIV_MAX)
128 clk_div = QSPI_CLK_DIV_MAX;
129
130 /* enable SCLK */
Mugunthan V N9c425582015-12-23 20:39:34 +0530131 writel(QSPI_CLK_EN | clk_div, &priv->base->clk_ctrl);
Matt Porter1d0933e2013-10-07 15:53:02 +0530132}
133
Mugunthan V N22309142015-12-23 20:39:35 +0530134static void ti_qspi_cs_deactivate(struct ti_qspi_priv *priv)
Matt Porter1d0933e2013-10-07 15:53:02 +0530135{
Mugunthan V N9c425582015-12-23 20:39:34 +0530136 writel(priv->cmd | QSPI_INVAL, &priv->base->cmd);
Vignesh R857db482015-11-10 11:52:10 +0530137 /* dummy readl to ensure bus sync */
Mugunthan V N22309142015-12-23 20:39:35 +0530138 readl(&priv->base->cmd);
Matt Porter1d0933e2013-10-07 15:53:02 +0530139}
140
Mugunthan V N22309142015-12-23 20:39:35 +0530141static int __ti_qspi_set_mode(struct ti_qspi_priv *priv, unsigned int mode)
Matt Porter1d0933e2013-10-07 15:53:02 +0530142{
Mugunthan V N9c425582015-12-23 20:39:34 +0530143 priv->dc = 0;
Mugunthan V N22309142015-12-23 20:39:35 +0530144 if (mode & SPI_CPHA)
145 priv->dc |= QSPI_CKPHA(0);
146 if (mode & SPI_CPOL)
147 priv->dc |= QSPI_CKPOL(0);
148 if (mode & SPI_CS_HIGH)
149 priv->dc |= QSPI_CSPOL(0);
Matt Porter1d0933e2013-10-07 15:53:02 +0530150
151 return 0;
152}
153
Mugunthan V N22309142015-12-23 20:39:35 +0530154static int __ti_qspi_claim_bus(struct ti_qspi_priv *priv, int cs)
Matt Porter1d0933e2013-10-07 15:53:02 +0530155{
Mugunthan V N22309142015-12-23 20:39:35 +0530156 writel(priv->dc, &priv->base->dc);
157 writel(0, &priv->base->cmd);
158 writel(0, &priv->base->data);
Matt Porter1d0933e2013-10-07 15:53:02 +0530159
Mugunthan V N22309142015-12-23 20:39:35 +0530160 priv->dc <<= cs * 8;
161 writel(priv->dc, &priv->base->dc);
Matt Porter1d0933e2013-10-07 15:53:02 +0530162
Mugunthan V N22309142015-12-23 20:39:35 +0530163 return 0;
164}
165
166static void __ti_qspi_release_bus(struct ti_qspi_priv *priv)
167{
Mugunthan V N9c425582015-12-23 20:39:34 +0530168 writel(0, &priv->base->dc);
169 writel(0, &priv->base->cmd);
170 writel(0, &priv->base->data);
Matt Porter1d0933e2013-10-07 15:53:02 +0530171}
172
Mugunthan V N22309142015-12-23 20:39:35 +0530173static void ti_qspi_ctrl_mode_mmap(void *ctrl_mod_mmap, int cs, bool enable)
Matt Porter1d0933e2013-10-07 15:53:02 +0530174{
Mugunthan V N22309142015-12-23 20:39:35 +0530175 u32 val;
176
177 val = readl(ctrl_mod_mmap);
178 if (enable)
179 val |= MEM_CS(cs);
180 else
181 val &= MEM_CS_UNSELECT;
182 writel(val, ctrl_mod_mmap);
183}
184
185static int __ti_qspi_xfer(struct ti_qspi_priv *priv, unsigned int bitlen,
186 const void *dout, void *din, unsigned long flags,
187 u32 cs)
188{
Matt Porter1d0933e2013-10-07 15:53:02 +0530189 uint words = bitlen >> 3; /* fixed 8-bit word length */
190 const uchar *txp = dout;
191 uchar *rxp = din;
192 uint status;
Sourav Poddar570533b2013-12-21 12:50:09 +0530193 int timeout;
194
Matt Porter1d0933e2013-10-07 15:53:02 +0530195 /* Setup mmap flags */
196 if (flags & SPI_XFER_MMAP) {
Mugunthan V N9c425582015-12-23 20:39:34 +0530197 writel(MM_SWITCH, &priv->base->memswitch);
Mugunthan V N22309142015-12-23 20:39:35 +0530198 if (priv->ctrl_mod_mmap)
199 ti_qspi_ctrl_mode_mmap(priv->ctrl_mod_mmap, cs, true);
Matt Porter1d0933e2013-10-07 15:53:02 +0530200 return 0;
201 } else if (flags & SPI_XFER_MMAP_END) {
Mugunthan V N9c425582015-12-23 20:39:34 +0530202 writel(~MM_SWITCH, &priv->base->memswitch);
Mugunthan V N22309142015-12-23 20:39:35 +0530203 if (priv->ctrl_mod_mmap)
204 ti_qspi_ctrl_mode_mmap(priv->ctrl_mod_mmap, cs, false);
Matt Porter1d0933e2013-10-07 15:53:02 +0530205 return 0;
206 }
207
208 if (bitlen == 0)
209 return -1;
210
211 if (bitlen % 8) {
212 debug("spi_xfer: Non byte aligned SPI transfer\n");
213 return -1;
214 }
215
216 /* Setup command reg */
Mugunthan V N9c425582015-12-23 20:39:34 +0530217 priv->cmd = 0;
218 priv->cmd |= QSPI_WLEN(8);
Mugunthan V N22309142015-12-23 20:39:35 +0530219 priv->cmd |= QSPI_EN_CS(cs);
Mugunthan V N9c425582015-12-23 20:39:34 +0530220 if (priv->mode & SPI_3WIRE)
221 priv->cmd |= QSPI_3_PIN;
222 priv->cmd |= 0xfff;
Matt Porter1d0933e2013-10-07 15:53:02 +0530223
Sourav Poddarbb7cd0d2013-12-21 12:50:10 +0530224/* FIXME: This delay is required for successfull
225 * completion of read/write/erase. Once its root
226 * caused, it will be remove from the driver.
227 */
228#ifdef CONFIG_AM43XX
229 udelay(100);
230#endif
Matt Porter1d0933e2013-10-07 15:53:02 +0530231 while (words--) {
232 if (txp) {
233 debug("tx cmd %08x dc %08x data %02x\n",
Mugunthan V N9c425582015-12-23 20:39:34 +0530234 priv->cmd | QSPI_WR_SNGL, priv->dc, *txp);
235 writel(*txp++, &priv->base->data);
236 writel(priv->cmd | QSPI_WR_SNGL,
237 &priv->base->cmd);
238 status = readl(&priv->base->status);
Matt Porter1d0933e2013-10-07 15:53:02 +0530239 timeout = QSPI_TIMEOUT;
240 while ((status & QSPI_WC_BUSY) != QSPI_XFER_DONE) {
241 if (--timeout < 0) {
242 printf("spi_xfer: TX timeout!\n");
243 return -1;
244 }
Mugunthan V N9c425582015-12-23 20:39:34 +0530245 status = readl(&priv->base->status);
Matt Porter1d0933e2013-10-07 15:53:02 +0530246 }
247 debug("tx done, status %08x\n", status);
248 }
249 if (rxp) {
Mugunthan V N9c425582015-12-23 20:39:34 +0530250 priv->cmd |= QSPI_RD_SNGL;
Matt Porter1d0933e2013-10-07 15:53:02 +0530251 debug("rx cmd %08x dc %08x\n",
Mugunthan V N9c425582015-12-23 20:39:34 +0530252 priv->cmd, priv->dc);
Poddar, Souravb545a982014-04-03 07:52:54 -0400253 #ifdef CONFIG_DRA7XX
254 udelay(500);
255 #endif
Mugunthan V N9c425582015-12-23 20:39:34 +0530256 writel(priv->cmd, &priv->base->cmd);
257 status = readl(&priv->base->status);
Matt Porter1d0933e2013-10-07 15:53:02 +0530258 timeout = QSPI_TIMEOUT;
259 while ((status & QSPI_WC_BUSY) != QSPI_XFER_DONE) {
260 if (--timeout < 0) {
261 printf("spi_xfer: RX timeout!\n");
262 return -1;
263 }
Mugunthan V N9c425582015-12-23 20:39:34 +0530264 status = readl(&priv->base->status);
Matt Porter1d0933e2013-10-07 15:53:02 +0530265 }
Mugunthan V N9c425582015-12-23 20:39:34 +0530266 *rxp++ = readl(&priv->base->data);
Matt Porter1d0933e2013-10-07 15:53:02 +0530267 debug("rx done, status %08x, read %02x\n",
268 status, *(rxp-1));
269 }
270 }
271
272 /* Terminate frame */
273 if (flags & SPI_XFER_END)
Mugunthan V N22309142015-12-23 20:39:35 +0530274 ti_qspi_cs_deactivate(priv);
Matt Porter1d0933e2013-10-07 15:53:02 +0530275
276 return 0;
277}
Vignesh R8ddd9c42015-08-17 15:20:13 +0530278
279/* TODO: control from sf layer to here through dm-spi */
Mugunthan V N518b0af2016-02-15 15:31:40 +0530280#if defined(CONFIG_TI_EDMA3) && !defined(CONFIG_DMA)
Vignesh R8ddd9c42015-08-17 15:20:13 +0530281void spi_flash_copy_mmap(void *data, void *offset, size_t len)
282{
283 unsigned int addr = (unsigned int) (data);
284 unsigned int edma_slot_num = 1;
285
286 /* Invalidate the area, so no writeback into the RAM races with DMA */
287 invalidate_dcache_range(addr, addr + roundup(len, ARCH_DMA_MINALIGN));
288
289 /* enable edma3 clocks */
290 enable_edma3_clocks();
291
292 /* Call edma3 api to do actual DMA transfer */
293 edma3_transfer(EDMA3_BASE, edma_slot_num, data, offset, len);
294
295 /* disable edma3 clocks */
296 disable_edma3_clocks();
297
298 *((unsigned int *)offset) += len;
299}
300#endif
Mugunthan V N22309142015-12-23 20:39:35 +0530301
Mugunthan V N106f8132015-12-23 20:39:40 +0530302#ifndef CONFIG_DM_SPI
303
Mugunthan V N22309142015-12-23 20:39:35 +0530304static inline struct ti_qspi_priv *to_ti_qspi_priv(struct spi_slave *slave)
305{
306 return container_of(slave, struct ti_qspi_priv, slave);
307}
308
309int spi_cs_is_valid(unsigned int bus, unsigned int cs)
310{
311 return 1;
312}
313
314void spi_cs_activate(struct spi_slave *slave)
315{
316 /* CS handled in xfer */
317 return;
318}
319
320void spi_cs_deactivate(struct spi_slave *slave)
321{
322 struct ti_qspi_priv *priv = to_ti_qspi_priv(slave);
323 ti_qspi_cs_deactivate(priv);
324}
325
326void spi_init(void)
327{
328 /* nothing to do */
329}
330
331static void ti_spi_setup_spi_register(struct ti_qspi_priv *priv)
332{
333 u32 memval = 0;
334
335#ifdef CONFIG_QSPI_QUAD_SUPPORT
336 struct spi_slave *slave = &priv->slave;
337 memval |= (QSPI_CMD_READ_QUAD | QSPI_SETUP0_NUM_A_BYTES |
338 QSPI_SETUP0_NUM_D_BYTES_8_BITS |
339 QSPI_SETUP0_READ_QUAD | QSPI_CMD_WRITE |
340 QSPI_NUM_DUMMY_BITS);
341 slave->mode_rx = SPI_RX_QUAD;
342#else
343 memval |= QSPI_CMD_READ | QSPI_SETUP0_NUM_A_BYTES |
344 QSPI_SETUP0_NUM_D_BYTES_NO_BITS |
345 QSPI_SETUP0_READ_NORMAL | QSPI_CMD_WRITE |
346 QSPI_NUM_DUMMY_BITS;
347#endif
348
349 writel(memval, &priv->base->setup0);
350}
351
352struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
353 unsigned int max_hz, unsigned int mode)
354{
355 struct ti_qspi_priv *priv;
356
357#ifdef CONFIG_AM43XX
358 gpio_request(CONFIG_QSPI_SEL_GPIO, "qspi_gpio");
359 gpio_direction_output(CONFIG_QSPI_SEL_GPIO, 1);
360#endif
361
362 priv = spi_alloc_slave(struct ti_qspi_priv, bus, cs);
363 if (!priv) {
364 printf("SPI_error: Fail to allocate ti_qspi_priv\n");
365 return NULL;
366 }
367
368 priv->base = (struct ti_qspi_regs *)QSPI_BASE;
369 priv->mode = mode;
370#if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX)
371 priv->ctrl_mod_mmap = (void *)CORE_CTRL_IO;
372 priv->slave.memory_map = (void *)MMAP_START_ADDR_DRA;
373#else
374 priv->slave.memory_map = (void *)MMAP_START_ADDR_AM43x;
375#endif
376
377 ti_spi_set_speed(priv, max_hz);
378
379#ifdef CONFIG_TI_SPI_MMAP
380 ti_spi_setup_spi_register(priv);
381#endif
382
383 return &priv->slave;
384}
385
386void spi_free_slave(struct spi_slave *slave)
387{
388 struct ti_qspi_priv *priv = to_ti_qspi_priv(slave);
389 free(priv);
390}
391
392int spi_claim_bus(struct spi_slave *slave)
393{
394 struct ti_qspi_priv *priv = to_ti_qspi_priv(slave);
395
396 debug("%s: bus:%i cs:%i\n", __func__, priv->slave.bus, priv->slave.cs);
397 __ti_qspi_set_mode(priv, priv->mode);
398 return __ti_qspi_claim_bus(priv, priv->slave.cs);
399}
400void spi_release_bus(struct spi_slave *slave)
401{
402 struct ti_qspi_priv *priv = to_ti_qspi_priv(slave);
403
404 debug("%s: bus:%i cs:%i\n", __func__, priv->slave.bus, priv->slave.cs);
405 __ti_qspi_release_bus(priv);
406}
407
408int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
409 void *din, unsigned long flags)
410{
411 struct ti_qspi_priv *priv = to_ti_qspi_priv(slave);
412
413 debug("spi_xfer: bus:%i cs:%i bitlen:%i flags:%lx\n",
414 priv->slave.bus, priv->slave.cs, bitlen, flags);
415 return __ti_qspi_xfer(priv, bitlen, dout, din, flags, priv->slave.cs);
416}
Mugunthan V N106f8132015-12-23 20:39:40 +0530417
418#else /* CONFIG_DM_SPI */
419
420static void __ti_qspi_setup_memorymap(struct ti_qspi_priv *priv,
421 struct spi_slave *slave,
422 bool enable)
423{
424 u32 memval;
425 u32 mode = slave->mode_rx & (SPI_RX_QUAD | SPI_RX_DUAL);
426
427 if (!enable) {
428 writel(0, &priv->base->setup0);
429 return;
430 }
431
432 memval = QSPI_SETUP0_NUM_A_BYTES | QSPI_CMD_WRITE | QSPI_NUM_DUMMY_BITS;
433
434 switch (mode) {
435 case SPI_RX_QUAD:
436 memval |= QSPI_CMD_READ_QUAD;
437 memval |= QSPI_SETUP0_NUM_D_BYTES_8_BITS;
438 memval |= QSPI_SETUP0_READ_QUAD;
439 slave->mode_rx = SPI_RX_QUAD;
440 break;
441 case SPI_RX_DUAL:
442 memval |= QSPI_CMD_READ_DUAL;
443 memval |= QSPI_SETUP0_NUM_D_BYTES_8_BITS;
444 memval |= QSPI_SETUP0_READ_DUAL;
445 break;
446 default:
447 memval |= QSPI_CMD_READ;
448 memval |= QSPI_SETUP0_NUM_D_BYTES_NO_BITS;
449 memval |= QSPI_SETUP0_READ_NORMAL;
450 break;
451 }
452
453 writel(memval, &priv->base->setup0);
454}
455
456
457static int ti_qspi_set_speed(struct udevice *bus, uint max_hz)
458{
459 struct ti_qspi_priv *priv = dev_get_priv(bus);
460
461 ti_spi_set_speed(priv, max_hz);
462
463 return 0;
464}
465
466static int ti_qspi_set_mode(struct udevice *bus, uint mode)
467{
468 struct ti_qspi_priv *priv = dev_get_priv(bus);
469 return __ti_qspi_set_mode(priv, mode);
470}
471
472static int ti_qspi_claim_bus(struct udevice *dev)
473{
474 struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
475 struct spi_slave *slave = dev_get_parent_priv(dev);
476 struct ti_qspi_priv *priv;
477 struct udevice *bus;
478
479 bus = dev->parent;
480 priv = dev_get_priv(bus);
481
482 if (slave_plat->cs > priv->num_cs) {
483 debug("invalid qspi chip select\n");
484 return -EINVAL;
485 }
486
487 __ti_qspi_setup_memorymap(priv, slave, true);
488
489 return __ti_qspi_claim_bus(priv, slave_plat->cs);
490}
491
492static int ti_qspi_release_bus(struct udevice *dev)
493{
494 struct spi_slave *slave = dev_get_parent_priv(dev);
495 struct ti_qspi_priv *priv;
496 struct udevice *bus;
497
498 bus = dev->parent;
499 priv = dev_get_priv(bus);
500
501 __ti_qspi_setup_memorymap(priv, slave, false);
502 __ti_qspi_release_bus(priv);
503
504 return 0;
505}
506
507static int ti_qspi_xfer(struct udevice *dev, unsigned int bitlen,
508 const void *dout, void *din, unsigned long flags)
509{
510 struct dm_spi_slave_platdata *slave = dev_get_parent_platdata(dev);
511 struct ti_qspi_priv *priv;
512 struct udevice *bus;
513
514 bus = dev->parent;
515 priv = dev_get_priv(bus);
516
517 if (slave->cs > priv->num_cs) {
518 debug("invalid qspi chip select\n");
519 return -EINVAL;
520 }
521
522 return __ti_qspi_xfer(priv, bitlen, dout, din, flags, slave->cs);
523}
524
525static int ti_qspi_probe(struct udevice *bus)
526{
527 /* Nothing to do in probe */
528 return 0;
529}
530
531static int ti_qspi_ofdata_to_platdata(struct udevice *bus)
532{
533 struct ti_qspi_priv *priv = dev_get_priv(bus);
534 const void *blob = gd->fdt_blob;
535 int node = bus->of_offset;
536 fdt_addr_t addr;
537
538 priv->base = (struct ti_qspi_regs *)dev_get_addr(bus);
539 priv->memory_map = (void *)dev_get_addr_index(bus, 1);
540 addr = dev_get_addr_index(bus, 2);
541 priv->ctrl_mod_mmap = (addr == FDT_ADDR_T_NONE) ? NULL : (void *)addr;
542
543 priv->max_hz = fdtdec_get_int(blob, node, "spi-max-frequency", -1);
544 if (priv->max_hz < 0) {
545 debug("Error: Max frequency missing\n");
546 return -ENODEV;
547 }
548 priv->num_cs = fdtdec_get_int(blob, node, "num-cs", 4);
549
550 debug("%s: regs=<0x%x>, max-frequency=%d\n", __func__,
551 (int)priv->base, priv->max_hz);
552
553 return 0;
554}
555
556static int ti_qspi_child_pre_probe(struct udevice *dev)
557{
558 struct spi_slave *slave = dev_get_parent_priv(dev);
559 struct udevice *bus = dev_get_parent(dev);
560 struct ti_qspi_priv *priv = dev_get_priv(bus);
561
562 slave->memory_map = priv->memory_map;
563 return 0;
564}
565
566static const struct dm_spi_ops ti_qspi_ops = {
567 .claim_bus = ti_qspi_claim_bus,
568 .release_bus = ti_qspi_release_bus,
569 .xfer = ti_qspi_xfer,
570 .set_speed = ti_qspi_set_speed,
571 .set_mode = ti_qspi_set_mode,
572};
573
574static const struct udevice_id ti_qspi_ids[] = {
575 { .compatible = "ti,dra7xxx-qspi" },
576 { .compatible = "ti,am4372-qspi" },
577 { }
578};
579
580U_BOOT_DRIVER(ti_qspi) = {
581 .name = "ti_qspi",
582 .id = UCLASS_SPI,
583 .of_match = ti_qspi_ids,
584 .ops = &ti_qspi_ops,
585 .ofdata_to_platdata = ti_qspi_ofdata_to_platdata,
586 .priv_auto_alloc_size = sizeof(struct ti_qspi_priv),
587 .probe = ti_qspi_probe,
588 .child_pre_probe = ti_qspi_child_pre_probe,
589};
590#endif /* CONFIG_DM_SPI */