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Kumar Gala9490a7f2008-07-25 13:31:05 -05001/*
ramneek mehresh3d7506f2012-04-18 19:39:53 +00002 * Copyright 2007-2009,2010-2012 Freescale Semiconductor, Inc.
Kumar Gala9490a7f2008-07-25 13:31:05 -05003 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02004 * SPDX-License-Identifier: GPL-2.0+
Kumar Gala9490a7f2008-07-25 13:31:05 -05005 */
6
7/*
8 * mpc8536ds board configuration file
9 *
10 */
11#ifndef __CONFIG_H
12#define __CONFIG_H
13
York Sun15672c62014-04-30 14:43:49 -070014#define CONFIG_DISPLAY_BOARDINFO
Kumar Galac7e1a432010-05-21 04:14:49 -050015#include "../board/freescale/common/ics307_clk.h"
16
Wolfgang Denkd24f2d32010-10-04 19:58:00 +020017#ifdef CONFIG_36BIT
Kumar Gala337f9fd2009-07-30 15:54:07 -050018#define CONFIG_PHYS_64BIT 1
19#endif
20
Wolfgang Denkd24f2d32010-10-04 19:58:00 +020021#ifdef CONFIG_SDCARD
Mingkai Hue40ac482009-09-23 15:20:38 +080022#define CONFIG_RAMBOOT_SDCARD 1
Haijun.Zhange2c9bc52014-04-10 11:16:30 +080023#define CONFIG_SYS_TEXT_BASE 0xf8f40000
Kumar Gala7a577fd2011-01-12 02:48:53 -060024#define CONFIG_RESET_VECTOR_ADDRESS 0xf8fffffc
Mingkai Hue40ac482009-09-23 15:20:38 +080025#endif
26
Wolfgang Denkd24f2d32010-10-04 19:58:00 +020027#ifdef CONFIG_SPIFLASH
Mingkai Hue40ac482009-09-23 15:20:38 +080028#define CONFIG_RAMBOOT_SPIFLASH 1
Haijun.Zhange2c9bc52014-04-10 11:16:30 +080029#define CONFIG_SYS_TEXT_BASE 0xf8f40000
Kumar Gala7a577fd2011-01-12 02:48:53 -060030#define CONFIG_RESET_VECTOR_ADDRESS 0xf8fffffc
Wolfgang Denk2ae18242010-10-06 09:05:45 +020031#endif
32
33#ifndef CONFIG_SYS_TEXT_BASE
Haijun.Zhangc6e8f492014-02-13 09:03:02 +080034#define CONFIG_SYS_TEXT_BASE 0xeff40000
Mingkai Hue40ac482009-09-23 15:20:38 +080035#endif
36
Kumar Gala7a577fd2011-01-12 02:48:53 -060037#ifndef CONFIG_RESET_VECTOR_ADDRESS
38#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
39#endif
40
Haiying Wang96196a12010-11-10 15:37:13 -050041#ifndef CONFIG_SYS_MONITOR_BASE
42#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
43#endif
44
Kumar Gala9490a7f2008-07-25 13:31:05 -050045/* High Level Configuration Options */
46#define CONFIG_BOOKE 1 /* BOOKE */
47#define CONFIG_E500 1 /* BOOKE e500 family */
Kumar Gala9490a7f2008-07-25 13:31:05 -050048#define CONFIG_MPC8536 1
49#define CONFIG_MPC8536DS 1
50
Kumar Galac51fc5d2009-01-23 14:22:13 -060051#define CONFIG_FSL_ELBC 1 /* Has Enhanced localbus controller */
Kumar Gala9490a7f2008-07-25 13:31:05 -050052#define CONFIG_PCI 1 /* Enable PCI/PCIE */
53#define CONFIG_PCI1 1 /* Enable PCI controller 1 */
54#define CONFIG_PCIE1 1 /* PCIE controler 1 (slot 1) */
55#define CONFIG_PCIE2 1 /* PCIE controler 2 (slot 2) */
56#define CONFIG_PCIE3 1 /* PCIE controler 3 (ULI bridge) */
57#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
Gabor Juhos842033e2013-05-30 07:06:12 +000058#define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */
Kumar Gala9490a7f2008-07-25 13:31:05 -050059#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */
Kumar Gala0151cba2008-10-21 11:33:58 -050060#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
Kumar Gala9490a7f2008-07-25 13:31:05 -050061
62#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
63
64#define CONFIG_TSEC_ENET /* tsec ethernet support */
65#define CONFIG_ENV_OVERWRITE
66
Kumar Galac7e1a432010-05-21 04:14:49 -050067#define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */
68#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk()
Kumar Gala9490a7f2008-07-25 13:31:05 -050069#define CONFIG_ICS307_REFCLK_HZ 33333000 /* ICS307 clock chip ref freq */
Kumar Gala9490a7f2008-07-25 13:31:05 -050070
71/*
72 * These can be toggled for performance analysis, otherwise use default.
73 */
74#define CONFIG_L2_CACHE /* toggle L2 cache */
75#define CONFIG_BTB /* toggle branch predition */
Kumar Gala9490a7f2008-07-25 13:31:05 -050076
Andy Fleming80522dc2008-10-30 16:51:33 -050077#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
78
Kumar Gala9490a7f2008-07-25 13:31:05 -050079#define CONFIG_ENABLE_36BIT_PHYS 1
80
Kumar Gala337f9fd2009-07-30 15:54:07 -050081#ifdef CONFIG_PHYS_64BIT
82#define CONFIG_ADDR_MAP 1
83#define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */
84#endif
85
Mingkai Hu07355702009-09-23 15:19:32 +080086#define CONFIG_SYS_MEMTEST_START 0x00010000 /* skip exception vectors */
87#define CONFIG_SYS_MEMTEST_END 0x1f000000 /* skip u-boot at top of RAM */
Kumar Gala9490a7f2008-07-25 13:31:05 -050088#define CONFIG_PANIC_HANG /* do not reset board on panic */
89
90/*
Mingkai Hu9a1a0ae2009-09-23 15:20:37 +080091 * Config the L2 Cache as L2 SRAM
92 */
93#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
94#ifdef CONFIG_PHYS_64BIT
95#define CONFIG_SYS_INIT_L2_ADDR_PHYS 0xff8f80000ull
96#else
97#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
98#endif
99#define CONFIG_SYS_L2_SIZE (512 << 10)
100#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
101
Timur Tabie46fedf2011-08-04 18:03:41 -0500102#define CONFIG_SYS_CCSRBAR 0xffe00000
103#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
Kumar Gala9490a7f2008-07-25 13:31:05 -0500104
Kumar Gala8d22ddc2011-11-09 09:10:49 -0600105#if defined(CONFIG_NAND_SPL)
Timur Tabie46fedf2011-08-04 18:03:41 -0500106#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
Mingkai Hu9a1a0ae2009-09-23 15:20:37 +0800107#endif
108
Kumar Gala9490a7f2008-07-25 13:31:05 -0500109/* DDR Setup */
Kumar Gala337f9fd2009-07-30 15:54:07 -0500110#define CONFIG_VERY_BIG_RAM
York Sun5614e712013-09-30 09:22:09 -0700111#define CONFIG_SYS_FSL_DDR2
Kumar Gala9490a7f2008-07-25 13:31:05 -0500112#undef CONFIG_FSL_DDR_INTERACTIVE
113#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
114#define CONFIG_DDR_SPD
Kumar Gala9490a7f2008-07-25 13:31:05 -0500115
Dave Liu9b0ad1b2008-10-28 17:53:38 +0800116#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */
Kumar Gala9490a7f2008-07-25 13:31:05 -0500117#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
118
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200119#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
120#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
Kumar Gala9490a7f2008-07-25 13:31:05 -0500121
122#define CONFIG_NUM_DDR_CONTROLLERS 1
123#define CONFIG_DIMM_SLOTS_PER_CTLR 1
124#define CONFIG_CHIP_SELECTS_PER_CTRL 2
125
126/* I2C addresses of SPD EEPROMs */
127#define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200128#define CONFIG_SYS_SPD_BUS_NUM 1
Kumar Gala9490a7f2008-07-25 13:31:05 -0500129
130/* These are used when DDR doesn't use SPD. */
Mingkai Hu07355702009-09-23 15:19:32 +0800131#define CONFIG_SYS_SDRAM_SIZE 256 /* DDR is 256MB */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200132#define CONFIG_SYS_DDR_CS0_BNDS 0x0000001F
Mingkai Hu07355702009-09-23 15:19:32 +0800133#define CONFIG_SYS_DDR_CS0_CONFIG 0x80010102 /* Enable, no interleaving */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200134#define CONFIG_SYS_DDR_TIMING_3 0x00000000
135#define CONFIG_SYS_DDR_TIMING_0 0x00260802
136#define CONFIG_SYS_DDR_TIMING_1 0x3935d322
137#define CONFIG_SYS_DDR_TIMING_2 0x14904cc8
138#define CONFIG_SYS_DDR_MODE_1 0x00480432
139#define CONFIG_SYS_DDR_MODE_2 0x00000000
140#define CONFIG_SYS_DDR_INTERVAL 0x06180100
141#define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
142#define CONFIG_SYS_DDR_CLK_CTRL 0x03800000
143#define CONFIG_SYS_DDR_OCD_CTRL 0x00000000
144#define CONFIG_SYS_DDR_OCD_STATUS 0x00000000
Mingkai Hu07355702009-09-23 15:19:32 +0800145#define CONFIG_SYS_DDR_CONTROL 0xC3008000 /* Type = DDR2 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200146#define CONFIG_SYS_DDR_CONTROL2 0x04400010
Kumar Gala9490a7f2008-07-25 13:31:05 -0500147
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200148#define CONFIG_SYS_DDR_ERR_INT_EN 0x0000000d
149#define CONFIG_SYS_DDR_ERR_DIS 0x00000000
150#define CONFIG_SYS_DDR_SBE 0x00010000
Kumar Gala9490a7f2008-07-25 13:31:05 -0500151
Kumar Gala9490a7f2008-07-25 13:31:05 -0500152/* Make sure required options are set */
153#ifndef CONFIG_SPD_EEPROM
154#error ("CONFIG_SPD_EEPROM is required")
155#endif
156
157#undef CONFIG_CLOCKS_IN_MHZ
158
Kumar Gala9490a7f2008-07-25 13:31:05 -0500159/*
160 * Memory map -- xxx -this is wrong, needs updating
161 *
162 * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable
163 * 0x8000_0000 0xbfff_ffff PCI Express Mem 1G non-cacheable
164 * 0xc000_0000 0xdfff_ffff PCI 512M non-cacheable
165 * 0xe100_0000 0xe3ff_ffff PCI IO range 4M non-cacheable
166 *
167 * Localbus cacheable (TBD)
168 * 0xXXXX_XXXX 0xXXXX_XXXX SRAM YZ M Cacheable
169 *
170 * Localbus non-cacheable
Jason Jinc57fc282008-10-31 05:07:04 -0500171 * 0xe000_0000 0xe7ff_ffff Promjet/free 128M non-cacheable
Kumar Gala9490a7f2008-07-25 13:31:05 -0500172 * 0xe800_0000 0xefff_ffff FLASH 128M non-cacheable
Jason Jinc57fc282008-10-31 05:07:04 -0500173 * 0xffa0_0000 0xffaf_ffff NAND 1M non-cacheable
Kumar Gala9490a7f2008-07-25 13:31:05 -0500174 * 0xffdf_0000 0xffdf_7fff PIXIS 32K non-cacheable TLB0
175 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0
176 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable
177 */
178
179/*
180 * Local Bus Definitions
181 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200182#define CONFIG_SYS_FLASH_BASE 0xe0000000 /* start of FLASH 128M */
Kumar Gala337f9fd2009-07-30 15:54:07 -0500183#ifdef CONFIG_PHYS_64BIT
184#define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull
185#else
Kumar Galac953ddf2008-12-02 14:19:34 -0600186#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
Kumar Gala337f9fd2009-07-30 15:54:07 -0500187#endif
Kumar Gala9490a7f2008-07-25 13:31:05 -0500188
Mingkai Hu9a1a0ae2009-09-23 15:20:37 +0800189#define CONFIG_FLASH_BR_PRELIM \
Timur Tabi7ee41102012-07-06 07:39:26 +0000190 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000) | BR_PS_16 | BR_V)
Mingkai Hu9a1a0ae2009-09-23 15:20:37 +0800191#define CONFIG_FLASH_OR_PRELIM 0xf8000ff7
Kumar Gala9490a7f2008-07-25 13:31:05 -0500192
Mingkai Hu07355702009-09-23 15:19:32 +0800193#define CONFIG_SYS_BR1_PRELIM \
194 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \
195 | BR_PS_16 | BR_V)
Kumar Galac953ddf2008-12-02 14:19:34 -0600196#define CONFIG_SYS_OR1_PRELIM 0xf8000ff7
Kumar Gala9490a7f2008-07-25 13:31:05 -0500197
Mingkai Hu07355702009-09-23 15:19:32 +0800198#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, \
199 CONFIG_SYS_FLASH_BASE_PHYS }
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200200#define CONFIG_SYS_FLASH_QUIET_TEST
Kumar Gala9490a7f2008-07-25 13:31:05 -0500201#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
202
Mingkai Hu07355702009-09-23 15:19:32 +0800203#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
204#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200205#undef CONFIG_SYS_FLASH_CHECKSUM
Mingkai Hu07355702009-09-23 15:19:32 +0800206#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
207#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
Kumar Gala9490a7f2008-07-25 13:31:05 -0500208
Masahiro Yamada02344462014-06-04 10:26:50 +0900209#if defined(CONFIG_RAMBOOT_SDCARD) || defined(CONFIG_RAMBOOT_SPIFLASH)
Mingkai Hu9a1a0ae2009-09-23 15:20:37 +0800210#define CONFIG_SYS_RAMBOOT
Kumar Galaa55bb832010-11-29 14:32:11 -0600211#define CONFIG_SYS_EXTRA_ENV_RELOC
Mingkai Hu9a1a0ae2009-09-23 15:20:37 +0800212#else
213#undef CONFIG_SYS_RAMBOOT
214#endif
215
Kumar Gala9490a7f2008-07-25 13:31:05 -0500216#define CONFIG_FLASH_CFI_DRIVER
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200217#define CONFIG_SYS_FLASH_CFI
218#define CONFIG_SYS_FLASH_EMPTY_INFO
219#define CONFIG_SYS_FLASH_AMD_CHECK_DQ7
Kumar Gala9490a7f2008-07-25 13:31:05 -0500220
221#define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */
222
Ramneek Mehresh68d42302011-06-07 10:10:43 +0000223#define CONFIG_HWCONFIG /* enable hwconfig */
Kumar Gala9490a7f2008-07-25 13:31:05 -0500224#define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */
225#define PIXIS_BASE 0xffdf0000 /* PIXIS registers */
Kumar Gala337f9fd2009-07-30 15:54:07 -0500226#ifdef CONFIG_PHYS_64BIT
227#define PIXIS_BASE_PHYS 0xfffdf0000ull
228#else
Kumar Gala52b565f2008-12-02 14:19:33 -0600229#define PIXIS_BASE_PHYS PIXIS_BASE
Kumar Gala337f9fd2009-07-30 15:54:07 -0500230#endif
Kumar Gala9490a7f2008-07-25 13:31:05 -0500231
Kumar Gala52b565f2008-12-02 14:19:33 -0600232#define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V)
Mingkai Hu07355702009-09-23 15:19:32 +0800233#define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */
Kumar Gala9490a7f2008-07-25 13:31:05 -0500234
235#define PIXIS_ID 0x0 /* Board ID at offset 0 */
236#define PIXIS_VER 0x1 /* Board version at offset 1 */
237#define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */
238#define PIXIS_CSR 0x3 /* PIXIS General control/status register */
239#define PIXIS_RST 0x4 /* PIXIS Reset Control register */
240#define PIXIS_PWR 0x5 /* PIXIS Power status register */
241#define PIXIS_AUX 0x6 /* Auxiliary 1 register */
242#define PIXIS_SPD 0x7 /* Register for SYSCLK speed */
243#define PIXIS_AUX2 0x8 /* Auxiliary 2 register */
244#define PIXIS_VCTL 0x10 /* VELA Control Register */
245#define PIXIS_VSTAT 0x11 /* VELA Status Register */
246#define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */
247#define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */
248#define PIXIS_VCORE0 0x14 /* VELA VCORE0 Register */
249#define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */
Kumar Gala6bb5b412009-07-14 22:42:01 -0500250#define PIXIS_VBOOT_LBMAP 0xe0 /* VBOOT - CFG_LBMAP */
251#define PIXIS_VBOOT_LBMAP_NOR0 0x00 /* cfg_lbmap - boot from NOR 0 */
252#define PIXIS_VBOOT_LBMAP_NOR1 0x01 /* cfg_lbmap - boot from NOR 1 */
253#define PIXIS_VBOOT_LBMAP_NOR2 0x02 /* cfg_lbmap - boot from NOR 2 */
254#define PIXIS_VBOOT_LBMAP_NOR3 0x03 /* cfg_lbmap - boot from NOR 3 */
255#define PIXIS_VBOOT_LBMAP_PJET 0x04 /* cfg_lbmap - boot from projet */
256#define PIXIS_VBOOT_LBMAP_NAND 0x05 /* cfg_lbmap - boot from NAND */
Kumar Gala9490a7f2008-07-25 13:31:05 -0500257#define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */
258#define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */
259#define PIXIS_VSPEED2 0x19 /* VELA VSpeed 2 */
260#define PIXIS_VSYSCLK0 0x1A /* VELA SYSCLK0 Register */
261#define PIXIS_VSYSCLK1 0x1B /* VELA SYSCLK1 Register */
262#define PIXIS_VSYSCLK2 0x1C /* VELA SYSCLK2 Register */
263#define PIXIS_VDDRCLK0 0x1D /* VELA DDRCLK0 Register */
264#define PIXIS_VDDRCLK1 0x1E /* VELA DDRCLK1 Register */
265#define PIXIS_VDDRCLK2 0x1F /* VELA DDRCLK2 Register */
266#define PIXIS_VWATCH 0x24 /* Watchdog Register */
267#define PIXIS_LED 0x25 /* LED Register */
268
Mingkai Hu9a1a0ae2009-09-23 15:20:37 +0800269#define PIXIS_SPD_SYSCLK 0x7 /* SYSCLK option */
270
Kumar Gala9490a7f2008-07-25 13:31:05 -0500271/* old pixis referenced names */
272#define PIXIS_VCLKH 0x19 /* VELA VCLKH register */
273#define PIXIS_VCLKL 0x1A /* VELA VCLKL register */
Matthew McClintock509e19c2011-02-25 16:20:11 -0600274#define CONFIG_SYS_PIXIS_VBOOT_MASK 0x4e
Kumar Gala9490a7f2008-07-25 13:31:05 -0500275
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200276#define CONFIG_SYS_INIT_RAM_LOCK 1
277#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */
Wolfgang Denk553f0982010-10-26 13:32:32 +0200278#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */
Kumar Gala9490a7f2008-07-25 13:31:05 -0500279
Mingkai Hu07355702009-09-23 15:19:32 +0800280#define CONFIG_SYS_GBL_DATA_OFFSET \
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200281 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200282#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
Kumar Gala9490a7f2008-07-25 13:31:05 -0500283
Mingkai Hu07355702009-09-23 15:19:32 +0800284#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
285#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */
Kumar Gala9490a7f2008-07-25 13:31:05 -0500286
Mingkai Hu9a1a0ae2009-09-23 15:20:37 +0800287#ifndef CONFIG_NAND_SPL
Kumar Gala337f9fd2009-07-30 15:54:07 -0500288#define CONFIG_SYS_NAND_BASE 0xffa00000
289#ifdef CONFIG_PHYS_64BIT
290#define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull
291#else
292#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
293#endif
Mingkai Hu9a1a0ae2009-09-23 15:20:37 +0800294#else
295#define CONFIG_SYS_NAND_BASE 0xfff00000
296#ifdef CONFIG_PHYS_64BIT
297#define CONFIG_SYS_NAND_BASE_PHYS 0xffff00000ull
298#else
299#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
300#endif
301#endif
Jason Jinc57fc282008-10-31 05:07:04 -0500302#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE,\
303 CONFIG_SYS_NAND_BASE + 0x40000, \
304 CONFIG_SYS_NAND_BASE + 0x80000, \
305 CONFIG_SYS_NAND_BASE + 0xC0000}
306#define CONFIG_SYS_MAX_NAND_DEVICE 4
Jason Jinc57fc282008-10-31 05:07:04 -0500307#define CONFIG_CMD_NAND 1
308#define CONFIG_NAND_FSL_ELBC 1
309#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
310
Mingkai Hu9a1a0ae2009-09-23 15:20:37 +0800311/* NAND boot: 4K NAND loader config */
312#define CONFIG_SYS_NAND_SPL_SIZE 0x1000
Haijun.Zhangc6e8f492014-02-13 09:03:02 +0800313#define CONFIG_SYS_NAND_U_BOOT_SIZE ((768 << 10) - 0x2000)
Mingkai Hu9a1a0ae2009-09-23 15:20:37 +0800314#define CONFIG_SYS_NAND_U_BOOT_DST (CONFIG_SYS_INIT_L2_ADDR)
315#define CONFIG_SYS_NAND_U_BOOT_START \
316 (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_NAND_SPL_SIZE)
317#define CONFIG_SYS_NAND_U_BOOT_OFFS (0)
318#define CONFIG_SYS_NAND_U_BOOT_RELOC (CONFIG_SYS_INIT_L2_END - 0x2000)
319#define CONFIG_SYS_NAND_U_BOOT_RELOC_SP ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
320
Jason Jinc57fc282008-10-31 05:07:04 -0500321/* NAND flash config */
Matthew McClintocka3055c52011-04-05 14:39:33 -0500322#define CONFIG_SYS_NAND_BR_PRELIM \
Mingkai Hu07355702009-09-23 15:19:32 +0800323 (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
324 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
325 | BR_PS_8 /* Port Size = 8 bit */ \
326 | BR_MS_FCM /* MSEL = FCM */ \
327 | BR_V) /* valid */
Matthew McClintocka3055c52011-04-05 14:39:33 -0500328#define CONFIG_SYS_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \
Mingkai Hu07355702009-09-23 15:19:32 +0800329 | OR_FCM_PGS /* Large Page*/ \
330 | OR_FCM_CSCT \
331 | OR_FCM_CST \
332 | OR_FCM_CHT \
333 | OR_FCM_SCY_1 \
334 | OR_FCM_TRLX \
335 | OR_FCM_EHTR)
Jason Jinc57fc282008-10-31 05:07:04 -0500336
Mingkai Hu9a1a0ae2009-09-23 15:20:37 +0800337#define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
338#define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
Matthew McClintocka3055c52011-04-05 14:39:33 -0500339#define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
340#define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
Jason Jinc57fc282008-10-31 05:07:04 -0500341
Mingkai Hu07355702009-09-23 15:19:32 +0800342#define CONFIG_SYS_BR4_PRELIM \
Timur Tabi7ee41102012-07-06 07:39:26 +0000343 (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0x40000) \
Mingkai Hu07355702009-09-23 15:19:32 +0800344 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
345 | BR_PS_8 /* Port Size = 8 bit */ \
346 | BR_MS_FCM /* MSEL = FCM */ \
347 | BR_V) /* valid */
Matthew McClintocka3055c52011-04-05 14:39:33 -0500348#define CONFIG_SYS_OR4_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
Mingkai Hu07355702009-09-23 15:19:32 +0800349#define CONFIG_SYS_BR5_PRELIM \
Timur Tabi7ee41102012-07-06 07:39:26 +0000350 (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0x80000) \
Mingkai Hu07355702009-09-23 15:19:32 +0800351 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
352 | BR_PS_8 /* Port Size = 8 bit */ \
353 | BR_MS_FCM /* MSEL = FCM */ \
354 | BR_V) /* valid */
Matthew McClintocka3055c52011-04-05 14:39:33 -0500355#define CONFIG_SYS_OR5_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
Jason Jinc57fc282008-10-31 05:07:04 -0500356
Mingkai Hu07355702009-09-23 15:19:32 +0800357#define CONFIG_SYS_BR6_PRELIM \
Timur Tabi7ee41102012-07-06 07:39:26 +0000358 (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0xc0000) \
Mingkai Hu07355702009-09-23 15:19:32 +0800359 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
360 | BR_PS_8 /* Port Size = 8 bit */ \
361 | BR_MS_FCM /* MSEL = FCM */ \
362 | BR_V) /* valid */
Matthew McClintocka3055c52011-04-05 14:39:33 -0500363#define CONFIG_SYS_OR6_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
Jason Jinc57fc282008-10-31 05:07:04 -0500364
Kumar Gala9490a7f2008-07-25 13:31:05 -0500365/* Serial Port - controlled on board with jumper J8
366 * open - index 2
367 * shorted - index 1
368 */
369#define CONFIG_CONS_INDEX 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200370#define CONFIG_SYS_NS16550_SERIAL
371#define CONFIG_SYS_NS16550_REG_SIZE 1
372#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
Kumar Gala93341902010-04-07 01:34:11 -0500373#ifdef CONFIG_NAND_SPL
374#define CONFIG_NS16550_MIN_FUNCTIONS
375#endif
Kumar Gala9490a7f2008-07-25 13:31:05 -0500376
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200377#define CONFIG_SYS_BAUDRATE_TABLE \
Kumar Gala9490a7f2008-07-25 13:31:05 -0500378 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
379
Mingkai Hu07355702009-09-23 15:19:32 +0800380#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR + 0x4500)
381#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR + 0x4600)
Kumar Gala9490a7f2008-07-25 13:31:05 -0500382
Kumar Gala9490a7f2008-07-25 13:31:05 -0500383/*
Kumar Gala9490a7f2008-07-25 13:31:05 -0500384 * I2C
385 */
Heiko Schocher00f792e2012-10-24 13:48:22 +0200386#define CONFIG_SYS_I2C
387#define CONFIG_SYS_I2C_FSL
388#define CONFIG_SYS_FSL_I2C_SPEED 400000
389#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
390#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
391#define CONFIG_SYS_FSL_I2C2_SPEED 400000
392#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
393#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
394#define CONFIG_SYS_I2C_NOPROBES { {0, 0x29} }
Kumar Gala9490a7f2008-07-25 13:31:05 -0500395
396/*
397 * I2C2 EEPROM
398 */
Jean-Christophe PLAGNIOL-VILLARD32628c52008-08-30 23:54:58 +0200399#define CONFIG_ID_EEPROM
400#ifdef CONFIG_ID_EEPROM
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200401#define CONFIG_SYS_I2C_EEPROM_NXID
Kumar Gala9490a7f2008-07-25 13:31:05 -0500402#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200403#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
404#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
405#define CONFIG_SYS_EEPROM_BUS_NUM 1
Kumar Gala9490a7f2008-07-25 13:31:05 -0500406
407/*
Xie Xiaoboae2044d2011-10-03 12:18:39 -0700408 * eSPI - Enhanced SPI
409 */
410#define CONFIG_HARD_SPI
Xie Xiaoboae2044d2011-10-03 12:18:39 -0700411
412#if defined(CONFIG_SPI_FLASH)
Xie Xiaoboae2044d2011-10-03 12:18:39 -0700413#define CONFIG_SF_DEFAULT_SPEED 10000000
414#define CONFIG_SF_DEFAULT_MODE 0
415#endif
416
417/*
Kumar Gala9490a7f2008-07-25 13:31:05 -0500418 * General PCI
419 * Memory space is mapped 1-1, but I/O space must start from 0.
420 */
421
Kumar Gala5af0fdd2008-12-02 16:08:39 -0600422#define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000
Kumar Gala337f9fd2009-07-30 15:54:07 -0500423#ifdef CONFIG_PHYS_64BIT
424#define CONFIG_SYS_PCI1_MEM_BUS 0xf0000000
425#define CONFIG_SYS_PCI1_MEM_PHYS 0xc00000000ull
426#else
Kumar Gala5af0fdd2008-12-02 16:08:39 -0600427#define CONFIG_SYS_PCI1_MEM_BUS 0x80000000
428#define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000
Kumar Gala337f9fd2009-07-30 15:54:07 -0500429#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200430#define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
Kumar Gala337f9fd2009-07-30 15:54:07 -0500431#define CONFIG_SYS_PCI1_IO_VIRT 0xffc00000
432#define CONFIG_SYS_PCI1_IO_BUS 0x00000000
433#ifdef CONFIG_PHYS_64BIT
434#define CONFIG_SYS_PCI1_IO_PHYS 0xfffc00000ull
435#else
436#define CONFIG_SYS_PCI1_IO_PHYS 0xffc00000
437#endif
438#define CONFIG_SYS_PCI1_IO_SIZE 0x00010000 /* 64k */
Kumar Gala9490a7f2008-07-25 13:31:05 -0500439
440/* controller 1, Slot 1, tgtid 1, Base address a000 */
Kumar Gala5f7b31b2010-12-17 15:14:54 -0600441#define CONFIG_SYS_PCIE1_NAME "Slot 1"
Kumar Gala5af0fdd2008-12-02 16:08:39 -0600442#define CONFIG_SYS_PCIE1_MEM_VIRT 0x90000000
Kumar Gala337f9fd2009-07-30 15:54:07 -0500443#ifdef CONFIG_PHYS_64BIT
444#define CONFIG_SYS_PCIE1_MEM_BUS 0xf8000000
445#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc10000000ull
446#else
Kumar Gala10795f42008-12-02 16:08:36 -0600447#define CONFIG_SYS_PCIE1_MEM_BUS 0x90000000
Kumar Gala5af0fdd2008-12-02 16:08:39 -0600448#define CONFIG_SYS_PCIE1_MEM_PHYS 0x90000000
Kumar Gala337f9fd2009-07-30 15:54:07 -0500449#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200450#define CONFIG_SYS_PCIE1_MEM_SIZE 0x08000000 /* 128M */
Kumar Galaaca5f012008-12-02 16:08:40 -0600451#define CONFIG_SYS_PCIE1_IO_VIRT 0xffc10000
Kumar Gala337f9fd2009-07-30 15:54:07 -0500452#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
453#ifdef CONFIG_PHYS_64BIT
454#define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc10000ull
455#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200456#define CONFIG_SYS_PCIE1_IO_PHYS 0xffc10000
Kumar Gala337f9fd2009-07-30 15:54:07 -0500457#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200458#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
Kumar Gala9490a7f2008-07-25 13:31:05 -0500459
460/* controller 2, Slot 2, tgtid 2, Base address 9000 */
Kumar Gala5f7b31b2010-12-17 15:14:54 -0600461#define CONFIG_SYS_PCIE2_NAME "Slot 2"
Kumar Gala5af0fdd2008-12-02 16:08:39 -0600462#define CONFIG_SYS_PCIE2_MEM_VIRT 0x98000000
Kumar Gala337f9fd2009-07-30 15:54:07 -0500463#ifdef CONFIG_PHYS_64BIT
464#define CONFIG_SYS_PCIE2_MEM_BUS 0xf8000000
465#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc18000000ull
466#else
Kumar Gala10795f42008-12-02 16:08:36 -0600467#define CONFIG_SYS_PCIE2_MEM_BUS 0x98000000
Kumar Gala5af0fdd2008-12-02 16:08:39 -0600468#define CONFIG_SYS_PCIE2_MEM_PHYS 0x98000000
Kumar Gala337f9fd2009-07-30 15:54:07 -0500469#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200470#define CONFIG_SYS_PCIE2_MEM_SIZE 0x08000000 /* 128M */
Kumar Galaaca5f012008-12-02 16:08:40 -0600471#define CONFIG_SYS_PCIE2_IO_VIRT 0xffc20000
Kumar Gala337f9fd2009-07-30 15:54:07 -0500472#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
473#ifdef CONFIG_PHYS_64BIT
474#define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc20000ull
475#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200476#define CONFIG_SYS_PCIE2_IO_PHYS 0xffc20000
Kumar Gala337f9fd2009-07-30 15:54:07 -0500477#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200478#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
Kumar Gala9490a7f2008-07-25 13:31:05 -0500479
480/* controller 3, direct to uli, tgtid 3, Base address 8000 */
Kumar Gala5f7b31b2010-12-17 15:14:54 -0600481#define CONFIG_SYS_PCIE3_NAME "Slot 3"
Kumar Gala5af0fdd2008-12-02 16:08:39 -0600482#define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000
Kumar Gala337f9fd2009-07-30 15:54:07 -0500483#ifdef CONFIG_PHYS_64BIT
484#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
485#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull
486#else
Kumar Gala10795f42008-12-02 16:08:36 -0600487#define CONFIG_SYS_PCIE3_MEM_BUS 0xa0000000
Kumar Gala5af0fdd2008-12-02 16:08:39 -0600488#define CONFIG_SYS_PCIE3_MEM_PHYS 0xa0000000
Kumar Gala337f9fd2009-07-30 15:54:07 -0500489#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200490#define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */
Kumar Galaaca5f012008-12-02 16:08:40 -0600491#define CONFIG_SYS_PCIE3_IO_VIRT 0xffc30000
Kumar Gala337f9fd2009-07-30 15:54:07 -0500492#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
493#ifdef CONFIG_PHYS_64BIT
494#define CONFIG_SYS_PCIE3_IO_PHYS 0xfffc30000ull
495#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200496#define CONFIG_SYS_PCIE3_IO_PHYS 0xffc30000
Kumar Gala337f9fd2009-07-30 15:54:07 -0500497#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200498#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
Kumar Gala9490a7f2008-07-25 13:31:05 -0500499
500#if defined(CONFIG_PCI)
501
Kumar Gala9490a7f2008-07-25 13:31:05 -0500502#define CONFIG_PCI_PNP /* do pci plug-and-play */
503
504/*PCIE video card used*/
Kumar Galaaca5f012008-12-02 16:08:40 -0600505#define VIDEO_IO_OFFSET CONFIG_SYS_PCIE3_IO_VIRT
Kumar Gala9490a7f2008-07-25 13:31:05 -0500506
507/*PCI video card used*/
Kumar Galaaca5f012008-12-02 16:08:40 -0600508/*#define VIDEO_IO_OFFSET CONFIG_SYS_PCI1_IO_VIRT*/
Kumar Gala9490a7f2008-07-25 13:31:05 -0500509
510/* video */
511#define CONFIG_VIDEO
512
513#if defined(CONFIG_VIDEO)
514#define CONFIG_BIOSEMU
515#define CONFIG_CFB_CONSOLE
516#define CONFIG_VIDEO_SW_CURSOR
517#define CONFIG_VGA_AS_SINGLE_DEVICE
518#define CONFIG_ATI_RADEON_FB
519#define CONFIG_VIDEO_LOGO
Kumar Galaaca5f012008-12-02 16:08:40 -0600520#define CONFIG_SYS_ISA_IO_BASE_ADDRESS CONFIG_SYS_PCIE3_IO_VIRT
Kumar Gala9490a7f2008-07-25 13:31:05 -0500521#endif
522
523#undef CONFIG_EEPRO100
524#undef CONFIG_TULIP
Kumar Gala9490a7f2008-07-25 13:31:05 -0500525
Kumar Gala9490a7f2008-07-25 13:31:05 -0500526#ifndef CONFIG_PCI_PNP
Kumar Gala5f91ef62008-12-02 16:08:37 -0600527 #define PCI_ENET0_IOADDR CONFIG_SYS_PCI1_IO_BUS
528 #define PCI_ENET0_MEMADDR CONFIG_SYS_PCI1_IO_BUS
Kumar Gala9490a7f2008-07-25 13:31:05 -0500529 #define PCI_IDSEL_NUMBER 0x11 /* IDSEL = AD11 */
530#endif
531
532#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
533
534#endif /* CONFIG_PCI */
535
536/* SATA */
537#define CONFIG_LIBATA
538#define CONFIG_FSL_SATA
539
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200540#define CONFIG_SYS_SATA_MAX_DEVICE 2
Kumar Gala9490a7f2008-07-25 13:31:05 -0500541#define CONFIG_SATA1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200542#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
543#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
Kumar Gala9490a7f2008-07-25 13:31:05 -0500544#define CONFIG_SATA2
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200545#define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
546#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
Kumar Gala9490a7f2008-07-25 13:31:05 -0500547
548#ifdef CONFIG_FSL_SATA
549#define CONFIG_LBA48
550#define CONFIG_CMD_SATA
551#define CONFIG_DOS_PARTITION
Kumar Gala9490a7f2008-07-25 13:31:05 -0500552#endif
553
554#if defined(CONFIG_TSEC_ENET)
555
Kumar Gala9490a7f2008-07-25 13:31:05 -0500556#define CONFIG_MII 1 /* MII PHY management */
557#define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */
558#define CONFIG_TSEC1 1
559#define CONFIG_TSEC1_NAME "eTSEC1"
560#define CONFIG_TSEC3 1
561#define CONFIG_TSEC3_NAME "eTSEC3"
562
Jason Jin2e26d832008-10-10 11:41:00 +0800563#define CONFIG_FSL_SGMII_RISER 1
564#define SGMII_RISER_PHY_OFFSET 0x1c
565
Kumar Gala9490a7f2008-07-25 13:31:05 -0500566#define TSEC1_PHY_ADDR 1 /* TSEC1 -> PHY1 */
567#define TSEC3_PHY_ADDR 0 /* TSEC3 -> PHY0 */
568
569#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
570#define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
571
572#define TSEC1_PHYIDX 0
573#define TSEC3_PHYIDX 0
574
575#define CONFIG_ETHPRIME "eTSEC1"
576
577#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
578
579#endif /* CONFIG_TSEC_ENET */
580
581/*
582 * Environment
583 */
Mingkai Hu9a1a0ae2009-09-23 15:20:37 +0800584
585#if defined(CONFIG_SYS_RAMBOOT)
Masahiro Yamada02344462014-06-04 10:26:50 +0900586#if defined(CONFIG_RAMBOOT_SPIFLASH)
Xie Xiaobo2d4afd42011-10-03 12:54:21 -0700587#define CONFIG_ENV_IS_IN_SPI_FLASH
588#define CONFIG_ENV_SPI_BUS 0
589#define CONFIG_ENV_SPI_CS 0
590#define CONFIG_ENV_SPI_MAX_HZ 10000000
591#define CONFIG_ENV_SPI_MODE 0
592#define CONFIG_ENV_SIZE 0x2000 /* 8KB */
593#define CONFIG_ENV_OFFSET 0xF0000
594#define CONFIG_ENV_SECT_SIZE 0x10000
595#elif defined(CONFIG_RAMBOOT_SDCARD)
596#define CONFIG_ENV_IS_IN_MMC
Fabio Estevam4394d0c2012-01-11 09:20:50 +0000597#define CONFIG_FSL_FIXED_MMC_LOCATION
Xie Xiaobo2d4afd42011-10-03 12:54:21 -0700598#define CONFIG_ENV_SIZE 0x2000
599#define CONFIG_SYS_MMC_ENV_DEV 0
600#else
Mingkai Hue40ac482009-09-23 15:20:38 +0800601 #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
602 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
603 #define CONFIG_ENV_SIZE 0x2000
Kumar Gala9490a7f2008-07-25 13:31:05 -0500604#endif
Mingkai Hu9a1a0ae2009-09-23 15:20:37 +0800605#else
606 #define CONFIG_ENV_IS_IN_FLASH 1
Mingkai Hu9a1a0ae2009-09-23 15:20:37 +0800607 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
Mingkai Hu9a1a0ae2009-09-23 15:20:37 +0800608 #define CONFIG_ENV_SIZE 0x2000
609 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
610#endif
Kumar Gala9490a7f2008-07-25 13:31:05 -0500611
612#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200613#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
Kumar Gala9490a7f2008-07-25 13:31:05 -0500614
615/*
616 * Command line configuration.
617 */
Kumar Gala9490a7f2008-07-25 13:31:05 -0500618#define CONFIG_CMD_IRQ
Kumar Gala1c9aa762008-09-22 23:40:42 -0500619#define CONFIG_CMD_IRQ
Becky Bruce199e2622010-06-17 11:37:25 -0500620#define CONFIG_CMD_REGINFO
Kumar Gala9490a7f2008-07-25 13:31:05 -0500621
622#if defined(CONFIG_PCI)
623#define CONFIG_CMD_PCI
Kumar Gala9490a7f2008-07-25 13:31:05 -0500624#endif
625
626#undef CONFIG_WATCHDOG /* watchdog disabled */
627
Andy Fleming80522dc2008-10-30 16:51:33 -0500628#define CONFIG_MMC 1
629
630#ifdef CONFIG_MMC
631#define CONFIG_FSL_ESDHC
632#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
Andy Fleming80522dc2008-10-30 16:51:33 -0500633#define CONFIG_GENERIC_MMC
Fanzc1116ebb2011-10-03 12:18:42 -0700634#endif
635
636/*
637 * USB
638 */
ramneek mehresh3d7506f2012-04-18 19:39:53 +0000639#define CONFIG_HAS_FSL_MPH_USB
640#ifdef CONFIG_HAS_FSL_MPH_USB
Fanzc1116ebb2011-10-03 12:18:42 -0700641#define CONFIG_USB_EHCI
642
643#ifdef CONFIG_USB_EHCI
Fanzc1116ebb2011-10-03 12:18:42 -0700644#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
645#define CONFIG_USB_EHCI_FSL
646#define CONFIG_USB_STORAGE
647#endif
ramneek mehresh3d7506f2012-04-18 19:39:53 +0000648#endif
Fanzc1116ebb2011-10-03 12:18:42 -0700649
650#if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI)
Andy Fleming80522dc2008-10-30 16:51:33 -0500651#define CONFIG_DOS_PARTITION
652#endif
653
Kumar Gala9490a7f2008-07-25 13:31:05 -0500654/*
655 * Miscellaneous configurable options
656 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200657#define CONFIG_SYS_LONGHELP /* undef to save memory */
Mingkai Hu07355702009-09-23 15:19:32 +0800658#define CONFIG_CMDLINE_EDITING /* Command-line editing */
Kim Phillips5be58f52010-07-14 19:47:18 -0500659#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200660#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
Kumar Gala9490a7f2008-07-25 13:31:05 -0500661#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200662#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
Kumar Gala9490a7f2008-07-25 13:31:05 -0500663#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200664#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
Kumar Gala9490a7f2008-07-25 13:31:05 -0500665#endif
Mingkai Hu07355702009-09-23 15:19:32 +0800666#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE \
667 + sizeof(CONFIG_SYS_PROMPT) + 16) /* Print Buffer Size */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200668#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
Mingkai Hu07355702009-09-23 15:19:32 +0800669#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
Kumar Gala9490a7f2008-07-25 13:31:05 -0500670
671/*
672 * For booting Linux, the board info and command line data
Kumar Galaa832ac42011-04-28 10:13:41 -0500673 * have to be in the first 64 MB of memory, since this is
Kumar Gala9490a7f2008-07-25 13:31:05 -0500674 * the maximum mapped by the Linux kernel during initialization.
675 */
Kumar Galaa832ac42011-04-28 10:13:41 -0500676#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux */
677#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
Kumar Gala9490a7f2008-07-25 13:31:05 -0500678
Kumar Gala9490a7f2008-07-25 13:31:05 -0500679#if defined(CONFIG_CMD_KGDB)
680#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
Kumar Gala9490a7f2008-07-25 13:31:05 -0500681#endif
682
683/*
684 * Environment Configuration
685 */
686
687/* The mac addresses for all ethernet interface */
688#if defined(CONFIG_TSEC_ENET)
689#define CONFIG_HAS_ETH0
Kumar Gala9490a7f2008-07-25 13:31:05 -0500690#define CONFIG_HAS_ETH1
Kumar Gala9490a7f2008-07-25 13:31:05 -0500691#define CONFIG_HAS_ETH2
Kumar Gala9490a7f2008-07-25 13:31:05 -0500692#define CONFIG_HAS_ETH3
Kumar Gala9490a7f2008-07-25 13:31:05 -0500693#endif
694
695#define CONFIG_IPADDR 192.168.1.254
696
697#define CONFIG_HOSTNAME unknown
Joe Hershberger8b3637c2011-10-13 13:03:47 +0000698#define CONFIG_ROOTPATH "/opt/nfsroot"
Joe Hershbergerb3f44c22011-10-13 13:03:48 +0000699#define CONFIG_BOOTFILE "uImage"
Mingkai Hu07355702009-09-23 15:19:32 +0800700#define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
Kumar Gala9490a7f2008-07-25 13:31:05 -0500701
702#define CONFIG_SERVERIP 192.168.1.1
703#define CONFIG_GATEWAYIP 192.168.1.1
704#define CONFIG_NETMASK 255.255.255.0
705
706/* default location for tftp and bootm */
707#define CONFIG_LOADADDR 1000000
708
709#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
710#undef CONFIG_BOOTARGS /* the boot command will set bootargs */
711
712#define CONFIG_BAUDRATE 115200
713
714#define CONFIG_EXTRA_ENV_SETTINGS \
Marek Vasut5368c552012-09-23 17:41:24 +0200715"netdev=eth0\0" \
716"uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
717"tftpflash=tftpboot $loadaddr $uboot; " \
718 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \
719 " +$filesize; " \
720 "erase " __stringify(CONFIG_SYS_TEXT_BASE) \
721 " +$filesize; " \
722 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
723 " $filesize; " \
724 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \
725 " +$filesize; " \
726 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
727 " $filesize\0" \
728"consoledev=ttyS0\0" \
729"ramdiskaddr=2000000\0" \
730"ramdiskfile=8536ds/ramdisk.uboot\0" \
731"fdtaddr=c00000\0" \
732"fdtfile=8536ds/mpc8536ds.dtb\0" \
733"bdev=sda3\0" \
734"hwconfig=usb1:dr_mode=host,phy_type=ulpi\0"
Kumar Gala9490a7f2008-07-25 13:31:05 -0500735
736#define CONFIG_HDBOOT \
737 "setenv bootargs root=/dev/$bdev rw " \
738 "console=$consoledev,$baudrate $othbootargs;" \
739 "tftp $loadaddr $bootfile;" \
740 "tftp $fdtaddr $fdtfile;" \
741 "bootm $loadaddr - $fdtaddr"
742
743#define CONFIG_NFSBOOTCOMMAND \
744 "setenv bootargs root=/dev/nfs rw " \
745 "nfsroot=$serverip:$rootpath " \
746 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
747 "console=$consoledev,$baudrate $othbootargs;" \
748 "tftp $loadaddr $bootfile;" \
749 "tftp $fdtaddr $fdtfile;" \
750 "bootm $loadaddr - $fdtaddr"
751
752#define CONFIG_RAMBOOTCOMMAND \
753 "setenv bootargs root=/dev/ram rw " \
754 "console=$consoledev,$baudrate $othbootargs;" \
755 "tftp $ramdiskaddr $ramdiskfile;" \
756 "tftp $loadaddr $bootfile;" \
757 "tftp $fdtaddr $fdtfile;" \
758 "bootm $loadaddr $ramdiskaddr $fdtaddr"
759
760#define CONFIG_BOOTCOMMAND CONFIG_HDBOOT
761
762#endif /* __CONFIG_H */