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stroese13fdf8a2003-09-12 08:55:18 +00001/*
2 * (C) Copyright 2001-2003
3 * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
4 *
Wolfgang Denk3765b3e2013-10-07 13:07:26 +02005 * SPDX-License-Identifier: GPL-2.0+
stroese13fdf8a2003-09-12 08:55:18 +00006 */
7
8/*
9 * board/config.h - configuration options, board specific
10 */
11
12#ifndef __CONFIG_H
13#define __CONFIG_H
14
15/*
16 * High Level Configuration Options
17 * (easy to change)
18 */
19
20#define CONFIG_405EP 1 /* This is a PPC405 CPU */
wdenkc837dcb2004-01-20 23:12:12 +000021#define CONFIG_PLU405 1 /* ...on a PLU405 board */
stroese13fdf8a2003-09-12 08:55:18 +000022
Wolfgang Denk2ae18242010-10-06 09:05:45 +020023#define CONFIG_SYS_TEXT_BASE 0xFFF80000
Matthias Fuchsa5ee5c62015-01-12 22:47:33 +010024#define CONFIG_DISPLAY_BOARDINFO
Wolfgang Denk2ae18242010-10-06 09:05:45 +020025
wdenkc837dcb2004-01-20 23:12:12 +000026#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */
27#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */
stroese13fdf8a2003-09-12 08:55:18 +000028
stroesea20b27a2004-12-16 18:05:42 +000029#define CONFIG_SYS_CLK_FREQ 33333400 /* external frequency to pll */
stroese13fdf8a2003-09-12 08:55:18 +000030
31#define CONFIG_BAUDRATE 9600
stroese13fdf8a2003-09-12 08:55:18 +000032
33#undef CONFIG_BOOTARGS
stroesea20b27a2004-12-16 18:05:42 +000034#undef CONFIG_BOOTCOMMAND
stroese13fdf8a2003-09-12 08:55:18 +000035
stroesea20b27a2004-12-16 18:05:42 +000036#define CONFIG_PREBOOT /* enable preboot variable */
37
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020038#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
stroese13fdf8a2003-09-12 08:55:18 +000039
Matthias Fuchsf9fc6a52007-03-07 15:32:01 +010040#undef CONFIG_HAS_ETH1
stroesea20b27a2004-12-16 18:05:42 +000041
Ben Warren96e21f82008-10-27 23:50:15 -070042#define CONFIG_PPC4xx_EMAC
stroese13fdf8a2003-09-12 08:55:18 +000043#define CONFIG_MII 1 /* MII PHY management */
wdenkc837dcb2004-01-20 23:12:12 +000044#define CONFIG_PHY_ADDR 0 /* PHY address */
stroesea20b27a2004-12-16 18:05:42 +000045#define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */
Matthias Fuchs9ec367a2008-09-02 11:36:14 +020046#define CONFIG_RESET_PHY_R 1 /* use reset_phy() */
stroesea20b27a2004-12-16 18:05:42 +000047
48#define CONFIG_PHY_CLK_FREQ EMAC_STACR_CLK_66MHZ /* 66 MHz OPB clock*/
stroese13fdf8a2003-09-12 08:55:18 +000049
Jon Loeligeracf02692007-07-08 14:49:44 -050050/*
Jon Loeligera1aa0bb2007-07-10 09:22:23 -050051 * BOOTP options
52 */
53#define CONFIG_BOOTP_BOOTFILESIZE
54#define CONFIG_BOOTP_BOOTPATH
55#define CONFIG_BOOTP_GATEWAY
56#define CONFIG_BOOTP_HOSTNAME
57
Jon Loeligera1aa0bb2007-07-10 09:22:23 -050058/*
Jon Loeligeracf02692007-07-08 14:49:44 -050059 * Command line configuration.
60 */
Jon Loeligeracf02692007-07-08 14:49:44 -050061#define CONFIG_CMD_PCI
62#define CONFIG_CMD_IRQ
63#define CONFIG_CMD_IDE
Jon Loeligeracf02692007-07-08 14:49:44 -050064#define CONFIG_CMD_NAND
65#define CONFIG_CMD_DATE
Jon Loeligeracf02692007-07-08 14:49:44 -050066#define CONFIG_CMD_EEPROM
67
stroese13fdf8a2003-09-12 08:55:18 +000068#define CONFIG_MAC_PARTITION
69#define CONFIG_DOS_PARTITION
70
stroesea20b27a2004-12-16 18:05:42 +000071#define CONFIG_SUPPORT_VFAT
72
wdenkc837dcb2004-01-20 23:12:12 +000073#undef CONFIG_WATCHDOG /* watchdog disabled */
stroese13fdf8a2003-09-12 08:55:18 +000074
wdenkc837dcb2004-01-20 23:12:12 +000075#define CONFIG_RTC_MC146818 /* DS1685 is MC146818 compatible*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020076#define CONFIG_SYS_RTC_REG_BASE_ADDR 0xF0000500 /* RTC Base Address */
stroese13fdf8a2003-09-12 08:55:18 +000077
wdenkc837dcb2004-01-20 23:12:12 +000078#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
stroese13fdf8a2003-09-12 08:55:18 +000079
80/*
81 * Miscellaneous configurable options
82 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020083#define CONFIG_SYS_LONGHELP /* undef to save memory */
stroese13fdf8a2003-09-12 08:55:18 +000084
Jon Loeligeracf02692007-07-08 14:49:44 -050085#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020086#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
stroese13fdf8a2003-09-12 08:55:18 +000087#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020088#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
stroese13fdf8a2003-09-12 08:55:18 +000089#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020090#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
91#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
92#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
stroese13fdf8a2003-09-12 08:55:18 +000093
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020094#define CONFIG_SYS_DEVICE_NULLDEV 1 /* include nulldev device */
stroese13fdf8a2003-09-12 08:55:18 +000095
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020096#define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/
stroese13fdf8a2003-09-12 08:55:18 +000097
stroesea20b27a2004-12-16 18:05:42 +000098#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */
99
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200100#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
101#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
stroese13fdf8a2003-09-12 08:55:18 +0000102
Stefan Roese550650d2010-09-20 16:05:31 +0200103#define CONFIG_CONS_INDEX 1 /* Use UART0 */
Stefan Roese550650d2010-09-20 16:05:31 +0200104#define CONFIG_SYS_NS16550_SERIAL
105#define CONFIG_SYS_NS16550_REG_SIZE 1
106#define CONFIG_SYS_NS16550_CLK get_serial_clock()
107
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200108#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200109#define CONFIG_SYS_BASE_BAUD 691200
stroese13fdf8a2003-09-12 08:55:18 +0000110
111/* The following table includes the supported baudrates */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200112#define CONFIG_SYS_BAUDRATE_TABLE \
stroese13fdf8a2003-09-12 08:55:18 +0000113 { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \
114 57600, 115200, 230400, 460800, 921600 }
115
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200116#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
117#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */
stroese13fdf8a2003-09-12 08:55:18 +0000118
Matthias Fuchs17e65c22008-09-02 11:35:56 +0200119#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
stroese13fdf8a2003-09-12 08:55:18 +0000120#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
stroesea20b27a2004-12-16 18:05:42 +0000121#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */
122
wdenkc837dcb2004-01-20 23:12:12 +0000123#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
stroese13fdf8a2003-09-12 08:55:18 +0000124
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200125#define CONFIG_SYS_RX_ETH_BUFFER 16 /* use 16 rx buffer on 405 emac */
stroese13fdf8a2003-09-12 08:55:18 +0000126
Matthias Fuchs9ec367a2008-09-02 11:36:14 +0200127/*
stroese13fdf8a2003-09-12 08:55:18 +0000128 * NAND-FLASH stuff
stroese13fdf8a2003-09-12 08:55:18 +0000129 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200130#define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE}
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200131#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
Matthias Fuchsbd84ee42007-07-09 10:10:06 +0200132#define NAND_BIG_DELAY_US 25
Bartlomiej Siekaaddb2e12006-03-05 18:57:33 +0100133
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200134#define CONFIG_SYS_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */
135#define CONFIG_SYS_NAND_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */
136#define CONFIG_SYS_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */
137#define CONFIG_SYS_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */
stroese13fdf8a2003-09-12 08:55:18 +0000138
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200139#define CONFIG_SYS_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */
140#define CONFIG_SYS_NAND_QUIET 1
stroesea20b27a2004-12-16 18:05:42 +0000141
Matthias Fuchs9ec367a2008-09-02 11:36:14 +0200142/*
stroese13fdf8a2003-09-12 08:55:18 +0000143 * PCI stuff
stroese13fdf8a2003-09-12 08:55:18 +0000144 */
stroesea20b27a2004-12-16 18:05:42 +0000145#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */
146#define PCI_HOST_FORCE 1 /* configure as pci host */
147#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
stroese13fdf8a2003-09-12 08:55:18 +0000148
stroesea20b27a2004-12-16 18:05:42 +0000149#define CONFIG_PCI /* include pci support */
Gabor Juhos842033e2013-05-30 07:06:12 +0000150#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
Matthias Fuchs17e65c22008-09-02 11:35:56 +0200151#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */
stroesea20b27a2004-12-16 18:05:42 +0000152#define CONFIG_PCI_PNP /* do pci plug-and-play */
153 /* resource configuration */
stroese13fdf8a2003-09-12 08:55:18 +0000154
stroesea20b27a2004-12-16 18:05:42 +0000155#define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */
stroese13fdf8a2003-09-12 08:55:18 +0000156
stroesea20b27a2004-12-16 18:05:42 +0000157#define CONFIG_PCI_CONFIG_HOST_BRIDGE 1 /* don't skip host bridge config*/
158
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200159#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */
160#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0405 /* PCI Device ID: CPCI-405 */
161#define CONFIG_SYS_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/
162#define CONFIG_SYS_PCI_PTM1LA 0x00000000 /* point to sdram */
163#define CONFIG_SYS_PCI_PTM1MS 0xf8000001 /* 128MB, enable hard-wired to 1 */
164#define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
165#define CONFIG_SYS_PCI_PTM2LA 0xffc00000 /* point to flash */
166#define CONFIG_SYS_PCI_PTM2MS 0xffc00001 /* 4MB, enable */
167#define CONFIG_SYS_PCI_PTM2PCI 0x08000000 /* Host: use this pci address */
stroese13fdf8a2003-09-12 08:55:18 +0000168
Matthias Fuchs9ec367a2008-09-02 11:36:14 +0200169/*
stroese13fdf8a2003-09-12 08:55:18 +0000170 * IDE/ATA stuff
stroese13fdf8a2003-09-12 08:55:18 +0000171 */
wdenkc837dcb2004-01-20 23:12:12 +0000172#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */
173#undef CONFIG_IDE_LED /* no led for ide supported */
stroese13fdf8a2003-09-12 08:55:18 +0000174#define CONFIG_IDE_RESET 1 /* reset for ide supported */
175
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200176#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE busses */
Matthias Fuchs9ec367a2008-09-02 11:36:14 +0200177/* max. 1 drives per IDE bus */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200178#define CONFIG_SYS_IDE_MAXDEVICE (CONFIG_SYS_IDE_MAXBUS*1)
stroese13fdf8a2003-09-12 08:55:18 +0000179
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200180#define CONFIG_SYS_ATA_BASE_ADDR 0xF0100000
181#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
stroese13fdf8a2003-09-12 08:55:18 +0000182
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200183#define CONFIG_SYS_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O */
184#define CONFIG_SYS_ATA_REG_OFFSET 0x0000 /* Offset for normal register access */
185#define CONFIG_SYS_ATA_ALT_OFFSET 0x0000 /* Offset for alternate registers */
stroese13fdf8a2003-09-12 08:55:18 +0000186
187/*
188 * For booting Linux, the board info and command line data
189 * have to be in the first 8 MB of memory, since this is
190 * the maximum mapped by the Linux kernel during initialization.
191 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200192#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
Matthias Fuchs9ec367a2008-09-02 11:36:14 +0200193
194/*
stroese13fdf8a2003-09-12 08:55:18 +0000195 * FLASH organization
196 */
Matthias Fuchs9ec367a2008-09-02 11:36:14 +0200197#define FLASH_BASE0_PRELIM 0xFFC00000 /* FLASH bank #0 */
stroese13fdf8a2003-09-12 08:55:18 +0000198
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200199#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
200#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
stroese13fdf8a2003-09-12 08:55:18 +0000201
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200202#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
203#define CONFIG_SYS_FLASH_WRITE_TOUT 1000 /* Timeout for Flash Write (in ms) */
stroese13fdf8a2003-09-12 08:55:18 +0000204
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200205#define CONFIG_SYS_FLASH_WORD_SIZE unsigned short /* flash word size (width) */
206#define CONFIG_SYS_FLASH_ADDR0 0x5555 /* 1st addr for flash config cycles */
207#define CONFIG_SYS_FLASH_ADDR1 0x2AAA /* 2nd addr for flash config cycles */
stroese13fdf8a2003-09-12 08:55:18 +0000208/*
209 * The following defines are added for buggy IOP480 byte interface.
210 * All other boards should use the standard values (CPCI405 etc.)
211 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200212#define CONFIG_SYS_FLASH_READ0 0x0000 /* 0 is standard */
213#define CONFIG_SYS_FLASH_READ1 0x0001 /* 1 is standard */
214#define CONFIG_SYS_FLASH_READ2 0x0002 /* 2 is standard */
stroese13fdf8a2003-09-12 08:55:18 +0000215
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200216#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector */
stroese13fdf8a2003-09-12 08:55:18 +0000217
Matthias Fuchs9ec367a2008-09-02 11:36:14 +0200218/*
stroese13fdf8a2003-09-12 08:55:18 +0000219 * Start addresses for the final memory configuration
220 * (Set up by the startup code)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200221 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
stroese13fdf8a2003-09-12 08:55:18 +0000222 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200223#define CONFIG_SYS_SDRAM_BASE 0x00000000
Matthias Fuchs985edac2009-10-27 12:19:11 +0100224#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_MONITOR_BASE
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200225#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
226#define CONFIG_SYS_MONITOR_LEN (~(CONFIG_SYS_TEXT_BASE) + 1)
Matthias Fuchs985edac2009-10-27 12:19:11 +0100227#define CONFIG_SYS_MALLOC_LEN (1024 << 10)
stroese13fdf8a2003-09-12 08:55:18 +0000228
Matthias Fuchs9ec367a2008-09-02 11:36:14 +0200229/*
stroese13fdf8a2003-09-12 08:55:18 +0000230 * Environment Variable setup
231 */
Jean-Christophe PLAGNIOL-VILLARDbb1f8b42008-09-05 09:19:30 +0200232#define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200233#define CONFIG_ENV_OFFSET 0x100 /* reseve 0x100 bytes for strapping */
234#define CONFIG_ENV_SIZE 0x700
stroese13fdf8a2003-09-12 08:55:18 +0000235
Matthias Fuchs9ec367a2008-09-02 11:36:14 +0200236/*
237 * I2C EEPROM (24WC16) for environment
stroese13fdf8a2003-09-12 08:55:18 +0000238 */
Dirk Eibach880540d2013-04-25 02:40:01 +0000239#define CONFIG_SYS_I2C
240#define CONFIG_SYS_I2C_PPC4XX
241#define CONFIG_SYS_I2C_PPC4XX_CH0
242#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000
243#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F
stroese13fdf8a2003-09-12 08:55:18 +0000244
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200245#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM 24WC16 */
246#define CONFIG_SYS_EEPROM_WREN 1
Matthias Fuchsbd84ee42007-07-09 10:10:06 +0200247
Matthias Fuchs9ec367a2008-09-02 11:36:14 +0200248/* 24WC16 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200249#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
Matthias Fuchs9ec367a2008-09-02 11:36:14 +0200250/* mask of address bits that overflow into the "EEPROM chip address" */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200251#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07
252#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* The 24WC16 has */
Matthias Fuchs9ec367a2008-09-02 11:36:14 +0200253 /* 16 byte page write mode using */
254 /* last 4 bits of the address */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200255#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
stroese13fdf8a2003-09-12 08:55:18 +0000256
Matthias Fuchs9ec367a2008-09-02 11:36:14 +0200257/*
stroese13fdf8a2003-09-12 08:55:18 +0000258 * External Bus Controller (EBC) Setup
259 */
Matthias Fuchsbe0db3e2009-10-26 09:58:45 +0100260#define CAN0_BA 0xF0000000 /* CAN0 Base Address */
261#define CAN1_BA 0xF0000100 /* CAN1 Base Address */
Matthias Fuchs9ec367a2008-09-02 11:36:14 +0200262#define DUART0_BA 0xF0000400 /* DUART Base Address */
263#define DUART1_BA 0xF0000408 /* DUART Base Address */
264#define RTC_BA 0xF0000500 /* RTC Base Address */
265#define VGA_BA 0xF1000000 /* Epson VGA Base Address */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200266#define CONFIG_SYS_NAND_BASE 0xF4000000 /* NAND FLASH Base Address */
stroese13fdf8a2003-09-12 08:55:18 +0000267
Matthias Fuchs9ec367a2008-09-02 11:36:14 +0200268/* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization */
269/* TWT=16,CSN=1,OEN=1,WBN=1,WBF=1,TH=4,SOR=1 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200270#define CONFIG_SYS_EBC_PB0AP 0x92015480
Matthias Fuchs9ec367a2008-09-02 11:36:14 +0200271/* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200272#define CONFIG_SYS_EBC_PB0CR 0xFFC5A000
stroese13fdf8a2003-09-12 08:55:18 +0000273
Matthias Fuchs9ec367a2008-09-02 11:36:14 +0200274/* Memory Bank 1 (Flash Bank 1, NAND-FLASH) initialization */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200275#define CONFIG_SYS_EBC_PB1AP 0x92015480
Matthias Fuchs9ec367a2008-09-02 11:36:14 +0200276/* BAS=0xF40,BS=1MB,BU=R/W,BW=8bit */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200277#define CONFIG_SYS_EBC_PB1CR 0xF4018000
stroese13fdf8a2003-09-12 08:55:18 +0000278
Matthias Fuchs9ec367a2008-09-02 11:36:14 +0200279/* Memory Bank 2 (8 Bit Peripheral: CAN, UART, RTC) initialization */
280/* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200281#define CONFIG_SYS_EBC_PB2AP 0x010053C0
Matthias Fuchs9ec367a2008-09-02 11:36:14 +0200282/* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200283#define CONFIG_SYS_EBC_PB2CR 0xF0018000
stroese13fdf8a2003-09-12 08:55:18 +0000284
Matthias Fuchs9ec367a2008-09-02 11:36:14 +0200285/* Memory Bank 3 (16 Bit Peripheral: FPGA internal, dig. IO) initialization */
286/* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200287#define CONFIG_SYS_EBC_PB3AP 0x010053C0
Matthias Fuchs9ec367a2008-09-02 11:36:14 +0200288/* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200289#define CONFIG_SYS_EBC_PB3CR 0xF011A000
stroese13fdf8a2003-09-12 08:55:18 +0000290
Matthias Fuchs9ec367a2008-09-02 11:36:14 +0200291/*
stroese13fdf8a2003-09-12 08:55:18 +0000292 * FPGA stuff
293 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200294#define CONFIG_SYS_FPGA_BASE_ADDR 0xF0100100 /* FPGA internal Base Address */
stroese13fdf8a2003-09-12 08:55:18 +0000295
296/* FPGA internal regs */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200297#define CONFIG_SYS_FPGA_CTRL 0x000
stroese13fdf8a2003-09-12 08:55:18 +0000298
299/* FPGA Control Reg */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200300#define CONFIG_SYS_FPGA_CTRL_CF_RESET 0x0001
301#define CONFIG_SYS_FPGA_CTRL_WDI 0x0002
302#define CONFIG_SYS_FPGA_CTRL_PS2_RESET 0x0020
stroese13fdf8a2003-09-12 08:55:18 +0000303
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200304#define CONFIG_SYS_FPGA_SPARTAN2 1 /* using Xilinx Spartan 2 now */
305#define CONFIG_SYS_FPGA_MAX_SIZE 128*1024 /* 128kByte is enough for XC2S50E*/
stroese13fdf8a2003-09-12 08:55:18 +0000306
307/* FPGA program pin configuration */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200308#define CONFIG_SYS_FPGA_PRG 0x04000000 /* FPGA program pin (ppc output) */
309#define CONFIG_SYS_FPGA_CLK 0x02000000 /* FPGA clk pin (ppc output) */
310#define CONFIG_SYS_FPGA_DATA 0x01000000 /* FPGA data pin (ppc output) */
311#define CONFIG_SYS_FPGA_INIT 0x00010000 /* FPGA init pin (ppc input) */
312#define CONFIG_SYS_FPGA_DONE 0x00008000 /* FPGA done pin (ppc input) */
stroese13fdf8a2003-09-12 08:55:18 +0000313
Matthias Fuchs9ec367a2008-09-02 11:36:14 +0200314/*
stroese13fdf8a2003-09-12 08:55:18 +0000315 * Definitions for initial stack pointer and data area (in data cache)
316 */
317/* use on chip memory ( OCM ) for temperary stack until sdram is tested */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200318#define CONFIG_SYS_TEMP_STACK_OCM 1
stroese13fdf8a2003-09-12 08:55:18 +0000319
320/* On Chip Memory location */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200321#define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000
322#define CONFIG_SYS_OCM_DATA_SIZE 0x1000
323#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM */
Wolfgang Denk553f0982010-10-26 13:32:32 +0200324#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM */
stroese13fdf8a2003-09-12 08:55:18 +0000325
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200326#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200327#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
stroese13fdf8a2003-09-12 08:55:18 +0000328
Matthias Fuchs9ec367a2008-09-02 11:36:14 +0200329/*
stroese13fdf8a2003-09-12 08:55:18 +0000330 * Definitions for GPIO setup (PPC405EP specific)
331 *
wdenkc837dcb2004-01-20 23:12:12 +0000332 * GPIO0[0] - External Bus Controller BLAST output
333 * GPIO0[1-9] - Instruction trace outputs -> GPIO
stroese13fdf8a2003-09-12 08:55:18 +0000334 * GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs
335 * GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs -> GPIO
336 * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs
337 * GPIO0[24-27] - UART0 control signal inputs/outputs
338 * GPIO0[28-29] - UART1 data signal input/output
339 * GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs
340 */
Stefan Roeseafabb492010-09-12 06:21:37 +0200341#define CONFIG_SYS_GPIO0_OSRL 0x00000550
342#define CONFIG_SYS_GPIO0_OSRH 0x00000110
343#define CONFIG_SYS_GPIO0_ISR1L 0x00000000
344#define CONFIG_SYS_GPIO0_ISR1H 0x15555445
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200345#define CONFIG_SYS_GPIO0_TSRL 0x00000000
Stefan Roeseafabb492010-09-12 06:21:37 +0200346#define CONFIG_SYS_GPIO0_TSRH 0x00000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200347#define CONFIG_SYS_GPIO0_TCR 0x77FE0014
stroese13fdf8a2003-09-12 08:55:18 +0000348
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200349#define CONFIG_SYS_DUART_RST (0x80000000 >> 14)
350#define CONFIG_SYS_EEPROM_WP (0x80000000 >> 0)
stroese13fdf8a2003-09-12 08:55:18 +0000351
352/*
Matthias Fuchs9ec367a2008-09-02 11:36:14 +0200353 * Default speed selection (cpu_plb_opb_ebc) in MHz.
stroese13fdf8a2003-09-12 08:55:18 +0000354 * This value will be set if iic boot eprom is disabled.
355 */
Matthias Fuchs17e65c22008-09-02 11:35:56 +0200356#if 1
wdenkc837dcb2004-01-20 23:12:12 +0000357#define PLLMR0_DEFAULT PLLMR0_266_133_66_33
358#define PLLMR1_DEFAULT PLLMR1_266_133_66_33
stroese13fdf8a2003-09-12 08:55:18 +0000359#endif
360#if 0
wdenkc837dcb2004-01-20 23:12:12 +0000361#define PLLMR0_DEFAULT PLLMR0_200_100_50_33
362#define PLLMR1_DEFAULT PLLMR1_200_100_50_33
stroese13fdf8a2003-09-12 08:55:18 +0000363#endif
Matthias Fuchs17e65c22008-09-02 11:35:56 +0200364#if 0
wdenkc837dcb2004-01-20 23:12:12 +0000365#define PLLMR0_DEFAULT PLLMR0_133_66_66_33
366#define PLLMR1_DEFAULT PLLMR1_133_66_66_33
stroese13fdf8a2003-09-12 08:55:18 +0000367#endif
368
Matthias Fuchs17e65c22008-09-02 11:35:56 +0200369/*
370 * PCI OHCI controller
371 */
372#define CONFIG_USB_OHCI_NEW 1
373#define CONFIG_PCI_OHCI 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200374#define CONFIG_SYS_OHCI_SWAP_REG_ACCESS 1
375#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15
376#define CONFIG_SYS_USB_OHCI_SLOT_NAME "ohci_pci"
Matthias Fuchs17e65c22008-09-02 11:35:56 +0200377#define CONFIG_USB_STORAGE 1
378
Matthias Fuchs985edac2009-10-27 12:19:11 +0100379/*
380 * UBI
381 */
382#define CONFIG_CMD_UBI
383#define CONFIG_RBTREE
384#define CONFIG_MTD_DEVICE
385#define CONFIG_MTD_PARTITIONS
386#define CONFIG_CMD_MTDPARTS
387#define CONFIG_LZO
388
stroese13fdf8a2003-09-12 08:55:18 +0000389#endif /* __CONFIG_H */