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Siva Durga Prasad Paladugu0b54a9d2015-06-10 15:50:57 +05301/*
Michal Simekd041e3e2015-08-20 15:21:48 +02002 * Configuration for Xilinx ZynqMP emulation platforms
Siva Durga Prasad Paladugu0b54a9d2015-06-10 15:50:57 +05303 *
4 * (C) Copyright 2014 - 2015 Xilinx, Inc.
5 * Michal Simek <michal.simek@xilinx.com>
6 * Siva Durga Prasad Paladugu <sivadur@xilinx.com>
7 *
8 * Based on Configuration for Versatile Express
9 *
10 * SPDX-License-Identifier: GPL-2.0+
11 */
12
13#ifndef __CONFIG_ZYNQMP_EP_H
14#define __CONFIG_ZYNQMP_EP_H
15
Michal Simekf3bd7282015-09-29 01:27:13 +020016#define CONFIG_ZYNQ_SDHCI_MAX_FREQ 52000000
Siva Durga Prasad Paladuguc061d5b2016-01-05 12:21:05 +053017#define CONFIG_ZYNQ_SDHCI_MIN_FREQ (CONFIG_ZYNQ_SDHCI_MAX_FREQ << 9)
Siva Durga Prasad Paladugu0b54a9d2015-06-10 15:50:57 +053018#define CONFIG_ZYNQ_EEPROM
Michal Simek6fe6f132015-07-23 13:27:40 +020019#define CONFIG_AHCI
Siva Durga Prasad Paladuguf4dd69c2015-11-16 16:49:23 +053020#define CONFIG_ZYNQMP_XHCI_LIST {ZYNQMP_USB0_XHCI_BASEADDR, \
21 ZYNQMP_USB1_XHCI_BASEADDR}
Siva Durga Prasad Paladugu0b54a9d2015-06-10 15:50:57 +053022
Michal Simek713b6162015-11-05 08:32:14 +010023#define COUNTER_FREQUENCY 4000000
24
Siva Durga Prasad Paladugu407b76f2015-11-02 19:45:35 +053025#define CONFIG_KERNEL_FDT_OFST_SIZE \
26 "kernel_offset=0x400000\0" \
27 "fdt_offset=0x2400000\0" \
28 "kernel_size=0x2000000\0" \
29 "fdt_size=0x80000\0" \
30 "board=ep108\0"
31
Siva Durga Prasad Paladugu0b54a9d2015-06-10 15:50:57 +053032#include <configs/xilinx_zynqmp.h>
33
34#endif /* __CONFIG_ZYNQMP_EP_H */