blob: 8c2ca65a91cc81f90280e9d237a4b14f8eb689b4 [file] [log] [blame]
Lunsheng Wangb0e32942005-07-29 10:20:29 -05001/*
2* Copyright (C) 2002,2003, Motorola Inc.
3* Xianghua Xiao <X.Xiao@motorola.com>
4*
5* See file CREDITS for list of people who contributed to this
6* project.
7*
8* This program is free software; you can redistribute it and/or
9* modify it under the terms of the GNU General Public License as
10* published by the Free Software Foundation; either version 2 of
11* the License, or (at your option) any later version.
12*
13* This program is distributed in the hope that it will be useful,
14* but WITHOUT ANY WARRANTY; without even the implied warranty of
15* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16* GNU General Public License for more details.
17*
18* You should have received a copy of the GNU General Public License
19* along with this program; if not, write to the Free Software
20* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21* MA 02111-1307 USA
22*/
23
24#include <ppc_asm.tmpl>
25#include <ppc_defs.h>
26#include <asm/cache.h>
27#include <asm/mmu.h>
28#include <config.h>
29#include <mpc85xx.h>
30
31#define entry_start \
32 mflr r1 ; \
33 bl 0f ;
34
35#define entry_end \
360: mflr r0 ; \
37 mtlr r1 ; \
38 blr ;
39
40/* TLB1 entries configuration: */
41
42 .section .bootpg, "ax"
43 .globl tlb1_entry
44tlb1_entry:
45 entry_start
46
47 .long 0x0a /* the following data table uses a few of 16 TLB entries */
48
49 .long TLB1_MAS0(1,1,0)
50 .long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_1M)
51 .long TLB1_MAS2(((CFG_CCSRBAR>>12) & 0xfffff),0,0,0,0,1,0,1,0)
52 .long TLB1_MAS3(((CFG_CCSRBAR>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
53
54 #if defined(CFG_FLASH_PORT_WIDTH_16)
55 .long TLB1_MAS0(1,2,0)
56 .long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_4M)
57 .long TLB1_MAS2(((CFG_FLASH_BASE>>12) & 0xfffff),0,0,0,0,1,0,1,0)
58 .long TLB1_MAS3(((CFG_FLASH_BASE>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
59
60 .long TLB1_MAS0(1,3,0)
61 .long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_4M)
62 .long TLB1_MAS2((((CFG_FLASH_BASE+0x400000)>>12)&0xfffff),0,0,0,0,1,0,1,0)
63 .long TLB1_MAS3((((CFG_FLASH_BASE+0x400000)>>12)&0xfffff),0,0,0,0,0,1,0,1,0,1)
64 #else
65 .long TLB1_MAS0(1,2,0)
66 .long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_16M)
67 .long TLB1_MAS2(((CFG_FLASH_BASE>>12) & 0xfffff),0,0,0,0,1,0,1,0)
68 .long TLB1_MAS3(((CFG_FLASH_BASE>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
69
70 .long TLB1_MAS0(1,3,0)
71 .long TLB1_MAS1(0,0,0,0,BOOKE_PAGESZ_1M)
72 .long TLB1_MAS2(0,0,0,0,0,0,0,0,0)
73 .long TLB1_MAS3(0,0,0,0,0,0,1,0,1,0,1)
74 #endif
75
76 #if !defined(CONFIG_SPD_EEPROM)
77 .long TLB1_MAS0(1,4,0)
78 .long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_64M)
79 .long TLB1_MAS2(((CFG_DDR_SDRAM_BASE>>12) & 0xfffff),0,0,0,0,0,0,0,0)
80 .long TLB1_MAS3(((CFG_DDR_SDRAM_BASE>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
81
82 .long TLB1_MAS0(1,5,0)
83 .long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_64M)
84 .long TLB1_MAS2((((CFG_DDR_SDRAM_BASE+0x4000000)>>12) & 0xfffff),0,0,0,0,0,0,0,0)
85 .long TLB1_MAS3((((CFG_DDR_SDRAM_BASE+0x4000000)>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
86 #else
87 .long TLB1_MAS0(1,4,0)
88 .long TLB1_MAS1(0,0,0,0,BOOKE_PAGESZ_1M)
89 .long TLB1_MAS2(0,0,0,0,0,0,0,0,0)
90 .long TLB1_MAS3(0,0,0,0,0,0,1,0,1,0,1)
91
92 .long TLB1_MAS0(1,5,0)
93 .long TLB1_MAS1(0,0,0,0,BOOKE_PAGESZ_1M)
94 .long TLB1_MAS2(0,0,0,0,0,0,0,0,0)
95 .long TLB1_MAS3(0,0,0,0,0,0,1,0,1,0,1)
96 #endif
97
98 .long TLB1_MAS0(1,6,0)
99 .long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_64M)
100 #if defined(CONFIG_RAM_AS_FLASH)
101 .long TLB1_MAS2(((CFG_LBC_SDRAM_BASE>>12) & 0xfffff),0,0,0,0,1,0,1,0)
102 #else
103 .long TLB1_MAS2(((CFG_LBC_SDRAM_BASE>>12) & 0xfffff),0,0,0,0,0,0,0,0)
104 #endif
105 .long TLB1_MAS3(((CFG_LBC_SDRAM_BASE>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
106
107 .long TLB1_MAS0(1,7,0)
108 .long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_16K)
109 #ifdef CONFIG_L2_INIT_RAM
110 .long TLB1_MAS2(((CFG_INIT_RAM_ADDR>>12) & 0xfffff),0,0,0,1,0,0,0,0)
111 #else
112 .long TLB1_MAS2(((CFG_INIT_RAM_ADDR>>12) & 0xfffff),0,0,0,0,0,0,0,0)
113 #endif
114 .long TLB1_MAS3(((CFG_INIT_RAM_ADDR>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
115
116 .long TLB1_MAS0(1,8,0)
117 .long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_256M)
118 .long TLB1_MAS2(((CFG_PCI_MEM_BASE>>12) & 0xfffff),0,0,0,0,1,0,1,0)
119 .long TLB1_MAS3(((CFG_PCI_MEM_BASE>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
120
121 .long TLB1_MAS0(1,9,0)
122 .long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_16K)
123 .long TLB1_MAS2(((CFG_BCSR>>12) & 0xfffff),0,0,0,0,1,0,1,0)
124 .long TLB1_MAS3(((CFG_BCSR>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
125
126 #if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR)
127 .long TLB1_MAS0(1,15,0)
128 .long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_1M)
129 .long TLB1_MAS2(((CFG_CCSRBAR_DEFAULT>>12) & 0xfffff),0,0,0,0,1,0,1,0)
130 .long TLB1_MAS3(((CFG_CCSRBAR_DEFAULT>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
131 #else
132 .long TLB1_MAS0(1,15,0)
133 .long TLB1_MAS1(0,0,0,0,BOOKE_PAGESZ_1M)
134 .long TLB1_MAS2(0,0,0,0,0,0,0,0,0)
135 .long TLB1_MAS3(0,0,0,0,0,0,1,0,1,0,1)
136 #endif
137 entry_end
138
139/* LAW(Local Access Window) configuration:
140 * 0000_0000-0800_0000: DDR(128M) -or- larger
141 * f000_0000-f3ff_ffff: PCI(256M)
142 * f400_0000-f7ff_ffff: RapidIO(128M)
143 * f800_0000-ffff_ffff: localbus(128M)
144 * f800_0000-fbff_ffff: LBC SDRAM(64M)
145 * fc00_0000-fdef_ffff: LBC BCSR,RTC,etc(31M)
146 * fdf0_0000-fdff_ffff: CCSRBAR(1M)
147 * fe00_0000-ffff_ffff: Flash(32M)
148 * Note: CCSRBAR and L2-as-SRAM don't need configure Local Access
149 * Window.
150 * Note: If flash is 8M at default position(last 8M),no LAW needed.
151 */
152
153#if !defined(CONFIG_SPD_EEPROM)
154#define LAWBAR0 ((CFG_DDR_SDRAM_BASE>>12) & 0xfffff)
155#define LAWAR0 (LAWAR_EN | LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M))
156#else
157#define LAWBAR0 0
158#define LAWAR0 ((LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN)
159#endif
160
161#define LAWBAR1 ((CFG_PCI_MEM_BASE>>12) & 0xfffff)
162#define LAWAR1 (LAWAR_EN | LAWAR_TRGT_IF_PCIX | (LAWAR_SIZE & LAWAR_SIZE_256M))
163
164#if !defined(CONFIG_RAM_AS_FLASH)
165#define LAWBAR2 ((CFG_LBC_SDRAM_BASE>>12) & 0xfffff)
166#define LAWAR2 (LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_128M))
167#else
168#define LAWBAR2 0
169#define LAWAR2 ((LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN)
170#endif
171
172 .section .bootpg, "ax"
173 .globl law_entry
174law_entry:
175 entry_start
176 .long 0x03
177 .long LAWBAR0,LAWAR0,LAWBAR1,LAWAR1,LAWBAR2,LAWAR2
178 entry_end