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gerrit.devboardsforandroid.linaro.org / platform / external / u-boot / 252c8b45c90b6fe2c523f805e7e1670c2fbe5f69 / . / arch / arm / dts / r8a7792.dtsi
blob: 8e26dede308b2c252408559f49d1cc246346b4bb [file] [log] [blame]
Tom Rini83d290c2018-05-06 17:58:06 -0400[diff] [blame]1// SPDX-License-Identifier: GPL-2.0
Marek Vasuta3fb9ff2018-01-07 20:17:53 +0100[diff] [blame]2/*
3 * Device Tree Source for the r8a7792 SoC
4 *
5 * Copyright (C) 2016 Cogent Embedded Inc.
Marek Vasuta3fb9ff2018-01-07 20:17:53 +0100[diff] [blame]6 */
7
8#include <dt-bindings/clock/r8a7792-cpg-mssr.h>
9#include <dt-bindings/interrupt-controller/irq.h>
10#include <dt-bindings/interrupt-controller/arm-gic.h>
11#include <dt-bindings/power/r8a7792-sysc.h>
12
13/ {
14 compatible = "renesas,r8a7792";
15 #address-cells = <2>;
16 #size-cells = <2>;
17
18 aliases {
19 i2c0 = &i2c0;
20 i2c1 = &i2c1;
21 i2c2 = &i2c2;
22 i2c3 = &i2c3;
23 i2c4 = &i2c4;
24 i2c5 = &i2c5;
25 spi0 = &qspi;
26 spi1 = &msiof0;
27 spi2 = &msiof1;
28 vin0 = &vin0;
29 vin1 = &vin1;
30 vin2 = &vin2;
31 vin3 = &vin3;
32 vin4 = &vin4;
33 vin5 = &vin5;
34 };
35
Marek Vasut252c8b42018-06-06 19:58:17 +0200[diff] [blame^]36 /* External CAN clock */
37 can_clk: can {
38 compatible = "fixed-clock";
39 #clock-cells = <0>;
40 /* This value must be overridden by the board. */
41 clock-frequency = <0>;
42 };
43
Marek Vasuta3fb9ff2018-01-07 20:17:53 +0100[diff] [blame]44 cpus {
45 #address-cells = <1>;
46 #size-cells = <0>;
47 enable-method = "renesas,apmu";
48
49 cpu0: cpu@0 {
50 device_type = "cpu";
51 compatible = "arm,cortex-a15";
52 reg = <0>;
53 clock-frequency = <1000000000>;
54 clocks = <&cpg CPG_CORE R8A7792_CLK_Z>;
55 power-domains = <&sysc R8A7792_PD_CA15_CPU0>;
56 next-level-cache = <&L2_CA15>;
57 };
58
59 cpu1: cpu@1 {
60 device_type = "cpu";
61 compatible = "arm,cortex-a15";
62 reg = <1>;
63 clock-frequency = <1000000000>;
64 clocks = <&cpg CPG_CORE R8A7792_CLK_Z>;
65 power-domains = <&sysc R8A7792_PD_CA15_CPU1>;
66 next-level-cache = <&L2_CA15>;
67 };
68
69 L2_CA15: cache-controller-0 {
70 compatible = "cache";
71 cache-unified;
72 cache-level = <2>;
73 power-domains = <&sysc R8A7792_PD_CA15_SCU>;
74 };
75 };
76
Marek Vasut252c8b42018-06-06 19:58:17 +0200[diff] [blame^]77 /* External root clock */
78 extal_clk: extal {
79 compatible = "fixed-clock";
80 #clock-cells = <0>;
81 /* This value must be overridden by the board. */
82 clock-frequency = <0>;
83 };
84
85 /* External SCIF clock */
86 scif_clk: scif {
87 compatible = "fixed-clock";
88 #clock-cells = <0>;
89 /* This value must be overridden by the board. */
90 clock-frequency = <0>;
91 };
92
Marek Vasuta3fb9ff2018-01-07 20:17:53 +0100[diff] [blame]93 soc {
94 compatible = "simple-bus";
95 interrupt-parent = <&gic>;
96
97 #address-cells = <2>;
98 #size-cells = <2>;
99 ranges;
100
Marek Vasuta3fb9ff2018-01-07 20:17:53 +0100[diff] [blame]101 gpio0: gpio@e6050000 {
102 compatible = "renesas,gpio-r8a7792",
103 "renesas,rcar-gen2-gpio";
104 reg = <0 0xe6050000 0 0x50>;
105 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
106 #gpio-cells = <2>;
107 gpio-controller;
108 gpio-ranges = <&pfc 0 0 29>;
109 #interrupt-cells = <2>;
110 interrupt-controller;
111 clocks = <&cpg CPG_MOD 912>;
112 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
113 resets = <&cpg 912>;
114 };
115
116 gpio1: gpio@e6051000 {
117 compatible = "renesas,gpio-r8a7792",
118 "renesas,rcar-gen2-gpio";
119 reg = <0 0xe6051000 0 0x50>;
120 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
121 #gpio-cells = <2>;
122 gpio-controller;
123 gpio-ranges = <&pfc 0 32 23>;
124 #interrupt-cells = <2>;
125 interrupt-controller;
126 clocks = <&cpg CPG_MOD 911>;
127 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
128 resets = <&cpg 911>;
129 };
130
131 gpio2: gpio@e6052000 {
132 compatible = "renesas,gpio-r8a7792",
133 "renesas,rcar-gen2-gpio";
134 reg = <0 0xe6052000 0 0x50>;
135 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
136 #gpio-cells = <2>;
137 gpio-controller;
138 gpio-ranges = <&pfc 0 64 32>;
139 #interrupt-cells = <2>;
140 interrupt-controller;
141 clocks = <&cpg CPG_MOD 910>;
142 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
143 resets = <&cpg 910>;
144 };
145
146 gpio3: gpio@e6053000 {
147 compatible = "renesas,gpio-r8a7792",
148 "renesas,rcar-gen2-gpio";
149 reg = <0 0xe6053000 0 0x50>;
150 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
151 #gpio-cells = <2>;
152 gpio-controller;
153 gpio-ranges = <&pfc 0 96 28>;
154 #interrupt-cells = <2>;
155 interrupt-controller;
156 clocks = <&cpg CPG_MOD 909>;
157 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
158 resets = <&cpg 909>;
159 };
160
161 gpio4: gpio@e6054000 {
162 compatible = "renesas,gpio-r8a7792",
163 "renesas,rcar-gen2-gpio";
164 reg = <0 0xe6054000 0 0x50>;
165 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
166 #gpio-cells = <2>;
167 gpio-controller;
168 gpio-ranges = <&pfc 0 128 17>;
169 #interrupt-cells = <2>;
170 interrupt-controller;
171 clocks = <&cpg CPG_MOD 908>;
172 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
173 resets = <&cpg 908>;
174 };
175
176 gpio5: gpio@e6055000 {
177 compatible = "renesas,gpio-r8a7792",
178 "renesas,rcar-gen2-gpio";
179 reg = <0 0xe6055000 0 0x50>;
180 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
181 #gpio-cells = <2>;
182 gpio-controller;
183 gpio-ranges = <&pfc 0 160 17>;
184 #interrupt-cells = <2>;
185 interrupt-controller;
186 clocks = <&cpg CPG_MOD 907>;
187 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
188 resets = <&cpg 907>;
189 };
190
191 gpio6: gpio@e6055100 {
192 compatible = "renesas,gpio-r8a7792",
193 "renesas,rcar-gen2-gpio";
194 reg = <0 0xe6055100 0 0x50>;
195 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
196 #gpio-cells = <2>;
197 gpio-controller;
198 gpio-ranges = <&pfc 0 192 17>;
199 #interrupt-cells = <2>;
200 interrupt-controller;
201 clocks = <&cpg CPG_MOD 905>;
202 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
203 resets = <&cpg 905>;
204 };
205
206 gpio7: gpio@e6055200 {
207 compatible = "renesas,gpio-r8a7792",
208 "renesas,rcar-gen2-gpio";
209 reg = <0 0xe6055200 0 0x50>;
210 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
211 #gpio-cells = <2>;
212 gpio-controller;
213 gpio-ranges = <&pfc 0 224 17>;
214 #interrupt-cells = <2>;
215 interrupt-controller;
216 clocks = <&cpg CPG_MOD 904>;
217 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
218 resets = <&cpg 904>;
219 };
220
221 gpio8: gpio@e6055300 {
222 compatible = "renesas,gpio-r8a7792",
223 "renesas,rcar-gen2-gpio";
224 reg = <0 0xe6055300 0 0x50>;
225 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
226 #gpio-cells = <2>;
227 gpio-controller;
228 gpio-ranges = <&pfc 0 256 17>;
229 #interrupt-cells = <2>;
230 interrupt-controller;
231 clocks = <&cpg CPG_MOD 921>;
232 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
233 resets = <&cpg 921>;
234 };
235
236 gpio9: gpio@e6055400 {
237 compatible = "renesas,gpio-r8a7792",
238 "renesas,rcar-gen2-gpio";
239 reg = <0 0xe6055400 0 0x50>;
240 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
241 #gpio-cells = <2>;
242 gpio-controller;
243 gpio-ranges = <&pfc 0 288 17>;
244 #interrupt-cells = <2>;
245 interrupt-controller;
246 clocks = <&cpg CPG_MOD 919>;
247 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
248 resets = <&cpg 919>;
249 };
250
251 gpio10: gpio@e6055500 {
252 compatible = "renesas,gpio-r8a7792",
253 "renesas,rcar-gen2-gpio";
254 reg = <0 0xe6055500 0 0x50>;
255 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
256 #gpio-cells = <2>;
257 gpio-controller;
258 gpio-ranges = <&pfc 0 320 32>;
259 #interrupt-cells = <2>;
260 interrupt-controller;
261 clocks = <&cpg CPG_MOD 914>;
262 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
263 resets = <&cpg 914>;
264 };
265
266 gpio11: gpio@e6055600 {
267 compatible = "renesas,gpio-r8a7792",
268 "renesas,rcar-gen2-gpio";
269 reg = <0 0xe6055600 0 0x50>;
270 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
271 #gpio-cells = <2>;
272 gpio-controller;
273 gpio-ranges = <&pfc 0 352 30>;
274 #interrupt-cells = <2>;
275 interrupt-controller;
276 clocks = <&cpg CPG_MOD 913>;
277 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
278 resets = <&cpg 913>;
279 };
280
Marek Vasut252c8b42018-06-06 19:58:17 +0200[diff] [blame^]281 pfc: pin-controller@e6060000 {
282 compatible = "renesas,pfc-r8a7792";
283 reg = <0 0xe6060000 0 0x144>;
284 };
285
286 cpg: clock-controller@e6150000 {
287 compatible = "renesas,r8a7792-cpg-mssr";
288 reg = <0 0xe6150000 0 0x1000>;
289 clocks = <&extal_clk>;
290 clock-names = "extal";
291 #clock-cells = <2>;
292 #power-domain-cells = <0>;
293 #reset-cells = <1>;
294 };
295
296 apmu@e6152000 {
297 compatible = "renesas,r8a7792-apmu", "renesas,apmu";
298 reg = <0 0xe6152000 0 0x188>;
299 cpus = <&cpu0 &cpu1>;
300 };
301
302 rst: reset-controller@e6160000 {
303 compatible = "renesas,r8a7792-rst";
304 reg = <0 0xe6160000 0 0x0100>;
305 };
306
307 sysc: system-controller@e6180000 {
308 compatible = "renesas,r8a7792-sysc";
309 reg = <0 0xe6180000 0 0x0200>;
310 #power-domain-cells = <1>;
311 };
312
313 irqc: interrupt-controller@e61c0000 {
314 compatible = "renesas,irqc-r8a7792", "renesas,irqc";
315 #interrupt-cells = <2>;
316 interrupt-controller;
317 reg = <0 0xe61c0000 0 0x200>;
318 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
319 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
320 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
321 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
322 clocks = <&cpg CPG_MOD 407>;
323 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
324 resets = <&cpg 407>;
325 };
326
327 icram0: sram@e63a0000 {
328 compatible = "mmio-sram";
329 reg = <0 0xe63a0000 0 0x12000>;
330 };
331
332 icram1: sram@e63c0000 {
333 compatible = "mmio-sram";
334 reg = <0 0xe63c0000 0 0x1000>;
335 #address-cells = <1>;
336 #size-cells = <1>;
337 ranges = <0 0 0xe63c0000 0x1000>;
338
339 smp-sram@0 {
340 compatible = "renesas,smp-sram";
341 reg = <0 0x10>;
342 };
343 };
344
345 /* I2C doesn't need pinmux */
346 i2c0: i2c@e6508000 {
347 compatible = "renesas,i2c-r8a7792",
348 "renesas,rcar-gen2-i2c";
349 reg = <0 0xe6508000 0 0x40>;
350 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
351 clocks = <&cpg CPG_MOD 931>;
352 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
353 resets = <&cpg 931>;
354 i2c-scl-internal-delay-ns = <6>;
355 #address-cells = <1>;
356 #size-cells = <0>;
357 status = "disabled";
358 };
359
360 i2c1: i2c@e6518000 {
361 compatible = "renesas,i2c-r8a7792",
362 "renesas,rcar-gen2-i2c";
363 reg = <0 0xe6518000 0 0x40>;
364 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
365 clocks = <&cpg CPG_MOD 930>;
366 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
367 resets = <&cpg 930>;
368 i2c-scl-internal-delay-ns = <6>;
369 #address-cells = <1>;
370 #size-cells = <0>;
371 status = "disabled";
372 };
373
374 i2c2: i2c@e6530000 {
375 compatible = "renesas,i2c-r8a7792",
376 "renesas,rcar-gen2-i2c";
377 reg = <0 0xe6530000 0 0x40>;
378 interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
379 clocks = <&cpg CPG_MOD 929>;
380 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
381 resets = <&cpg 929>;
382 i2c-scl-internal-delay-ns = <6>;
383 #address-cells = <1>;
384 #size-cells = <0>;
385 status = "disabled";
386 };
387
388 i2c3: i2c@e6540000 {
389 compatible = "renesas,i2c-r8a7792",
390 "renesas,rcar-gen2-i2c";
391 reg = <0 0xe6540000 0 0x40>;
392 interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
393 clocks = <&cpg CPG_MOD 928>;
394 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
395 resets = <&cpg 928>;
396 i2c-scl-internal-delay-ns = <6>;
397 #address-cells = <1>;
398 #size-cells = <0>;
399 status = "disabled";
400 };
401
402 i2c4: i2c@e6520000 {
403 compatible = "renesas,i2c-r8a7792",
404 "renesas,rcar-gen2-i2c";
405 reg = <0 0xe6520000 0 0x40>;
406 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
407 clocks = <&cpg CPG_MOD 927>;
408 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
409 resets = <&cpg 927>;
410 i2c-scl-internal-delay-ns = <6>;
411 #address-cells = <1>;
412 #size-cells = <0>;
413 status = "disabled";
414 };
415
416 i2c5: i2c@e6528000 {
417 compatible = "renesas,i2c-r8a7792",
418 "renesas,rcar-gen2-i2c";
419 reg = <0 0xe6528000 0 0x40>;
420 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
421 clocks = <&cpg CPG_MOD 925>;
422 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
423 resets = <&cpg 925>;
424 i2c-scl-internal-delay-ns = <110>;
425 #address-cells = <1>;
426 #size-cells = <0>;
427 status = "disabled";
428 };
429
Marek Vasuta3fb9ff2018-01-07 20:17:53 +0100[diff] [blame]430 dmac0: dma-controller@e6700000 {
431 compatible = "renesas,dmac-r8a7792",
432 "renesas,rcar-dmac";
433 reg = <0 0xe6700000 0 0x20000>;
434 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH
435 GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH
436 GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH
437 GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH
438 GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH
439 GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH
440 GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH
441 GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH
442 GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH
443 GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH
444 GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH
445 GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH
446 GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH
447 GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH
448 GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH
449 GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
450 interrupt-names = "error",
451 "ch0", "ch1", "ch2", "ch3",
452 "ch4", "ch5", "ch6", "ch7",
453 "ch8", "ch9", "ch10", "ch11",
454 "ch12", "ch13", "ch14";
455 clocks = <&cpg CPG_MOD 219>;
456 clock-names = "fck";
457 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
458 resets = <&cpg 219>;
459 #dma-cells = <1>;
460 dma-channels = <15>;
461 };
462
463 dmac1: dma-controller@e6720000 {
464 compatible = "renesas,dmac-r8a7792",
465 "renesas,rcar-dmac";
466 reg = <0 0xe6720000 0 0x20000>;
467 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH
468 GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH
469 GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH
470 GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH
471 GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH
472 GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH
473 GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH
474 GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH
475 GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH
476 GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH
477 GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH
478 GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH
479 GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH
480 GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH
481 GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH
482 GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;
483 interrupt-names = "error",
484 "ch0", "ch1", "ch2", "ch3",
485 "ch4", "ch5", "ch6", "ch7",
486 "ch8", "ch9", "ch10", "ch11",
487 "ch12", "ch13", "ch14";
488 clocks = <&cpg CPG_MOD 218>;
489 clock-names = "fck";
490 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
491 resets = <&cpg 218>;
492 #dma-cells = <1>;
493 dma-channels = <15>;
494 };
495
Marek Vasut252c8b42018-06-06 19:58:17 +0200[diff] [blame^]496 avb: ethernet@e6800000 {
497 compatible = "renesas,etheravb-r8a7792",
498 "renesas,etheravb-rcar-gen2";
499 reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>;
500 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
501 clocks = <&cpg CPG_MOD 812>;
502 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
503 resets = <&cpg 812>;
504 #address-cells = <1>;
505 #size-cells = <0>;
506 status = "disabled";
507 };
508
509 qspi: spi@e6b10000 {
510 compatible = "renesas,qspi-r8a7792", "renesas,qspi";
511 reg = <0 0xe6b10000 0 0x2c>;
512 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
513 clocks = <&cpg CPG_MOD 917>;
514 dmas = <&dmac0 0x17>, <&dmac0 0x18>,
515 <&dmac1 0x17>, <&dmac1 0x18>;
516 dma-names = "tx", "rx", "tx", "rx";
517 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
518 resets = <&cpg 917>;
519 num-cs = <1>;
520 #address-cells = <1>;
521 #size-cells = <0>;
522 status = "disabled";
523 };
524
Marek Vasuta3fb9ff2018-01-07 20:17:53 +0100[diff] [blame]525 scif0: serial@e6e60000 {
526 compatible = "renesas,scif-r8a7792",
527 "renesas,rcar-gen2-scif", "renesas,scif";
528 reg = <0 0xe6e60000 0 64>;
529 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
530 clocks = <&cpg CPG_MOD 721>,
531 <&cpg CPG_CORE R8A7792_CLK_ZS>, <&scif_clk>;
532 clock-names = "fck", "brg_int", "scif_clk";
533 dmas = <&dmac0 0x29>, <&dmac0 0x2a>,
534 <&dmac1 0x29>, <&dmac1 0x2a>;
535 dma-names = "tx", "rx", "tx", "rx";
536 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
537 resets = <&cpg 721>;
538 status = "disabled";
539 };
540
541 scif1: serial@e6e68000 {
542 compatible = "renesas,scif-r8a7792",
543 "renesas,rcar-gen2-scif", "renesas,scif";
544 reg = <0 0xe6e68000 0 64>;
545 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
546 clocks = <&cpg CPG_MOD 720>,
547 <&cpg CPG_CORE R8A7792_CLK_ZS>, <&scif_clk>;
548 clock-names = "fck", "brg_int", "scif_clk";
549 dmas = <&dmac0 0x2d>, <&dmac0 0x2e>,
550 <&dmac1 0x2d>, <&dmac1 0x2e>;
551 dma-names = "tx", "rx", "tx", "rx";
552 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
553 resets = <&cpg 720>;
554 status = "disabled";
555 };
556
557 scif2: serial@e6e58000 {
558 compatible = "renesas,scif-r8a7792",
559 "renesas,rcar-gen2-scif", "renesas,scif";
560 reg = <0 0xe6e58000 0 64>;
561 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
562 clocks = <&cpg CPG_MOD 719>,
563 <&cpg CPG_CORE R8A7792_CLK_ZS>, <&scif_clk>;
564 clock-names = "fck", "brg_int", "scif_clk";
565 dmas = <&dmac0 0x2b>, <&dmac0 0x2c>,
566 <&dmac1 0x2b>, <&dmac1 0x2c>;
567 dma-names = "tx", "rx", "tx", "rx";
568 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
569 resets = <&cpg 719>;
570 status = "disabled";
571 };
572
573 scif3: serial@e6ea8000 {
574 compatible = "renesas,scif-r8a7792",
575 "renesas,rcar-gen2-scif", "renesas,scif";
576 reg = <0 0xe6ea8000 0 64>;
577 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
578 clocks = <&cpg CPG_MOD 718>,
579 <&cpg CPG_CORE R8A7792_CLK_ZS>, <&scif_clk>;
580 clock-names = "fck", "brg_int", "scif_clk";
581 dmas = <&dmac0 0x2f>, <&dmac0 0x30>,
582 <&dmac1 0x2f>, <&dmac1 0x30>;
583 dma-names = "tx", "rx", "tx", "rx";
584 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
585 resets = <&cpg 718>;
586 status = "disabled";
587 };
588
589 hscif0: serial@e62c0000 {
590 compatible = "renesas,hscif-r8a7792",
591 "renesas,rcar-gen2-hscif", "renesas,hscif";
592 reg = <0 0xe62c0000 0 96>;
593 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
594 clocks = <&cpg CPG_MOD 717>,
595 <&cpg CPG_CORE R8A7792_CLK_ZS>, <&scif_clk>;
596 clock-names = "fck", "brg_int", "scif_clk";
597 dmas = <&dmac0 0x39>, <&dmac0 0x3a>,
598 <&dmac1 0x39>, <&dmac1 0x3a>;
599 dma-names = "tx", "rx", "tx", "rx";
600 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
601 resets = <&cpg 717>;
602 status = "disabled";
603 };
604
605 hscif1: serial@e62c8000 {
606 compatible = "renesas,hscif-r8a7792",
607 "renesas,rcar-gen2-hscif", "renesas,hscif";
608 reg = <0 0xe62c8000 0 96>;
609 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
610 clocks = <&cpg CPG_MOD 716>,
611 <&cpg CPG_CORE R8A7792_CLK_ZS>, <&scif_clk>;
612 clock-names = "fck", "brg_int", "scif_clk";
613 dmas = <&dmac0 0x4d>, <&dmac0 0x4e>,
614 <&dmac1 0x4d>, <&dmac1 0x4e>;
615 dma-names = "tx", "rx", "tx", "rx";
616 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
617 resets = <&cpg 716>;
618 status = "disabled";
619 };
620
Marek Vasuta3fb9ff2018-01-07 20:17:53 +0100[diff] [blame]621 msiof0: spi@e6e20000 {
622 compatible = "renesas,msiof-r8a7792",
623 "renesas,rcar-gen2-msiof";
624 reg = <0 0xe6e20000 0 0x0064>;
625 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
626 clocks = <&cpg CPG_MOD 000>;
627 dmas = <&dmac0 0x51>, <&dmac0 0x52>,
628 <&dmac1 0x51>, <&dmac1 0x52>;
629 dma-names = "tx", "rx", "tx", "rx";
630 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
631 resets = <&cpg 000>;
632 #address-cells = <1>;
633 #size-cells = <0>;
634 status = "disabled";
635 };
636
637 msiof1: spi@e6e10000 {
638 compatible = "renesas,msiof-r8a7792",
639 "renesas,rcar-gen2-msiof";
640 reg = <0 0xe6e10000 0 0x0064>;
641 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
642 clocks = <&cpg CPG_MOD 208>;
643 dmas = <&dmac0 0x55>, <&dmac0 0x56>,
644 <&dmac1 0x55>, <&dmac1 0x56>;
645 dma-names = "tx", "rx", "tx", "rx";
646 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
647 resets = <&cpg 208>;
648 #address-cells = <1>;
649 #size-cells = <0>;
650 status = "disabled";
651 };
652
Marek Vasuta3fb9ff2018-01-07 20:17:53 +0100[diff] [blame]653 can0: can@e6e80000 {
654 compatible = "renesas,can-r8a7792",
655 "renesas,rcar-gen2-can";
656 reg = <0 0xe6e80000 0 0x1000>;
657 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
658 clocks = <&cpg CPG_MOD 916>,
659 <&cpg CPG_CORE R8A7792_CLK_RCAN>, <&can_clk>;
660 clock-names = "clkp1", "clkp2", "can_clk";
661 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
662 resets = <&cpg 916>;
663 status = "disabled";
664 };
665
666 can1: can@e6e88000 {
667 compatible = "renesas,can-r8a7792",
668 "renesas,rcar-gen2-can";
669 reg = <0 0xe6e88000 0 0x1000>;
670 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
671 clocks = <&cpg CPG_MOD 915>,
672 <&cpg CPG_CORE R8A7792_CLK_RCAN>, <&can_clk>;
673 clock-names = "clkp1", "clkp2", "can_clk";
674 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
675 resets = <&cpg 915>;
676 status = "disabled";
677 };
678
679 vin0: video@e6ef0000 {
680 compatible = "renesas,vin-r8a7792",
681 "renesas,rcar-gen2-vin";
682 reg = <0 0xe6ef0000 0 0x1000>;
683 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
684 clocks = <&cpg CPG_MOD 811>;
685 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
686 resets = <&cpg 811>;
687 status = "disabled";
688 };
689
690 vin1: video@e6ef1000 {
691 compatible = "renesas,vin-r8a7792",
692 "renesas,rcar-gen2-vin";
693 reg = <0 0xe6ef1000 0 0x1000>;
694 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
695 clocks = <&cpg CPG_MOD 810>;
696 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
697 resets = <&cpg 810>;
698 status = "disabled";
699 };
700
701 vin2: video@e6ef2000 {
702 compatible = "renesas,vin-r8a7792",
703 "renesas,rcar-gen2-vin";
704 reg = <0 0xe6ef2000 0 0x1000>;
705 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
706 clocks = <&cpg CPG_MOD 809>;
707 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
708 resets = <&cpg 809>;
709 status = "disabled";
710 };
711
712 vin3: video@e6ef3000 {
713 compatible = "renesas,vin-r8a7792",
714 "renesas,rcar-gen2-vin";
715 reg = <0 0xe6ef3000 0 0x1000>;
716 interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
717 clocks = <&cpg CPG_MOD 808>;
718 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
719 resets = <&cpg 808>;
720 status = "disabled";
721 };
722
723 vin4: video@e6ef4000 {
724 compatible = "renesas,vin-r8a7792",
725 "renesas,rcar-gen2-vin";
726 reg = <0 0xe6ef4000 0 0x1000>;
727 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
728 clocks = <&cpg CPG_MOD 805>;
729 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
730 resets = <&cpg 805>;
731 status = "disabled";
732 };
733
734 vin5: video@e6ef5000 {
735 compatible = "renesas,vin-r8a7792",
736 "renesas,rcar-gen2-vin";
737 reg = <0 0xe6ef5000 0 0x1000>;
738 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
739 clocks = <&cpg CPG_MOD 804>;
740 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
741 resets = <&cpg 804>;
742 status = "disabled";
743 };
744
Marek Vasut252c8b42018-06-06 19:58:17 +0200[diff] [blame^]745 sdhi0: sd@ee100000 {
746 compatible = "renesas,sdhi-r8a7792",
747 "renesas,rcar-gen2-sdhi";
748 reg = <0 0xee100000 0 0x328>;
749 interrupts = <0 165 IRQ_TYPE_LEVEL_HIGH>;
750 dmas = <&dmac0 0xcd>, <&dmac0 0xce>,
751 <&dmac1 0xcd>, <&dmac1 0xce>;
752 dma-names = "tx", "rx", "tx", "rx";
753 clocks = <&cpg CPG_MOD 314>;
754 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
755 resets = <&cpg 314>;
756 status = "disabled";
757 };
758
759 gic: interrupt-controller@f1001000 {
760 compatible = "arm,gic-400";
761 #interrupt-cells = <3>;
762 interrupt-controller;
763 reg = <0 0xf1001000 0 0x1000>,
764 <0 0xf1002000 0 0x2000>,
765 <0 0xf1004000 0 0x2000>,
766 <0 0xf1006000 0 0x2000>;
767 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) |
768 IRQ_TYPE_LEVEL_HIGH)>;
769 clocks = <&cpg CPG_MOD 408>;
770 clock-names = "clk";
771 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
772 resets = <&cpg 408>;
773 };
774
Marek Vasuta3fb9ff2018-01-07 20:17:53 +0100[diff] [blame]775 vsp@fe928000 {
776 compatible = "renesas,vsp1";
777 reg = <0 0xfe928000 0 0x8000>;
778 interrupts = <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>;
779 clocks = <&cpg CPG_MOD 131>;
780 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
781 resets = <&cpg 131>;
782 };
783
784 vsp@fe930000 {
785 compatible = "renesas,vsp1";
786 reg = <0 0xfe930000 0 0x8000>;
787 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
788 clocks = <&cpg CPG_MOD 128>;
789 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
790 resets = <&cpg 128>;
791 };
792
793 vsp@fe938000 {
794 compatible = "renesas,vsp1";
795 reg = <0 0xfe938000 0 0x8000>;
796 interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>;
797 clocks = <&cpg CPG_MOD 127>;
798 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
799 resets = <&cpg 127>;
800 };
801
Marek Vasut252c8b42018-06-06 19:58:17 +0200[diff] [blame^]802 jpu: jpeg-codec@fe980000 {
803 compatible = "renesas,jpu-r8a7792",
804 "renesas,rcar-gen2-jpu";
805 reg = <0 0xfe980000 0 0x10300>;
806 interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
807 clocks = <&cpg CPG_MOD 106>;
808 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
809 resets = <&cpg 106>;
810 };
811
812 du: display@feb00000 {
813 compatible = "renesas,du-r8a7792";
814 reg = <0 0xfeb00000 0 0x40000>;
815 reg-names = "du";
816 interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
817 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
818 clocks = <&cpg CPG_MOD 724>,
819 <&cpg CPG_MOD 723>;
820 clock-names = "du.0", "du.1";
821 status = "disabled";
822
823 ports {
824 #address-cells = <1>;
825 #size-cells = <0>;
826
827 port@0 {
828 reg = <0>;
829 du_out_rgb0: endpoint {
830 };
831 };
832 port@1 {
833 reg = <1>;
834 du_out_rgb1: endpoint {
835 };
836 };
837 };
838 };
839
840 prr: chipid@ff000044 {
841 compatible = "renesas,prr";
842 reg = <0 0xff000044 0 4>;
Marek Vasuta3fb9ff2018-01-07 20:17:53 +0100[diff] [blame]843 };
844 };
845
Marek Vasut252c8b42018-06-06 19:58:17 +0200[diff] [blame^]846 timer {
847 compatible = "arm,armv7-timer";
848 interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
849 <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
850 <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
851 <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
Marek Vasuta3fb9ff2018-01-07 20:17:53 +0100[diff] [blame]852 };
853};