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Shengzhou Liuc4d0e812013-11-22 17:39:11 +08001/*
2 * Copyright 2013 Freescale Semiconductor, Inc.
3 *
4 * Shengzhou Liu <Shengzhou.Liu@freescale.com>
5 *
6 * SPDX-License-Identifier: GPL-2.0+
7 */
8
9#include <common.h>
10#include <command.h>
11#include <netdev.h>
12#include <asm/mmu.h>
13#include <asm/processor.h>
14#include <asm/immap_85xx.h>
15#include <asm/fsl_law.h>
16#include <asm/fsl_serdes.h>
17#include <asm/fsl_portals.h>
18#include <asm/fsl_liodn.h>
19#include <malloc.h>
20#include <fm_eth.h>
21#include <fsl_mdio.h>
22#include <miiphy.h>
23#include <phy.h>
24#include <asm/fsl_dtsec.h>
25#include <asm/fsl_serdes.h>
26#include "../common/qixis.h"
27#include "../common/fman.h"
Shengzhou Liu254887a2014-02-21 13:16:19 +080028#include "t208xqds_qixis.h"
Shengzhou Liuc4d0e812013-11-22 17:39:11 +080029
30#define EMI_NONE 0xFFFFFFFF
31#define EMI1_RGMII1 0
32#define EMI1_RGMII2 1
33#define EMI1_SLOT1 2
Shengzhou Liu254887a2014-02-21 13:16:19 +080034#if defined(CONFIG_T2080QDS)
Shengzhou Liuc4d0e812013-11-22 17:39:11 +080035#define EMI1_SLOT2 6
36#define EMI1_SLOT3 3
37#define EMI1_SLOT4 4
38#define EMI1_SLOT5 5
Shengzhou Liu254887a2014-02-21 13:16:19 +080039#elif defined(CONFIG_T2081QDS)
40#define EMI1_SLOT2 3
41#define EMI1_SLOT3 4
42#define EMI1_SLOT5 5
43#define EMI1_SLOT6 6
44#define EMI1_SLOT7 7
45#endif
46#define EMI2 8
Shengzhou Liuc4d0e812013-11-22 17:39:11 +080047
48static int mdio_mux[NUM_FM_PORTS];
49
50static const char * const mdio_names[] = {
Shengzhou Liu254887a2014-02-21 13:16:19 +080051#if defined(CONFIG_T2080QDS)
Shengzhou Liuc4d0e812013-11-22 17:39:11 +080052 "T2080QDS_MDIO_RGMII1",
53 "T2080QDS_MDIO_RGMII2",
54 "T2080QDS_MDIO_SLOT1",
55 "T2080QDS_MDIO_SLOT3",
56 "T2080QDS_MDIO_SLOT4",
57 "T2080QDS_MDIO_SLOT5",
58 "T2080QDS_MDIO_SLOT2",
59 "T2080QDS_MDIO_10GC",
Shengzhou Liu254887a2014-02-21 13:16:19 +080060#elif defined(CONFIG_T2081QDS)
61 "T2081QDS_MDIO_RGMII1",
62 "T2081QDS_MDIO_RGMII2",
63 "T2081QDS_MDIO_SLOT1",
64 "T2081QDS_MDIO_SLOT2",
65 "T2081QDS_MDIO_SLOT3",
66 "T2081QDS_MDIO_SLOT5",
67 "T2081QDS_MDIO_SLOT6",
68 "T2081QDS_MDIO_SLOT7",
69 "T2081QDS_MDIO_10GC",
70#endif
Shengzhou Liuc4d0e812013-11-22 17:39:11 +080071};
72
73/* Map SerDes1 8 lanes to default slot, will be initialized dynamically */
Shengzhou Liu254887a2014-02-21 13:16:19 +080074#if defined(CONFIG_T2080QDS)
Shengzhou Liuc4d0e812013-11-22 17:39:11 +080075static u8 lane_to_slot[] = {3, 3, 3, 3, 1, 1, 1, 1};
Shengzhou Liu254887a2014-02-21 13:16:19 +080076#elif defined(CONFIG_T2081QDS)
77static u8 lane_to_slot[] = {2, 2, 2, 2, 1, 1, 1, 1};
78#endif
Shengzhou Liuc4d0e812013-11-22 17:39:11 +080079
Shengzhou Liu254887a2014-02-21 13:16:19 +080080static const char *t208xqds_mdio_name_for_muxval(u8 muxval)
Shengzhou Liuc4d0e812013-11-22 17:39:11 +080081{
82 return mdio_names[muxval];
83}
84
85struct mii_dev *mii_dev_for_muxval(u8 muxval)
86{
87 struct mii_dev *bus;
Shengzhou Liu254887a2014-02-21 13:16:19 +080088 const char *name = t208xqds_mdio_name_for_muxval(muxval);
Shengzhou Liuc4d0e812013-11-22 17:39:11 +080089
90 if (!name) {
91 printf("No bus for muxval %x\n", muxval);
92 return NULL;
93 }
94
95 bus = miiphy_get_dev_by_name(name);
96
97 if (!bus) {
98 printf("No bus by name %s\n", name);
99 return NULL;
100 }
101
102 return bus;
103}
104
Shengzhou Liu254887a2014-02-21 13:16:19 +0800105struct t208xqds_mdio {
Shengzhou Liuc4d0e812013-11-22 17:39:11 +0800106 u8 muxval;
107 struct mii_dev *realbus;
108};
109
Shengzhou Liu254887a2014-02-21 13:16:19 +0800110static void t208xqds_mux_mdio(u8 muxval)
Shengzhou Liuc4d0e812013-11-22 17:39:11 +0800111{
112 u8 brdcfg4;
Shengzhou Liu254887a2014-02-21 13:16:19 +0800113 if (muxval < 8) {
Shengzhou Liuc4d0e812013-11-22 17:39:11 +0800114 brdcfg4 = QIXIS_READ(brdcfg[4]);
115 brdcfg4 &= ~BRDCFG4_EMISEL_MASK;
116 brdcfg4 |= (muxval << BRDCFG4_EMISEL_SHIFT);
117 QIXIS_WRITE(brdcfg[4], brdcfg4);
118 }
119}
120
Shengzhou Liu254887a2014-02-21 13:16:19 +0800121static int t208xqds_mdio_read(struct mii_dev *bus, int addr, int devad,
Shengzhou Liuc4d0e812013-11-22 17:39:11 +0800122 int regnum)
123{
Shengzhou Liu254887a2014-02-21 13:16:19 +0800124 struct t208xqds_mdio *priv = bus->priv;
Shengzhou Liuc4d0e812013-11-22 17:39:11 +0800125
Shengzhou Liu254887a2014-02-21 13:16:19 +0800126 t208xqds_mux_mdio(priv->muxval);
Shengzhou Liuc4d0e812013-11-22 17:39:11 +0800127
128 return priv->realbus->read(priv->realbus, addr, devad, regnum);
129}
130
Shengzhou Liu254887a2014-02-21 13:16:19 +0800131static int t208xqds_mdio_write(struct mii_dev *bus, int addr, int devad,
Shengzhou Liuc4d0e812013-11-22 17:39:11 +0800132 int regnum, u16 value)
133{
Shengzhou Liu254887a2014-02-21 13:16:19 +0800134 struct t208xqds_mdio *priv = bus->priv;
Shengzhou Liuc4d0e812013-11-22 17:39:11 +0800135
Shengzhou Liu254887a2014-02-21 13:16:19 +0800136 t208xqds_mux_mdio(priv->muxval);
Shengzhou Liuc4d0e812013-11-22 17:39:11 +0800137
138 return priv->realbus->write(priv->realbus, addr, devad, regnum, value);
139}
140
Shengzhou Liu254887a2014-02-21 13:16:19 +0800141static int t208xqds_mdio_reset(struct mii_dev *bus)
Shengzhou Liuc4d0e812013-11-22 17:39:11 +0800142{
Shengzhou Liu254887a2014-02-21 13:16:19 +0800143 struct t208xqds_mdio *priv = bus->priv;
Shengzhou Liuc4d0e812013-11-22 17:39:11 +0800144
145 return priv->realbus->reset(priv->realbus);
146}
147
Shengzhou Liu254887a2014-02-21 13:16:19 +0800148static int t208xqds_mdio_init(char *realbusname, u8 muxval)
Shengzhou Liuc4d0e812013-11-22 17:39:11 +0800149{
Shengzhou Liu254887a2014-02-21 13:16:19 +0800150 struct t208xqds_mdio *pmdio;
Shengzhou Liuc4d0e812013-11-22 17:39:11 +0800151 struct mii_dev *bus = mdio_alloc();
152
153 if (!bus) {
Shengzhou Liu254887a2014-02-21 13:16:19 +0800154 printf("Failed to allocate t208xqds MDIO bus\n");
Shengzhou Liuc4d0e812013-11-22 17:39:11 +0800155 return -1;
156 }
157
158 pmdio = malloc(sizeof(*pmdio));
159 if (!pmdio) {
Shengzhou Liu254887a2014-02-21 13:16:19 +0800160 printf("Failed to allocate t208xqds private data\n");
Shengzhou Liuc4d0e812013-11-22 17:39:11 +0800161 free(bus);
162 return -1;
163 }
164
Shengzhou Liu254887a2014-02-21 13:16:19 +0800165 bus->read = t208xqds_mdio_read;
166 bus->write = t208xqds_mdio_write;
167 bus->reset = t208xqds_mdio_reset;
168 sprintf(bus->name, t208xqds_mdio_name_for_muxval(muxval));
Shengzhou Liuc4d0e812013-11-22 17:39:11 +0800169
170 pmdio->realbus = miiphy_get_dev_by_name(realbusname);
171
172 if (!pmdio->realbus) {
173 printf("No bus with name %s\n", realbusname);
174 free(bus);
175 free(pmdio);
176 return -1;
177 }
178
179 pmdio->muxval = muxval;
180 bus->priv = pmdio;
Shengzhou Liuc4d0e812013-11-22 17:39:11 +0800181 return mdio_register(bus);
182}
183
184void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr,
185 enum fm_port port, int offset)
186{
187 int phy;
188 char alias[20];
189 struct fixed_link f_link;
190 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
191 u32 srds_s1 = in_be32(&gur->rcwsr[4]) &
192 FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
193
194 srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
195
196 if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII) {
197 phy = fm_info_get_phy_address(port);
198 switch (port) {
Shengzhou Liu254887a2014-02-21 13:16:19 +0800199#if defined(CONFIG_T2080QDS)
Shengzhou Liuc4d0e812013-11-22 17:39:11 +0800200 case FM1_DTSEC1:
201 case FM1_DTSEC2:
202 case FM1_DTSEC9:
203 case FM1_DTSEC10:
Shengzhou Liu254887a2014-02-21 13:16:19 +0800204 if (mdio_mux[port] == EMI1_SLOT2) {
205 sprintf(alias, "phy_sgmii_s2_%x", phy);
206 fdt_set_phy_handle(fdt, compat, addr, alias);
207 fdt_status_okay_by_alias(fdt, "emi1_slot2");
208 } else if (mdio_mux[port] == EMI1_SLOT3) {
209 sprintf(alias, "phy_sgmii_s3_%x", phy);
210 fdt_set_phy_handle(fdt, compat, addr, alias);
211 fdt_status_okay_by_alias(fdt, "emi1_slot3");
212 }
Shengzhou Liuc4d0e812013-11-22 17:39:11 +0800213 break;
214 case FM1_DTSEC5:
215 case FM1_DTSEC6:
216 if (mdio_mux[port] == EMI1_SLOT1) {
217 sprintf(alias, "phy_sgmii_s1_%x", phy);
218 fdt_set_phy_handle(fdt, compat, addr, alias);
219 fdt_status_okay_by_alias(fdt, "emi1_slot1");
220 } else if (mdio_mux[port] == EMI1_SLOT2) {
221 sprintf(alias, "phy_sgmii_s2_%x", phy);
222 fdt_set_phy_handle(fdt, compat, addr, alias);
223 fdt_status_okay_by_alias(fdt, "emi1_slot2");
224 }
225 break;
Shengzhou Liu254887a2014-02-21 13:16:19 +0800226#elif defined(CONFIG_T2081QDS)
227 case FM1_DTSEC1:
228 case FM1_DTSEC2:
229 case FM1_DTSEC5:
230 case FM1_DTSEC6:
231 case FM1_DTSEC9:
232 case FM1_DTSEC10:
233 if (mdio_mux[port] == EMI1_SLOT2) {
234 sprintf(alias, "phy_sgmii_s2_%x", phy);
235 fdt_set_phy_handle(fdt, compat, addr, alias);
236 fdt_status_okay_by_alias(fdt, "emi1_slot2");
237 } else if (mdio_mux[port] == EMI1_SLOT3) {
238 sprintf(alias, "phy_sgmii_s3_%x", phy);
239 fdt_set_phy_handle(fdt, compat, addr, alias);
240 fdt_status_okay_by_alias(fdt, "emi1_slot3");
241 } else if (mdio_mux[port] == EMI1_SLOT5) {
242 sprintf(alias, "phy_sgmii_s5_%x", phy);
243 fdt_set_phy_handle(fdt, compat, addr, alias);
244 fdt_status_okay_by_alias(fdt, "emi1_slot5");
245 } else if (mdio_mux[port] == EMI1_SLOT6) {
246 sprintf(alias, "phy_sgmii_s6_%x", phy);
247 fdt_set_phy_handle(fdt, compat, addr, alias);
248 fdt_status_okay_by_alias(fdt, "emi1_slot6");
249 } else if (mdio_mux[port] == EMI1_SLOT7) {
250 sprintf(alias, "phy_sgmii_s7_%x", phy);
251 fdt_set_phy_handle(fdt, compat, addr, alias);
252 fdt_status_okay_by_alias(fdt, "emi1_slot7");
253 }
254 break;
255#endif
Shengzhou Liuc4d0e812013-11-22 17:39:11 +0800256 default:
257 break;
258 }
259
260 } else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_XGMII) {
261 switch (srds_s1) {
262 case 0x66: /* XFI interface */
263 case 0x6b:
264 case 0x6c:
265 case 0x6d:
266 case 0x71:
267 f_link.phy_id = port;
268 f_link.duplex = 1;
269 f_link.link_speed = 10000;
270 f_link.pause = 0;
271 f_link.asym_pause = 0;
272 /* no PHY for XFI */
273 fdt_delprop(fdt, offset, "phy-handle");
274 fdt_setprop(fdt, offset, "fixed-link", &f_link,
275 sizeof(f_link));
276 break;
277 default:
278 break;
279 }
280 }
281}
282
283void fdt_fixup_board_enet(void *fdt)
284{
285 return;
286}
287
288/*
Shengzhou Liu254887a2014-02-21 13:16:19 +0800289 * This function reads RCW to check if Serdes1{A:H} is configured
290 * to slot 1/2/3/4/5/6/7 and update the lane_to_slot[] array accordingly
Shengzhou Liuc4d0e812013-11-22 17:39:11 +0800291 */
292static void initialize_lane_to_slot(void)
293{
294 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
295 u32 srds_s1 = in_be32(&gur->rcwsr[4]) &
296 FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
297
298 srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
299
300 switch (srds_s1) {
Shengzhou Liu254887a2014-02-21 13:16:19 +0800301#if defined(CONFIG_T2080QDS)
Shengzhou Liuc4d0e812013-11-22 17:39:11 +0800302 case 0x51:
303 case 0x5f:
304 case 0x65:
305 case 0x6b:
306 case 0x71:
307 lane_to_slot[5] = 2;
308 lane_to_slot[6] = 2;
309 lane_to_slot[7] = 2;
310 break;
311 case 0xa6:
312 case 0x8e:
313 case 0x8f:
314 case 0x82:
315 case 0x83:
316 case 0xd3:
317 case 0xd9:
318 case 0xcb:
319 lane_to_slot[6] = 2;
320 lane_to_slot[7] = 2;
321 break;
322 case 0xda:
323 lane_to_slot[4] = 3;
324 lane_to_slot[5] = 3;
325 lane_to_slot[6] = 3;
326 lane_to_slot[7] = 3;
327 break;
Shengzhou Liu254887a2014-02-21 13:16:19 +0800328#elif defined(CONFIG_T2081QDS)
329 case 0x6b:
330 lane_to_slot[4] = 1;
331 lane_to_slot[5] = 3;
332 lane_to_slot[6] = 3;
333 lane_to_slot[7] = 3;
334 break;
335 case 0xca:
336 case 0xcb:
337 lane_to_slot[1] = 7;
338 lane_to_slot[2] = 6;
339 lane_to_slot[3] = 5;
340 lane_to_slot[5] = 3;
341 lane_to_slot[6] = 3;
342 lane_to_slot[7] = 3;
343 break;
344 case 0xf2:
345 lane_to_slot[1] = 7;
346 lane_to_slot[2] = 7;
347 lane_to_slot[3] = 7;
348 lane_to_slot[5] = 4;
349 lane_to_slot[6] = 3;
350 lane_to_slot[7] = 7;
351 break;
352#endif
Shengzhou Liuc4d0e812013-11-22 17:39:11 +0800353 default:
354 break;
355 }
356}
357
358int board_eth_init(bd_t *bis)
359{
360#if defined(CONFIG_FMAN_ENET)
361 int i, idx, lane, slot, interface;
362 struct memac_mdio_info dtsec_mdio_info;
363 struct memac_mdio_info tgec_mdio_info;
364 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
365 u32 rcwsr13 = in_be32(&gur->rcwsr[13]);
366 u32 srds_s1;
367
368 srds_s1 = in_be32(&gur->rcwsr[4]) &
369 FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
370 srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
371
372 initialize_lane_to_slot();
373
374 /* Initialize the mdio_mux array so we can recognize empty elements */
375 for (i = 0; i < NUM_FM_PORTS; i++)
376 mdio_mux[i] = EMI_NONE;
377
378 dtsec_mdio_info.regs =
379 (struct memac_mdio_controller *)CONFIG_SYS_FM1_DTSEC_MDIO_ADDR;
380
381 dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
382
383 /* Register the 1G MDIO bus */
384 fm_memac_mdio_init(bis, &dtsec_mdio_info);
385
386 tgec_mdio_info.regs =
387 (struct memac_mdio_controller *)CONFIG_SYS_FM1_TGEC_MDIO_ADDR;
388 tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME;
389
390 /* Register the 10G MDIO bus */
391 fm_memac_mdio_init(bis, &tgec_mdio_info);
392
393 /* Register the muxing front-ends to the MDIO buses */
Shengzhou Liu254887a2014-02-21 13:16:19 +0800394 t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII1);
395 t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII2);
396 t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT1);
397 t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT2);
398 t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT3);
399#if defined(CONFIG_T2080QDS)
400 t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT4);
401#endif
402 t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT5);
403#if defined(CONFIG_T2081QDS)
404 t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT6);
405 t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT7);
406#endif
407 t208xqds_mdio_init(DEFAULT_FM_TGEC_MDIO_NAME, EMI2);
Shengzhou Liuc4d0e812013-11-22 17:39:11 +0800408
409 /* Set the two on-board RGMII PHY address */
410 fm_info_set_phy_address(FM1_DTSEC3, RGMII_PHY1_ADDR);
411 if ((rcwsr13 & FSL_CORENET_RCWSR13_EC2) ==
412 FSL_CORENET_RCWSR13_EC2_DTSEC4_RGMII)
413 fm_info_set_phy_address(FM1_DTSEC4, RGMII_PHY2_ADDR);
414 else
415 fm_info_set_phy_address(FM1_DTSEC10, RGMII_PHY2_ADDR);
416
417 switch (srds_s1) {
418 case 0x1c:
419 case 0x95:
420 case 0xa2:
421 case 0x94:
Shengzhou Liu254887a2014-02-21 13:16:19 +0800422 /* T2080QDS: SGMII in Slot3; T2081QDS: SGMII in Slot2 */
Shengzhou Liuc4d0e812013-11-22 17:39:11 +0800423 fm_info_set_phy_address(FM1_DTSEC9, SGMII_CARD_PORT1_PHY_ADDR);
424 fm_info_set_phy_address(FM1_DTSEC10, SGMII_CARD_PORT2_PHY_ADDR);
425 fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR);
426 fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR);
Shengzhou Liu254887a2014-02-21 13:16:19 +0800427 /* T2080QDS: SGMII in Slot2; T2081QDS: SGMII in Slot1 */
Shengzhou Liuc4d0e812013-11-22 17:39:11 +0800428 fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR);
429 fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT4_PHY_ADDR);
430 break;
431 case 0x51:
432 case 0x5f:
433 case 0x65:
Shengzhou Liu254887a2014-02-21 13:16:19 +0800434 /* T2080QDS: XAUI/HiGig in Slot3; T2081QDS: in Slot2 */
Shengzhou Liuc4d0e812013-11-22 17:39:11 +0800435 fm_info_set_phy_address(FM1_10GEC1, FM1_10GEC1_PHY_ADDR);
Shengzhou Liu254887a2014-02-21 13:16:19 +0800436 /* T2080QDS: SGMII in Slot2; T2081QDS: in Slot3 */
Shengzhou Liuc4d0e812013-11-22 17:39:11 +0800437 fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR);
438 fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT4_PHY_ADDR);
439 break;
440 case 0x66:
441 /*
442 * XFI does not need a PHY to work, but to avoid U-boot use
443 * default PHY address which is zero to a MAC when it found
444 * a MAC has no PHY address, we give a PHY address to XFI
445 * MAC, and should not use a real XAUI PHY address, since
446 * MDIO can access it successfully, and then MDIO thinks
447 * the XAUI card is used for the XFI MAC, which will cause
448 * error.
449 */
450 fm_info_set_phy_address(FM1_10GEC1, 4);
451 fm_info_set_phy_address(FM1_10GEC2, 5);
452 fm_info_set_phy_address(FM1_10GEC3, 6);
453 fm_info_set_phy_address(FM1_10GEC4, 7);
454 break;
455 case 0x6b:
456 fm_info_set_phy_address(FM1_10GEC1, 4);
457 fm_info_set_phy_address(FM1_10GEC2, 5);
458 fm_info_set_phy_address(FM1_10GEC3, 6);
459 fm_info_set_phy_address(FM1_10GEC4, 7);
Shengzhou Liu254887a2014-02-21 13:16:19 +0800460 /* T2080QDS: SGMII in Slot2; T2081QDS: in Slot3 */
Shengzhou Liuc4d0e812013-11-22 17:39:11 +0800461 fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR);
462 fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT2_PHY_ADDR);
463 break;
464 case 0x6c:
465 case 0x6d:
Shengzhou Liu1576b552014-01-03 14:48:44 +0800466 fm_info_set_phy_address(FM1_10GEC1, 4);
467 fm_info_set_phy_address(FM1_10GEC2, 5);
Shengzhou Liu254887a2014-02-21 13:16:19 +0800468 /* T2080QDS: SGMII in Slot3; T2081QDS: in Slot2 */
Shengzhou Liuc4d0e812013-11-22 17:39:11 +0800469 fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR);
Shengzhou Liu1576b552014-01-03 14:48:44 +0800470 fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR);
Shengzhou Liuc4d0e812013-11-22 17:39:11 +0800471 break;
472 case 0x71:
473 /* SGMII in Slot3 */
474 fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR);
475 fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR);
476 /* SGMII in Slot2 */
477 fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR);
478 fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT2_PHY_ADDR);
479 break;
480 case 0xa6:
481 case 0x8e:
482 case 0x8f:
483 case 0x82:
484 case 0x83:
485 /* SGMII in Slot3 */
486 fm_info_set_phy_address(FM1_DTSEC9, SGMII_CARD_PORT1_PHY_ADDR);
487 fm_info_set_phy_address(FM1_DTSEC10, SGMII_CARD_PORT2_PHY_ADDR);
488 fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR);
489 fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR);
490 /* SGMII in Slot2 */
491 fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR);
492 fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT2_PHY_ADDR);
493 break;
494 case 0xa4:
495 case 0x96:
496 case 0x8a:
497 /* SGMII in Slot3 */
498 fm_info_set_phy_address(FM1_DTSEC9, SGMII_CARD_PORT1_PHY_ADDR);
499 fm_info_set_phy_address(FM1_DTSEC10, SGMII_CARD_PORT2_PHY_ADDR);
500 fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR);
501 fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR);
502 break;
Shengzhou Liu254887a2014-02-21 13:16:19 +0800503#if defined(CONFIG_T2080QDS)
Shengzhou Liuc4d0e812013-11-22 17:39:11 +0800504 case 0xd9:
505 case 0xd3:
506 case 0xcb:
507 /* SGMII in Slot3 */
508 fm_info_set_phy_address(FM1_DTSEC10, SGMII_CARD_PORT2_PHY_ADDR);
509 fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR);
510 fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR);
511 /* SGMII in Slot2 */
512 fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR);
513 fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT2_PHY_ADDR);
514 break;
Shengzhou Liu254887a2014-02-21 13:16:19 +0800515#elif defined(CONFIG_T2081QDS)
516 case 0xca:
517 case 0xcb:
518 /* SGMII in Slot3 */
519 fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT1_PHY_ADDR);
520 fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT2_PHY_ADDR);
521 /* SGMII in Slot5 */
522 fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT1_PHY_ADDR);
523 /* SGMII in Slot6 */
524 fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT1_PHY_ADDR);
525 /* SGMII in Slot7 */
526 fm_info_set_phy_address(FM1_DTSEC10, SGMII_CARD_PORT3_PHY_ADDR);
527 break;
528#endif
529 case 0xf2:
530 /* T2080QDS: SGMII in Slot3; T2081QDS: SGMII in Slot7 */
531 fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT1_PHY_ADDR);
532 fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT2_PHY_ADDR);
533 fm_info_set_phy_address(FM1_DTSEC10, SGMII_CARD_PORT3_PHY_ADDR);
534 fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT4_PHY_ADDR);
535 break;
Shengzhou Liuc4d0e812013-11-22 17:39:11 +0800536 default:
Shengzhou Liuc4d0e812013-11-22 17:39:11 +0800537 break;
538 }
539
540 for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
541 idx = i - FM1_DTSEC1;
542 interface = fm_info_get_enet_if(i);
543 switch (interface) {
544 case PHY_INTERFACE_MODE_SGMII:
545 lane = serdes_get_first_lane(FSL_SRDS_1,
546 SGMII_FM1_DTSEC1 + idx);
547 if (lane < 0)
548 break;
549 slot = lane_to_slot[lane];
550 debug("FM1@DTSEC%u expects SGMII in slot %u\n",
551 idx + 1, slot);
552 if (QIXIS_READ(present2) & (1 << (slot - 1)))
553 fm_disable_port(i);
554
555 switch (slot) {
556 case 1:
557 mdio_mux[i] = EMI1_SLOT1;
558 fm_info_set_mdio(i, mii_dev_for_muxval(
559 mdio_mux[i]));
560 break;
561 case 2:
562 mdio_mux[i] = EMI1_SLOT2;
563 fm_info_set_mdio(i, mii_dev_for_muxval(
564 mdio_mux[i]));
565 break;
Shengzhou Liu1576b552014-01-03 14:48:44 +0800566 case 3:
567 mdio_mux[i] = EMI1_SLOT3;
568 fm_info_set_mdio(i, mii_dev_for_muxval(
Shengzhou Liu254887a2014-02-21 13:16:19 +0800569 mdio_mux[i]));
Shengzhou Liu1576b552014-01-03 14:48:44 +0800570 break;
Shengzhou Liu254887a2014-02-21 13:16:19 +0800571#if defined(CONFIG_T2081QDS)
572 case 5:
573 mdio_mux[i] = EMI1_SLOT5;
574 fm_info_set_mdio(i, mii_dev_for_muxval(
575 mdio_mux[i]));
576 break;
577 case 6:
578 mdio_mux[i] = EMI1_SLOT6;
579 fm_info_set_mdio(i, mii_dev_for_muxval(
580 mdio_mux[i]));
581 break;
582 case 7:
583 mdio_mux[i] = EMI1_SLOT7;
584 fm_info_set_mdio(i, mii_dev_for_muxval(
585 mdio_mux[i]));
586 break;
587#endif
Shengzhou Liu1576b552014-01-03 14:48:44 +0800588 }
Shengzhou Liuc4d0e812013-11-22 17:39:11 +0800589 break;
590 case PHY_INTERFACE_MODE_RGMII:
591 if (i == FM1_DTSEC3)
592 mdio_mux[i] = EMI1_RGMII1;
593 else if (i == FM1_DTSEC4 || FM1_DTSEC10)
594 mdio_mux[i] = EMI1_RGMII2;
595 fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
596 break;
597 default:
598 break;
599 }
600 }
601
602 for (i = FM1_10GEC1; i < FM1_10GEC1 + CONFIG_SYS_NUM_FM1_10GEC; i++) {
603 idx = i - FM1_10GEC1;
604 switch (fm_info_get_enet_if(i)) {
605 case PHY_INTERFACE_MODE_XGMII:
606 if (srds_s1 == 0x51) {
607 lane = serdes_get_first_lane(FSL_SRDS_1,
608 XAUI_FM1_MAC9 + idx);
609 } else if ((srds_s1 == 0x5f) || (srds_s1 == 0x65)) {
610 lane = serdes_get_first_lane(FSL_SRDS_1,
611 HIGIG_FM1_MAC9 + idx);
612 } else {
613 if (i == FM1_10GEC1 || i == FM1_10GEC2)
614 lane = serdes_get_first_lane(FSL_SRDS_1,
615 XFI_FM1_MAC9 + idx);
616 else
617 lane = serdes_get_first_lane(FSL_SRDS_1,
618 XFI_FM1_MAC1 + idx);
619 }
620
621 if (lane < 0)
622 break;
623 mdio_mux[i] = EMI2;
624 fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
625
626 if ((srds_s1 == 0x66) || (srds_s1 == 0x6b) ||
627 (srds_s1 == 0x6c) || (srds_s1 == 0x6d) ||
628 (srds_s1 == 0x71)) {
629 /* As XFI is in cage intead of a slot, so
630 * ensure doesn't disable the corresponding port
631 */
632 break;
633 }
634
635 slot = lane_to_slot[lane];
636 if (QIXIS_READ(present2) & (1 << (slot - 1)))
637 fm_disable_port(i);
638 break;
639 default:
640 break;
641 }
642 }
643
644 cpu_eth_init(bis);
645#endif /* CONFIG_FMAN_ENET */
646
647 return pci_eth_init(bis);
648}