blob: 65468ad1656dad3bbd66fea5fcc8b9b7d6590201 [file] [log] [blame]
Heiko Schocher0f8bc282013-12-02 07:47:22 +01001/*
2 * Common board functions for Siemens TAURUS (AT91SAM9G20) based boards
3 * (C) Copyright 2013 Siemens AG
4 *
5 * Based on:
6 * U-Boot file: include/configs/at91sam9260ek.h
7 *
8 * (C) Copyright 2007-2008
9 * Stelian Pop <stelian@popies.net>
10 * Lead Tech Design <www.leadtechdesign.com>
11 *
12 * SPDX-License-Identifier: GPL-2.0+
13 */
14
15#ifndef __CONFIG_H
16#define __CONFIG_H
17
18/*
19 * SoC must be defined first, before hardware.h is included.
20 * In this case SoC is defined in boards.cfg.
21 */
22#include <asm/hardware.h>
23
24#define MACH_TYPE_TAURUS 2067
25#define MACH_TYPE_AXM 2068
26
Heiko Schocherd0b37232014-10-01 07:26:06 +020027#define CONFIG_SYS_GENERIC_BOARD
28
Heiko Schocher389aee82014-11-18 09:41:57 +010029#if defined(CONFIG_SPL_BUILD)
30#define CONFIG_SYS_THUMB_BUILD
31#define CONFIG_SYS_ICACHE_OFF
32#define CONFIG_SYS_DCACHE_OFF
33#endif
Heiko Schocher0f8bc282013-12-02 07:47:22 +010034/*
35 * Warning: changing CONFIG_SYS_TEXT_BASE requires
36 * adapting the initial boot program.
37 * Since the linker has to swallow that define, we must use a pure
38 * hex number here!
39 */
40
41
Heiko Schocher237e3792014-10-31 08:31:05 +010042#define CONFIG_SYS_TEXT_BASE 0x21000000
Heiko Schocher0f8bc282013-12-02 07:47:22 +010043
44/* ARM asynchronous clock */
45#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */
46#define CONFIG_SYS_AT91_MAIN_CLOCK 18432000 /* main clock xtal */
Heiko Schocher0f8bc282013-12-02 07:47:22 +010047
48/* Misc CPU related */
49#define CONFIG_ARCH_CPU_INIT
50#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
51#define CONFIG_SETUP_MEMORY_TAGS
52#define CONFIG_INITRD_TAG
53#define CONFIG_SKIP_LOWLEVEL_INIT
54#define CONFIG_BOARD_EARLY_INIT_F
55#define CONFIG_DISPLAY_CPUINFO
56
57#define CONFIG_CMD_BOOTZ
58#define CONFIG_OF_LIBFDT
59
60/* general purpose I/O */
61#define CONFIG_ATMEL_LEGACY /* required until (g)pio is fixed */
62#define CONFIG_AT91_GPIO
63#define CONFIG_AT91_GPIO_PULLUP 1 /* keep pullups on peripheral pins */
64
65/* serial console */
66#define CONFIG_ATMEL_USART
67#define CONFIG_USART_BASE ATMEL_BASE_DBGU
68#define CONFIG_USART_ID ATMEL_ID_SYS
69#define CONFIG_BAUDRATE 115200
70
71#define CONFIG_BOOTDELAY 3
72
73/*
74 * Command line configuration.
75 */
76#include <config_cmd_default.h>
77#undef CONFIG_CMD_BDI
78#undef CONFIG_CMD_FPGA
79#undef CONFIG_CMD_IMI
80#undef CONFIG_CMD_IMLS
81#undef CONFIG_CMD_LOADS
82#undef CONFIG_CMD_SOURCE
83
84#define CONFIG_CMD_PING
85#define CONFIG_CMD_DHCP
86#define CONFIG_CMD_NAND
87
88/*
89 * SDRAM: 1 bank, min 32, max 128 MB
90 * Initialized before u-boot gets started.
91 */
92#define CONFIG_NR_DRAM_BANKS 1
93#define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_CS1
94#define CONFIG_SYS_SDRAM_SIZE (128 * 1024 * 1024)
95
96/*
97 * Initial stack pointer: 4k - GENERATED_GBL_DATA_SIZE in internal SRAM,
98 * leaving the correct space for initial global data structure above
99 * that address while providing maximum stack area below.
100 */
101# define CONFIG_SYS_INIT_SP_ADDR \
102 (ATMEL_BASE_SRAM1 + 0x1000 - GENERATED_GBL_DATA_SIZE)
103
104/* NAND flash */
105#ifdef CONFIG_CMD_NAND
106#define CONFIG_NAND_ATMEL
107#define CONFIG_SYS_MAX_NAND_DEVICE 1
108#define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3
109#define CONFIG_SYS_NAND_DBW_8
110#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
111#define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
112#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14
113#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PC13
114#endif
115
116/* NOR flash - no real flash on this board */
117#define CONFIG_SYS_NO_FLASH 1
118
119/* Ethernet */
120#define CONFIG_MACB
121#define CONFIG_RMII
122#define CONFIG_AT91_WANTS_COMMON_PHY
123
124/* USB */
125#if defined(CONFIG_BOARD_TAURUS)
126#define CONFIG_USB_ATMEL
127#define CONFIG_USB_OHCI_NEW
128#define CONFIG_SYS_USB_OHCI_CPU_INIT
129#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00500000
130#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9260"
131#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
132#define CONFIG_USB_STORAGE
133#endif
134
Heiko Schocher50921cd2014-10-31 08:30:56 +0100135/* SPI EEPROM */
136#define CONFIG_SPI
137#define CONFIG_CMD_SPI
138#define CONFIG_CMD_SF
139#define CONFIG_SPI_FLASH
140#define CONFIG_ATMEL_SPI
141#define CONFIG_SPI_FLASH_STMICRO
142#define TAURUS_SPI_MASK (1 << 4)
143#define TAURUS_SPI_CS_PIN AT91_PIN_PA3
144
Heiko Schochera1655bb2014-11-18 09:41:58 +0100145#if defined(CONFIG_SPL_BUILD)
146/* SPL related */
147#undef CONFIG_SPL_OS_BOOT /* Not supported by existing map */
148#define CONFIG_SPL_SPI_SUPPORT
149#define CONFIG_SPL_SPI_FLASH_SUPPORT
150#define CONFIG_SPL_SPI_LOAD
151#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000
152
153#define CONFIG_SF_DEFAULT_BUS 0
154#define CONFIG_SF_DEFAULT_SPEED 10000000
155#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
156#endif
157
Heiko Schocher0f8bc282013-12-02 07:47:22 +0100158/* load address */
159#define CONFIG_SYS_LOAD_ADDR 0x22000000
160
161/* bootstrap in spi flash , u-boot + env + linux in nandflash */
162#define CONFIG_ENV_IS_IN_NAND
163#define CONFIG_ENV_OFFSET 0x100000
164#define CONFIG_ENV_OFFSET_REDUND 0x180000
165#define CONFIG_ENV_SIZE 0x20000 /* 1 sector = 128 kB */
166#define CONFIG_BOOTCOMMAND "nand read 0x22000000 0x200000 0x300000; bootm"
167#define CONFIG_BOOTARGS \
168 "console=ttyS0,115200 earlyprintk " \
169 "mtdparts=atmel_nand:256k(bootstrap)ro,512k(uboot)ro," \
170 "256k(env),256k(env_redundant),256k(spare)," \
171 "512k(dtb),6M(kernel)ro,-(rootfs) " \
172 "root=/dev/mtdblock7 rw rootfstype=jffs2"
173
174#define CONFIG_SYS_PROMPT "U-Boot> "
175#define CONFIG_SYS_CBSIZE 256
176#define CONFIG_SYS_MAXARGS 16
177#define CONFIG_SYS_PBSIZE \
178 (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
179#define CONFIG_SYS_LONGHELP
180#define CONFIG_CMDLINE_EDITING
181#define CONFIG_AUTO_COMPLETE
182
183/*
184 * Size of malloc() pool
185 */
186#define CONFIG_SYS_MALLOC_LEN \
187 ROUND(3 * CONFIG_ENV_SIZE + 128*1024, 0x1000)
188
Heiko Schocher237e3792014-10-31 08:31:05 +0100189/* Defines for SPL */
190#define CONFIG_SPL_FRAMEWORK
191#define CONFIG_SPL_TEXT_BASE 0x0
Heiko Schochera1655bb2014-11-18 09:41:58 +0100192#define CONFIG_SPL_MAX_SIZE (14 * 1024)
Heiko Schocher237e3792014-10-31 08:31:05 +0100193#define CONFIG_SPL_STACK (16 * 1024)
Heiko Schochera1655bb2014-11-18 09:41:58 +0100194#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE - \
195 CONFIG_SYS_MALLOC_LEN)
196#define CONFIG_SYS_SPL_MALLOC_SIZE CONFIG_SYS_MALLOC_LEN
Heiko Schocher237e3792014-10-31 08:31:05 +0100197
198#define CONFIG_SPL_BSS_START_ADDR CONFIG_SPL_MAX_SIZE
199#define CONFIG_SPL_BSS_MAX_SIZE (3 * 1024)
200
201#define CONFIG_SPL_LIBCOMMON_SUPPORT
202#define CONFIG_SPL_LIBGENERIC_SUPPORT
203#define CONFIG_SPL_SERIAL_SUPPORT
204
205#define CONFIG_SPL_BOARD_INIT
206#define CONFIG_SPL_GPIO_SUPPORT
207#define CONFIG_SYS_NAND_ENABLE_PIN_SPL (2*32 + 14)
208#define CONFIG_SPL_NAND_SUPPORT
209#define CONFIG_SYS_USE_NANDFLASH 1
210#define CONFIG_SPL_NAND_DRIVERS
211#define CONFIG_SPL_NAND_BASE
212#define CONFIG_SPL_NAND_ECC
213#define CONFIG_SPL_NAND_RAW_ONLY
214#define CONFIG_SPL_NAND_SOFTECC
215#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x20000
216#define CONFIG_SYS_NAND_U_BOOT_SIZE 0x80000
217#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
218#define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE
219#define CONFIG_SYS_NAND_5_ADDR_CYCLE
220
221#define CONFIG_SYS_NAND_SIZE (256*1024*1024)
222#define CONFIG_SYS_NAND_PAGE_SIZE 2048
223#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024)
224#define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \
225 CONFIG_SYS_NAND_PAGE_SIZE)
226#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
227#define CONFIG_SYS_NAND_ECCSIZE 256
228#define CONFIG_SYS_NAND_ECCBYTES 3
229#define CONFIG_SYS_NAND_OOBSIZE 64
230#define CONFIG_SYS_NAND_ECCPOS { 40, 41, 42, 43, 44, 45, 46, 47, \
231 48, 49, 50, 51, 52, 53, 54, 55, \
232 56, 57, 58, 59, 60, 61, 62, 63, }
233
234
235#define CONFIG_SPL_ATMEL_SIZE
236#define CONFIG_SYS_MASTER_CLOCK 132096000
237#define AT91_PLL_LOCK_TIMEOUT 1000000
238#define CONFIG_SYS_AT91_PLLA 0x202A3F01
239#define CONFIG_SYS_MCKR 0x1300
240#define CONFIG_SYS_MCKR_CSS (0x02 | CONFIG_SYS_MCKR)
241#define CONFIG_SYS_AT91_PLLB 0x10193F05
Heiko Schocher0f8bc282013-12-02 07:47:22 +0100242#endif