wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 1 | /* |
| 2 | * (C) Copyright 2003,Motorola Inc. |
| 3 | * Xianghua Xiao <x.xiao@motorola.com> |
| 4 | * Adapted for Motorola 85xx chip. |
| 5 | * |
| 6 | * (C) Copyright 2003 |
| 7 | * Gleb Natapov <gnatapov@mrv.com> |
| 8 | * Some bits are taken from linux driver writen by adrian@humboldt.co.uk |
| 9 | * |
| 10 | * Hardware I2C driver for MPC107 PCI bridge. |
| 11 | * |
| 12 | * See file CREDITS for list of people who contributed to this |
| 13 | * project. |
| 14 | * |
| 15 | * This program is free software; you can redistribute it and/or |
| 16 | * modify it under the terms of the GNU General Public License as |
| 17 | * published by the Free Software Foundation; either version 2 of |
| 18 | * the License, or (at your option) any later version. |
| 19 | * |
| 20 | * This program is distributed in the hope that it will be useful, |
| 21 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 22 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 23 | * GNU General Public License for more details. |
| 24 | * |
| 25 | * You should have received a copy of the GNU General Public License |
| 26 | * along with this program; if not, write to the Free Software |
| 27 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
| 28 | * MA 02111-1307 USA |
| 29 | */ |
| 30 | |
| 31 | #include <common.h> |
| 32 | #include <command.h> |
wdenk | c65fdc7 | 2004-09-28 21:26:26 +0000 | [diff] [blame] | 33 | #include <asm/io.h> |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 34 | |
| 35 | #ifdef CONFIG_HARD_I2C |
| 36 | #include <i2c.h> |
| 37 | |
| 38 | #define TIMEOUT (CFG_HZ/4) |
| 39 | |
wdenk | c65fdc7 | 2004-09-28 21:26:26 +0000 | [diff] [blame] | 40 | #define I2C_Addr ((u8 *)(CFG_CCSRBAR + 0x3000)) |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 41 | |
| 42 | #define I2CADR &I2C_Addr[0] |
wdenk | c65fdc7 | 2004-09-28 21:26:26 +0000 | [diff] [blame] | 43 | #define I2CFDR &I2C_Addr[4] |
| 44 | #define I2CCCR &I2C_Addr[8] |
| 45 | #define I2CCSR &I2C_Addr[12] |
| 46 | #define I2CCDR &I2C_Addr[16] |
| 47 | #define I2CDFSRR &I2C_Addr[20] |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 48 | |
| 49 | #define I2C_READ 1 |
| 50 | #define I2C_WRITE 0 |
| 51 | |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 52 | void |
| 53 | i2c_init(int speed, int slaveadd) |
| 54 | { |
wdenk | c65fdc7 | 2004-09-28 21:26:26 +0000 | [diff] [blame] | 55 | /* stop I2C controller */ |
| 56 | writeb(0x0, I2CCCR); |
| 57 | |
| 58 | /* set clock */ |
| 59 | writeb(0x3f, I2CFDR); |
| 60 | |
| 61 | /* set default filter */ |
| 62 | writeb(0x10,I2CDFSRR); |
| 63 | |
| 64 | /* write slave address */ |
| 65 | writeb(slaveadd, I2CADR); |
| 66 | |
| 67 | /* clear status register */ |
| 68 | writeb(0x0, I2CCSR); |
| 69 | |
| 70 | /* start I2C controller */ |
| 71 | writeb(MPC85xx_I2CCR_MEN, I2CCCR); |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 72 | } |
| 73 | |
| 74 | static __inline__ int |
| 75 | i2c_wait4bus (void) |
| 76 | { |
wdenk | c65fdc7 | 2004-09-28 21:26:26 +0000 | [diff] [blame] | 77 | ulong timeval = get_timer (0); |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 78 | |
wdenk | c65fdc7 | 2004-09-28 21:26:26 +0000 | [diff] [blame] | 79 | while (readb(I2CCSR) & MPC85xx_I2CSR_MBB) { |
| 80 | if (get_timer (timeval) > TIMEOUT) { |
| 81 | return -1; |
| 82 | } |
| 83 | } |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 84 | |
| 85 | return 0; |
| 86 | } |
| 87 | |
| 88 | static __inline__ int |
| 89 | i2c_wait (int write) |
| 90 | { |
wdenk | c65fdc7 | 2004-09-28 21:26:26 +0000 | [diff] [blame] | 91 | u32 csr; |
| 92 | ulong timeval = get_timer (0); |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 93 | |
wdenk | c65fdc7 | 2004-09-28 21:26:26 +0000 | [diff] [blame] | 94 | do { |
| 95 | csr = readb(I2CCSR); |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 96 | |
wdenk | c65fdc7 | 2004-09-28 21:26:26 +0000 | [diff] [blame] | 97 | if (!(csr & MPC85xx_I2CSR_MIF)) |
| 98 | continue; |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 99 | |
wdenk | c65fdc7 | 2004-09-28 21:26:26 +0000 | [diff] [blame] | 100 | writeb(0x0, I2CCSR); |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 101 | |
wdenk | c65fdc7 | 2004-09-28 21:26:26 +0000 | [diff] [blame] | 102 | if (csr & MPC85xx_I2CSR_MAL) { |
| 103 | debug("i2c_wait: MAL\n"); |
| 104 | return -1; |
| 105 | } |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 106 | |
wdenk | c65fdc7 | 2004-09-28 21:26:26 +0000 | [diff] [blame] | 107 | if (!(csr & MPC85xx_I2CSR_MCF)) { |
| 108 | debug("i2c_wait: unfinished\n"); |
| 109 | return -1; |
| 110 | } |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 111 | |
wdenk | c65fdc7 | 2004-09-28 21:26:26 +0000 | [diff] [blame] | 112 | if (write == I2C_WRITE && (csr & MPC85xx_I2CSR_RXAK)) { |
| 113 | debug("i2c_wait: No RXACK\n"); |
| 114 | return -1; |
| 115 | } |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 116 | |
wdenk | c65fdc7 | 2004-09-28 21:26:26 +0000 | [diff] [blame] | 117 | return 0; |
| 118 | } while (get_timer (timeval) < TIMEOUT); |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 119 | |
wdenk | c65fdc7 | 2004-09-28 21:26:26 +0000 | [diff] [blame] | 120 | debug("i2c_wait: timed out\n"); |
| 121 | return -1; |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 122 | } |
| 123 | |
| 124 | static __inline__ int |
| 125 | i2c_write_addr (u8 dev, u8 dir, int rsta) |
| 126 | { |
wdenk | c65fdc7 | 2004-09-28 21:26:26 +0000 | [diff] [blame] | 127 | writeb(MPC85xx_I2CCR_MEN | MPC85xx_I2CCR_MSTA | MPC85xx_I2CCR_MTX | |
| 128 | (rsta?MPC85xx_I2CCR_RSTA:0), |
| 129 | I2CCCR); |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 130 | |
wdenk | c65fdc7 | 2004-09-28 21:26:26 +0000 | [diff] [blame] | 131 | writeb((dev << 1) | dir, I2CCDR); |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 132 | |
wdenk | c65fdc7 | 2004-09-28 21:26:26 +0000 | [diff] [blame] | 133 | if (i2c_wait (I2C_WRITE) < 0) |
| 134 | return 0; |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 135 | |
wdenk | c65fdc7 | 2004-09-28 21:26:26 +0000 | [diff] [blame] | 136 | return 1; |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 137 | } |
| 138 | |
| 139 | static __inline__ int |
| 140 | __i2c_write (u8 *data, int length) |
| 141 | { |
wdenk | c65fdc7 | 2004-09-28 21:26:26 +0000 | [diff] [blame] | 142 | int i; |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 143 | |
wdenk | c65fdc7 | 2004-09-28 21:26:26 +0000 | [diff] [blame] | 144 | writeb(MPC85xx_I2CCR_MEN | MPC85xx_I2CCR_MSTA | MPC85xx_I2CCR_MTX, |
| 145 | I2CCCR); |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 146 | |
wdenk | c65fdc7 | 2004-09-28 21:26:26 +0000 | [diff] [blame] | 147 | for (i=0; i < length; i++) { |
| 148 | writeb(data[i], I2CCDR); |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 149 | |
wdenk | c65fdc7 | 2004-09-28 21:26:26 +0000 | [diff] [blame] | 150 | if (i2c_wait (I2C_WRITE) < 0) |
| 151 | break; |
| 152 | } |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 153 | |
wdenk | c65fdc7 | 2004-09-28 21:26:26 +0000 | [diff] [blame] | 154 | return i; |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 155 | } |
| 156 | |
| 157 | static __inline__ int |
| 158 | __i2c_read (u8 *data, int length) |
| 159 | { |
wdenk | c65fdc7 | 2004-09-28 21:26:26 +0000 | [diff] [blame] | 160 | int i; |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 161 | |
wdenk | c65fdc7 | 2004-09-28 21:26:26 +0000 | [diff] [blame] | 162 | writeb(MPC85xx_I2CCR_MEN | MPC85xx_I2CCR_MSTA | |
| 163 | ((length == 1) ? MPC85xx_I2CCR_TXAK : 0), |
| 164 | I2CCCR); |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 165 | |
wdenk | c65fdc7 | 2004-09-28 21:26:26 +0000 | [diff] [blame] | 166 | /* dummy read */ |
| 167 | readb(I2CCDR); |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 168 | |
wdenk | c65fdc7 | 2004-09-28 21:26:26 +0000 | [diff] [blame] | 169 | for (i=0; i < length; i++) { |
| 170 | if (i2c_wait (I2C_READ) < 0) |
| 171 | break; |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 172 | |
wdenk | c65fdc7 | 2004-09-28 21:26:26 +0000 | [diff] [blame] | 173 | /* Generate ack on last next to last byte */ |
| 174 | if (i == length - 2) |
| 175 | writeb(MPC85xx_I2CCR_MEN | MPC85xx_I2CCR_MSTA | |
| 176 | MPC85xx_I2CCR_TXAK, |
| 177 | I2CCCR); |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 178 | |
wdenk | c65fdc7 | 2004-09-28 21:26:26 +0000 | [diff] [blame] | 179 | /* Generate stop on last byte */ |
| 180 | if (i == length - 1) |
| 181 | writeb(MPC85xx_I2CCR_MEN | MPC85xx_I2CCR_TXAK, I2CCCR); |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 182 | |
wdenk | c65fdc7 | 2004-09-28 21:26:26 +0000 | [diff] [blame] | 183 | data[i] = readb(I2CCDR); |
| 184 | } |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 185 | |
wdenk | c65fdc7 | 2004-09-28 21:26:26 +0000 | [diff] [blame] | 186 | return i; |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 187 | } |
| 188 | |
| 189 | int |
| 190 | i2c_read (u8 dev, uint addr, int alen, u8 *data, int length) |
| 191 | { |
wdenk | c65fdc7 | 2004-09-28 21:26:26 +0000 | [diff] [blame] | 192 | int i = 0; |
| 193 | u8 *a = (u8*)&addr; |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 194 | |
wdenk | c65fdc7 | 2004-09-28 21:26:26 +0000 | [diff] [blame] | 195 | if (i2c_wait4bus () < 0) |
| 196 | goto exit; |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 197 | |
wdenk | c65fdc7 | 2004-09-28 21:26:26 +0000 | [diff] [blame] | 198 | if (i2c_write_addr (dev, I2C_WRITE, 0) == 0) |
| 199 | goto exit; |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 200 | |
wdenk | c65fdc7 | 2004-09-28 21:26:26 +0000 | [diff] [blame] | 201 | if (__i2c_write (&a[4 - alen], alen) != alen) |
| 202 | goto exit; |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 203 | |
wdenk | c65fdc7 | 2004-09-28 21:26:26 +0000 | [diff] [blame] | 204 | if (i2c_write_addr (dev, I2C_READ, 1) == 0) |
| 205 | goto exit; |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 206 | |
wdenk | c65fdc7 | 2004-09-28 21:26:26 +0000 | [diff] [blame] | 207 | i = __i2c_read (data, length); |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 208 | |
| 209 | exit: |
wdenk | c65fdc7 | 2004-09-28 21:26:26 +0000 | [diff] [blame] | 210 | writeb(MPC85xx_I2CCR_MEN, I2CCCR); |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 211 | |
wdenk | c65fdc7 | 2004-09-28 21:26:26 +0000 | [diff] [blame] | 212 | return !(i == length); |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 213 | } |
| 214 | |
| 215 | int |
| 216 | i2c_write (u8 dev, uint addr, int alen, u8 *data, int length) |
| 217 | { |
wdenk | c65fdc7 | 2004-09-28 21:26:26 +0000 | [diff] [blame] | 218 | int i = 0; |
| 219 | u8 *a = (u8*)&addr; |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 220 | |
wdenk | c65fdc7 | 2004-09-28 21:26:26 +0000 | [diff] [blame] | 221 | if (i2c_wait4bus () < 0) |
| 222 | goto exit; |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 223 | |
wdenk | c65fdc7 | 2004-09-28 21:26:26 +0000 | [diff] [blame] | 224 | if (i2c_write_addr (dev, I2C_WRITE, 0) == 0) |
| 225 | goto exit; |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 226 | |
wdenk | c65fdc7 | 2004-09-28 21:26:26 +0000 | [diff] [blame] | 227 | if (__i2c_write (&a[4 - alen], alen) != alen) |
| 228 | goto exit; |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 229 | |
wdenk | c65fdc7 | 2004-09-28 21:26:26 +0000 | [diff] [blame] | 230 | i = __i2c_write (data, length); |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 231 | |
| 232 | exit: |
wdenk | c65fdc7 | 2004-09-28 21:26:26 +0000 | [diff] [blame] | 233 | writeb(MPC85xx_I2CCR_MEN, I2CCCR); |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 234 | |
wdenk | c65fdc7 | 2004-09-28 21:26:26 +0000 | [diff] [blame] | 235 | return !(i == length); |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 236 | } |
| 237 | |
| 238 | int i2c_probe (uchar chip) |
| 239 | { |
| 240 | int tmp; |
| 241 | |
| 242 | /* |
| 243 | * Try to read the first location of the chip. The underlying |
| 244 | * driver doesn't appear to support sending just the chip address |
| 245 | * and looking for an <ACK> back. |
| 246 | */ |
| 247 | udelay(10000); |
| 248 | return i2c_read (chip, 0, 1, (char *)&tmp, 1); |
| 249 | } |
| 250 | |
| 251 | uchar i2c_reg_read (uchar i2c_addr, uchar reg) |
| 252 | { |
| 253 | char buf[1]; |
| 254 | |
| 255 | i2c_read (i2c_addr, reg, 1, buf, 1); |
| 256 | |
| 257 | return (buf[0]); |
| 258 | } |
| 259 | |
| 260 | void i2c_reg_write (uchar i2c_addr, uchar reg, uchar val) |
| 261 | { |
| 262 | i2c_write (i2c_addr, reg, 1, &val, 1); |
| 263 | } |
| 264 | |
| 265 | #endif /* CONFIG_HARD_I2C */ |