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wdenk42d1f032003-10-15 23:53:47 +00001/*
2 * (C) Copyright 2003,Motorola Inc.
3 * Xianghua Xiao <x.xiao@motorola.com>
4 * Adapted for Motorola 85xx chip.
5 *
6 * (C) Copyright 2003
7 * Gleb Natapov <gnatapov@mrv.com>
8 * Some bits are taken from linux driver writen by adrian@humboldt.co.uk
9 *
10 * Hardware I2C driver for MPC107 PCI bridge.
11 *
12 * See file CREDITS for list of people who contributed to this
13 * project.
14 *
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License as
17 * published by the Free Software Foundation; either version 2 of
18 * the License, or (at your option) any later version.
19 *
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
24 *
25 * You should have received a copy of the GNU General Public License
26 * along with this program; if not, write to the Free Software
27 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28 * MA 02111-1307 USA
29 */
30
31#include <common.h>
32#include <command.h>
wdenkc65fdc72004-09-28 21:26:26 +000033#include <asm/io.h>
wdenk42d1f032003-10-15 23:53:47 +000034
35#ifdef CONFIG_HARD_I2C
36#include <i2c.h>
37
38#define TIMEOUT (CFG_HZ/4)
39
wdenkc65fdc72004-09-28 21:26:26 +000040#define I2C_Addr ((u8 *)(CFG_CCSRBAR + 0x3000))
wdenk42d1f032003-10-15 23:53:47 +000041
42#define I2CADR &I2C_Addr[0]
wdenkc65fdc72004-09-28 21:26:26 +000043#define I2CFDR &I2C_Addr[4]
44#define I2CCCR &I2C_Addr[8]
45#define I2CCSR &I2C_Addr[12]
46#define I2CCDR &I2C_Addr[16]
47#define I2CDFSRR &I2C_Addr[20]
wdenk42d1f032003-10-15 23:53:47 +000048
49#define I2C_READ 1
50#define I2C_WRITE 0
51
wdenk42d1f032003-10-15 23:53:47 +000052void
53i2c_init(int speed, int slaveadd)
54{
wdenkc65fdc72004-09-28 21:26:26 +000055 /* stop I2C controller */
56 writeb(0x0, I2CCCR);
57
58 /* set clock */
59 writeb(0x3f, I2CFDR);
60
61 /* set default filter */
62 writeb(0x10,I2CDFSRR);
63
64 /* write slave address */
65 writeb(slaveadd, I2CADR);
66
67 /* clear status register */
68 writeb(0x0, I2CCSR);
69
70 /* start I2C controller */
71 writeb(MPC85xx_I2CCR_MEN, I2CCCR);
wdenk42d1f032003-10-15 23:53:47 +000072}
73
74static __inline__ int
75i2c_wait4bus (void)
76{
wdenkc65fdc72004-09-28 21:26:26 +000077 ulong timeval = get_timer (0);
wdenk42d1f032003-10-15 23:53:47 +000078
wdenkc65fdc72004-09-28 21:26:26 +000079 while (readb(I2CCSR) & MPC85xx_I2CSR_MBB) {
80 if (get_timer (timeval) > TIMEOUT) {
81 return -1;
82 }
83 }
wdenk42d1f032003-10-15 23:53:47 +000084
85 return 0;
86}
87
88static __inline__ int
89i2c_wait (int write)
90{
wdenkc65fdc72004-09-28 21:26:26 +000091 u32 csr;
92 ulong timeval = get_timer (0);
wdenk42d1f032003-10-15 23:53:47 +000093
wdenkc65fdc72004-09-28 21:26:26 +000094 do {
95 csr = readb(I2CCSR);
wdenk42d1f032003-10-15 23:53:47 +000096
wdenkc65fdc72004-09-28 21:26:26 +000097 if (!(csr & MPC85xx_I2CSR_MIF))
98 continue;
wdenk42d1f032003-10-15 23:53:47 +000099
wdenkc65fdc72004-09-28 21:26:26 +0000100 writeb(0x0, I2CCSR);
wdenk42d1f032003-10-15 23:53:47 +0000101
wdenkc65fdc72004-09-28 21:26:26 +0000102 if (csr & MPC85xx_I2CSR_MAL) {
103 debug("i2c_wait: MAL\n");
104 return -1;
105 }
wdenk42d1f032003-10-15 23:53:47 +0000106
wdenkc65fdc72004-09-28 21:26:26 +0000107 if (!(csr & MPC85xx_I2CSR_MCF)) {
108 debug("i2c_wait: unfinished\n");
109 return -1;
110 }
wdenk42d1f032003-10-15 23:53:47 +0000111
wdenkc65fdc72004-09-28 21:26:26 +0000112 if (write == I2C_WRITE && (csr & MPC85xx_I2CSR_RXAK)) {
113 debug("i2c_wait: No RXACK\n");
114 return -1;
115 }
wdenk42d1f032003-10-15 23:53:47 +0000116
wdenkc65fdc72004-09-28 21:26:26 +0000117 return 0;
118 } while (get_timer (timeval) < TIMEOUT);
wdenk42d1f032003-10-15 23:53:47 +0000119
wdenkc65fdc72004-09-28 21:26:26 +0000120 debug("i2c_wait: timed out\n");
121 return -1;
wdenk42d1f032003-10-15 23:53:47 +0000122}
123
124static __inline__ int
125i2c_write_addr (u8 dev, u8 dir, int rsta)
126{
wdenkc65fdc72004-09-28 21:26:26 +0000127 writeb(MPC85xx_I2CCR_MEN | MPC85xx_I2CCR_MSTA | MPC85xx_I2CCR_MTX |
128 (rsta?MPC85xx_I2CCR_RSTA:0),
129 I2CCCR);
wdenk42d1f032003-10-15 23:53:47 +0000130
wdenkc65fdc72004-09-28 21:26:26 +0000131 writeb((dev << 1) | dir, I2CCDR);
wdenk42d1f032003-10-15 23:53:47 +0000132
wdenkc65fdc72004-09-28 21:26:26 +0000133 if (i2c_wait (I2C_WRITE) < 0)
134 return 0;
wdenk42d1f032003-10-15 23:53:47 +0000135
wdenkc65fdc72004-09-28 21:26:26 +0000136 return 1;
wdenk42d1f032003-10-15 23:53:47 +0000137}
138
139static __inline__ int
140__i2c_write (u8 *data, int length)
141{
wdenkc65fdc72004-09-28 21:26:26 +0000142 int i;
wdenk42d1f032003-10-15 23:53:47 +0000143
wdenkc65fdc72004-09-28 21:26:26 +0000144 writeb(MPC85xx_I2CCR_MEN | MPC85xx_I2CCR_MSTA | MPC85xx_I2CCR_MTX,
145 I2CCCR);
wdenk42d1f032003-10-15 23:53:47 +0000146
wdenkc65fdc72004-09-28 21:26:26 +0000147 for (i=0; i < length; i++) {
148 writeb(data[i], I2CCDR);
wdenk42d1f032003-10-15 23:53:47 +0000149
wdenkc65fdc72004-09-28 21:26:26 +0000150 if (i2c_wait (I2C_WRITE) < 0)
151 break;
152 }
wdenk42d1f032003-10-15 23:53:47 +0000153
wdenkc65fdc72004-09-28 21:26:26 +0000154 return i;
wdenk42d1f032003-10-15 23:53:47 +0000155}
156
157static __inline__ int
158__i2c_read (u8 *data, int length)
159{
wdenkc65fdc72004-09-28 21:26:26 +0000160 int i;
wdenk42d1f032003-10-15 23:53:47 +0000161
wdenkc65fdc72004-09-28 21:26:26 +0000162 writeb(MPC85xx_I2CCR_MEN | MPC85xx_I2CCR_MSTA |
163 ((length == 1) ? MPC85xx_I2CCR_TXAK : 0),
164 I2CCCR);
wdenk42d1f032003-10-15 23:53:47 +0000165
wdenkc65fdc72004-09-28 21:26:26 +0000166 /* dummy read */
167 readb(I2CCDR);
wdenk42d1f032003-10-15 23:53:47 +0000168
wdenkc65fdc72004-09-28 21:26:26 +0000169 for (i=0; i < length; i++) {
170 if (i2c_wait (I2C_READ) < 0)
171 break;
wdenk42d1f032003-10-15 23:53:47 +0000172
wdenkc65fdc72004-09-28 21:26:26 +0000173 /* Generate ack on last next to last byte */
174 if (i == length - 2)
175 writeb(MPC85xx_I2CCR_MEN | MPC85xx_I2CCR_MSTA |
176 MPC85xx_I2CCR_TXAK,
177 I2CCCR);
wdenk42d1f032003-10-15 23:53:47 +0000178
wdenkc65fdc72004-09-28 21:26:26 +0000179 /* Generate stop on last byte */
180 if (i == length - 1)
181 writeb(MPC85xx_I2CCR_MEN | MPC85xx_I2CCR_TXAK, I2CCCR);
wdenk42d1f032003-10-15 23:53:47 +0000182
wdenkc65fdc72004-09-28 21:26:26 +0000183 data[i] = readb(I2CCDR);
184 }
wdenk42d1f032003-10-15 23:53:47 +0000185
wdenkc65fdc72004-09-28 21:26:26 +0000186 return i;
wdenk42d1f032003-10-15 23:53:47 +0000187}
188
189int
190i2c_read (u8 dev, uint addr, int alen, u8 *data, int length)
191{
wdenkc65fdc72004-09-28 21:26:26 +0000192 int i = 0;
193 u8 *a = (u8*)&addr;
wdenk42d1f032003-10-15 23:53:47 +0000194
wdenkc65fdc72004-09-28 21:26:26 +0000195 if (i2c_wait4bus () < 0)
196 goto exit;
wdenk42d1f032003-10-15 23:53:47 +0000197
wdenkc65fdc72004-09-28 21:26:26 +0000198 if (i2c_write_addr (dev, I2C_WRITE, 0) == 0)
199 goto exit;
wdenk42d1f032003-10-15 23:53:47 +0000200
wdenkc65fdc72004-09-28 21:26:26 +0000201 if (__i2c_write (&a[4 - alen], alen) != alen)
202 goto exit;
wdenk42d1f032003-10-15 23:53:47 +0000203
wdenkc65fdc72004-09-28 21:26:26 +0000204 if (i2c_write_addr (dev, I2C_READ, 1) == 0)
205 goto exit;
wdenk42d1f032003-10-15 23:53:47 +0000206
wdenkc65fdc72004-09-28 21:26:26 +0000207 i = __i2c_read (data, length);
wdenk42d1f032003-10-15 23:53:47 +0000208
209 exit:
wdenkc65fdc72004-09-28 21:26:26 +0000210 writeb(MPC85xx_I2CCR_MEN, I2CCCR);
wdenk42d1f032003-10-15 23:53:47 +0000211
wdenkc65fdc72004-09-28 21:26:26 +0000212 return !(i == length);
wdenk42d1f032003-10-15 23:53:47 +0000213}
214
215int
216i2c_write (u8 dev, uint addr, int alen, u8 *data, int length)
217{
wdenkc65fdc72004-09-28 21:26:26 +0000218 int i = 0;
219 u8 *a = (u8*)&addr;
wdenk42d1f032003-10-15 23:53:47 +0000220
wdenkc65fdc72004-09-28 21:26:26 +0000221 if (i2c_wait4bus () < 0)
222 goto exit;
wdenk42d1f032003-10-15 23:53:47 +0000223
wdenkc65fdc72004-09-28 21:26:26 +0000224 if (i2c_write_addr (dev, I2C_WRITE, 0) == 0)
225 goto exit;
wdenk42d1f032003-10-15 23:53:47 +0000226
wdenkc65fdc72004-09-28 21:26:26 +0000227 if (__i2c_write (&a[4 - alen], alen) != alen)
228 goto exit;
wdenk42d1f032003-10-15 23:53:47 +0000229
wdenkc65fdc72004-09-28 21:26:26 +0000230 i = __i2c_write (data, length);
wdenk42d1f032003-10-15 23:53:47 +0000231
232 exit:
wdenkc65fdc72004-09-28 21:26:26 +0000233 writeb(MPC85xx_I2CCR_MEN, I2CCCR);
wdenk42d1f032003-10-15 23:53:47 +0000234
wdenkc65fdc72004-09-28 21:26:26 +0000235 return !(i == length);
wdenk42d1f032003-10-15 23:53:47 +0000236}
237
238int i2c_probe (uchar chip)
239{
240 int tmp;
241
242 /*
243 * Try to read the first location of the chip. The underlying
244 * driver doesn't appear to support sending just the chip address
245 * and looking for an <ACK> back.
246 */
247 udelay(10000);
248 return i2c_read (chip, 0, 1, (char *)&tmp, 1);
249}
250
251uchar i2c_reg_read (uchar i2c_addr, uchar reg)
252{
253 char buf[1];
254
255 i2c_read (i2c_addr, reg, 1, buf, 1);
256
257 return (buf[0]);
258}
259
260void i2c_reg_write (uchar i2c_addr, uchar reg, uchar val)
261{
262 i2c_write (i2c_addr, reg, 1, &val, 1);
263}
264
265#endif /* CONFIG_HARD_I2C */