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Dirk Eibacha605ea72010-10-21 10:50:05 +02001/*
2 * (C) Copyright 2010
3 * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
4 *
Wolfgang Denk3765b3e2013-10-07 13:07:26 +02005 * SPDX-License-Identifier: GPL-2.0+
Dirk Eibacha605ea72010-10-21 10:50:05 +02006 */
7
8#ifndef __CONFIG_H
9#define __CONFIG_H
10
11#define CONFIG_405EP 1 /* this is a PPC405 CPU */
Dirk Eibacha605ea72010-10-21 10:50:05 +020012#define CONFIG_IOCON 1 /* on a IoCon board */
13
14#define CONFIG_SYS_TEXT_BASE 0xFFFC0000
15
16/*
17 * Include common defines/options for all AMCC eval boards
18 */
19#define CONFIG_HOSTNAME iocon
Dirk Eibachcccd4f42014-07-03 09:28:20 +020020#define CONFIG_IDENT_STRING " iocon 0.06"
Dirk Eibacha605ea72010-10-21 10:50:05 +020021#include "amcc-common.h"
22
Dirk Eibach6e9e6c32012-04-26 03:54:22 +000023#define CONFIG_BOARD_EARLY_INIT_F
24#define CONFIG_BOARD_EARLY_INIT_R
Dirk Eibacha605ea72010-10-21 10:50:05 +020025#define CONFIG_LAST_STAGE_INIT
26
27#define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */
28
29/*
30 * Configure PLL
31 */
32#define PLLMR0_DEFAULT PLLMR0_266_133_66
33#define PLLMR1_DEFAULT PLLMR1_266_133_66
34
Dirk Eibach996d88d2012-04-26 03:54:25 +000035#undef CONFIG_ZERO_BOOTDELAY_CHECK /* ignore keypress on bootdelay==0 */
Dirk Eibach996d88d2012-04-26 03:54:25 +000036
Dirk Eibacha605ea72010-10-21 10:50:05 +020037/* new uImage format support */
Dirk Eibach9a4f4792014-07-03 09:28:26 +020038#define CONFIG_FIT_DISABLE_SHA256
Dirk Eibacha605ea72010-10-21 10:50:05 +020039
40#define CONFIG_ENV_IS_IN_FLASH /* use FLASH for environment vars */
41
42/*
43 * Default environment variables
44 */
45#define CONFIG_EXTRA_ENV_SETTINGS \
46 CONFIG_AMCC_DEF_ENV \
47 CONFIG_AMCC_DEF_ENV_POWERPC \
48 CONFIG_AMCC_DEF_ENV_NOR_UPD \
49 "kernel_addr=fc000000\0" \
50 "fdt_addr=fc1e0000\0" \
51 "ramdisk_addr=fc200000\0" \
52 ""
53
54#define CONFIG_PHY_ADDR 4 /* PHY address */
55#define CONFIG_HAS_ETH0
56#define CONFIG_PHY_CLK_FREQ EMAC_STACR_CLK_66MHZ
57
58/*
59 * Commands additional to the ones defined in amcc-common.h
60 */
61#define CONFIG_CMD_CACHE
Michal Simek7d2357c2014-06-17 00:36:14 +020062#define CONFIG_CMD_FPGAD
Dirk Eibacha605ea72010-10-21 10:50:05 +020063#undef CONFIG_CMD_EEPROM
Dirk Eibach4fb9b412014-07-03 09:28:25 +020064#undef CONFIG_CMD_I2C
65#undef CONFIG_CMD_IRQ
Dirk Eibacha605ea72010-10-21 10:50:05 +020066
67/*
68 * SDRAM configuration (please see cpu/ppc/sdram.[ch])
69 */
70#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
71
72/* SDRAM timings used in datasheet */
73#define CONFIG_SYS_SDRAM_CL 3 /* CAS latency */
74#define CONFIG_SYS_SDRAM_tRP 20 /* PRECHARGE command period */
75#define CONFIG_SYS_SDRAM_tRC 66 /* ACTIVE-to-ACTIVE period */
76#define CONFIG_SYS_SDRAM_tRCD 20 /* ACTIVE-to-READ delay */
77#define CONFIG_SYS_SDRAM_tRFC 66 /* Auto refresh period */
78
79/*
80 * If CONFIG_SYS_EXT_SERIAL_CLOCK, then the UART divisor is 1.
81 * If CONFIG_SYS_405_UART_ERRATA_59, then UART divisor is 31.
82 * Otherwise, UART divisor is determined by CPU Clock and CONFIG_SYS_BASE_BAUD.
83 * The Linux BASE_BAUD define should match this configuration.
84 * baseBaud = cpuClock/(uartDivisor*16)
85 * If CONFIG_SYS_405_UART_ERRATA_59 and 200MHz CPU clock,
86 * set Linux BASE_BAUD to 403200.
87 */
88#define CONFIG_CONS_INDEX 1 /* Use UART0 */
89#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* external serial clock */
90#undef CONFIG_SYS_405_UART_ERRATA_59 /* 405GP/CR Rev. D silicon */
91#define CONFIG_SYS_BASE_BAUD 691200
92
93/*
94 * I2C stuff
95 */
Heiko Schocherea818db2013-01-29 08:53:15 +010096#define CONFIG_SYS_I2C
Dirk Eibach880540d2013-04-25 02:40:01 +000097#define CONFIG_SYS_I2C_PPC4XX
98#define CONFIG_SYS_I2C_PPC4XX_CH0
99#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000
100#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F
Dirk Eibachb46226b2014-07-03 09:28:18 +0200101#define CONFIG_SYS_I2C_IHS
Dirk Eibacha605ea72010-10-21 10:50:05 +0200102
Dirk Eibache50e8962013-07-25 19:28:13 +0200103#define CONFIG_SYS_I2C_SPEED 400000
Dirk Eibachb46226b2014-07-03 09:28:18 +0200104#define CONFIG_SYS_SPD_BUS_NUM 4
Dirk Eibache50e8962013-07-25 19:28:13 +0200105
106#define CONFIG_PCA953X /* NXP PCA9554 */
107#define CONFIG_PCA9698 /* NXP PCA9698 */
108
Dirk Eibachb46226b2014-07-03 09:28:18 +0200109#define CONFIG_SYS_I2C_IHS_CH0
110#define CONFIG_SYS_I2C_IHS_SPEED_0 50000
111#define CONFIG_SYS_I2C_IHS_SLAVE_0 0x7F
112#define CONFIG_SYS_I2C_IHS_CH1
113#define CONFIG_SYS_I2C_IHS_SPEED_1 50000
114#define CONFIG_SYS_I2C_IHS_SLAVE_1 0x7F
115#define CONFIG_SYS_I2C_IHS_CH2
116#define CONFIG_SYS_I2C_IHS_SPEED_2 50000
117#define CONFIG_SYS_I2C_IHS_SLAVE_2 0x7F
118#define CONFIG_SYS_I2C_IHS_CH3
119#define CONFIG_SYS_I2C_IHS_SPEED_3 50000
120#define CONFIG_SYS_I2C_IHS_SLAVE_3 0x7F
121
Dirk Eibacha605ea72010-10-21 10:50:05 +0200122/*
123 * Software (bit-bang) I2C driver configuration
124 */
Dirk Eibache50e8962013-07-25 19:28:13 +0200125#define CONFIG_SYS_I2C_SOFT
126#define CONFIG_SYS_I2C_SOFT_SPEED 50000
127#define CONFIG_SYS_I2C_SOFT_SLAVE 0x7F
128#define I2C_SOFT_DECLARATIONS2
129#define CONFIG_SYS_I2C_SOFT_SPEED_2 50000
130#define CONFIG_SYS_I2C_SOFT_SLAVE_2 0x7F
131#define I2C_SOFT_DECLARATIONS3
132#define CONFIG_SYS_I2C_SOFT_SPEED_3 50000
133#define CONFIG_SYS_I2C_SOFT_SLAVE_3 0x7F
134#define I2C_SOFT_DECLARATIONS4
135#define CONFIG_SYS_I2C_SOFT_SPEED_4 50000
136#define CONFIG_SYS_I2C_SOFT_SLAVE_4 0x7F
137
Dirk Eibachb46226b2014-07-03 09:28:18 +0200138#define CONFIG_SYS_ICS8N3QV01_I2C {5, 6, 7, 8}
139#define CONFIG_SYS_CH7301_I2C {5, 6, 7, 8}
140#define CONFIG_SYS_DP501_I2C {0, 1, 2, 3}
Dirk Eibacha605ea72010-10-21 10:50:05 +0200141
142#ifndef __ASSEMBLY__
Dirk Eibache50e8962013-07-25 19:28:13 +0200143void fpga_gpio_set(unsigned int bus, int pin);
144void fpga_gpio_clear(unsigned int bus, int pin);
145int fpga_gpio_get(unsigned int bus, int pin);
Dirk Eibacha605ea72010-10-21 10:50:05 +0200146#endif
147
148#define I2C_ACTIVE { }
149#define I2C_TRISTATE { }
Dirk Eibache50e8962013-07-25 19:28:13 +0200150#define I2C_READ \
151 (fpga_gpio_get(I2C_ADAP_HWNR, 0x0040) ? 1 : 0)
152#define I2C_SDA(bit) \
153 do { \
154 if (bit) \
155 fpga_gpio_set(I2C_ADAP_HWNR, 0x0040); \
156 else \
157 fpga_gpio_clear(I2C_ADAP_HWNR, 0x0040); \
158 } while (0)
159#define I2C_SCL(bit) \
160 do { \
161 if (bit) \
162 fpga_gpio_set(I2C_ADAP_HWNR, 0x0020); \
163 else \
164 fpga_gpio_clear(I2C_ADAP_HWNR, 0x0020); \
165 } while (0)
Dirk Eibacha605ea72010-10-21 10:50:05 +0200166#define I2C_DELAY udelay(25) /* 1/4 I2C clock duration */
167
168/*
169 * FLASH organization
170 */
171#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */
172#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
173
174#define CONFIG_SYS_FLASH_BASE 0xFC000000
175#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
176
177#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */
178#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sectors per chip*/
179
180#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase/ms */
181#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write/ms */
182
183#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buff'd writes */
Dirk Eibacha605ea72010-10-21 10:50:05 +0200184
185#define CONFIG_SYS_FLASH_EMPTY_INFO /* 'E' for empty sector on flinfo */
186#define CONFIG_SYS_FLASH_QUIET_TEST 1 /* no warn upon unknown flash */
187
188#ifdef CONFIG_ENV_IS_IN_FLASH
189#define CONFIG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
190#define CONFIG_ENV_ADDR ((-CONFIG_SYS_MONITOR_LEN)-CONFIG_ENV_SECT_SIZE)
191#define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
192
193/* Address and size of Redundant Environment Sector */
194#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
195#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
196#endif
197
198/*
199 * PPC405 GPIO Configuration
200 */
201#define CONFIG_SYS_4xx_GPIO_TABLE { /* GPIO Alternate1 */ \
202{ \
203/* GPIO Core 0 */ \
204{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO0 PerBLast */ \
205{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO1 TS1E */ \
206{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO2 TS2E */ \
207{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO3 TS1O */ \
208{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO4 TS2O */ \
209{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_1 }, /* GPIO5 TS3 */ \
210{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO6 TS4 */ \
211{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO7 TS5 */ \
212{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO8 TS6 */ \
213{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO9 TrcClk */ \
214{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO10 PerCS1 */ \
215{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO11 PerCS2 */ \
216{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO12 PerCS3 */ \
217{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO13 PerCS4 */ \
218{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO14 PerAddr03 */ \
219{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO15 PerAddr04 */ \
220{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO16 PerAddr05 */ \
221{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO17 IRQ0 */ \
222{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO18 IRQ1 */ \
223{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO19 IRQ2 */ \
224{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO20 IRQ3 */ \
225{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO21 IRQ4 */ \
226{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO22 IRQ5 */ \
227{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO23 IRQ6 */ \
228{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO24 UART0_DCD */ \
229{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO25 UART0_DSR */ \
230{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO26 UART0_RI */ \
231{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO27 UART0_DTR */ \
232{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO28 UART1_Rx */ \
233{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO29 UART1_Tx */ \
234{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO30 RejectPkt0 */ \
235{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO31 RejectPkt1 */ \
236} \
237}
238
239/*
240 * Definitions for initial stack pointer and data area (in data cache)
241 */
242/* use on chip memory (OCM) for temperary stack until sdram is tested */
243#define CONFIG_SYS_TEMP_STACK_OCM 1
244
245/* On Chip Memory location */
246#define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000
247#define CONFIG_SYS_OCM_DATA_SIZE 0x1000
248#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* in SDRAM */
249#define CONFIG_SYS_INIT_RAM_END CONFIG_SYS_OCM_DATA_SIZE /* End of used area */
250
Dirk Eibacha605ea72010-10-21 10:50:05 +0200251#define CONFIG_SYS_GBL_DATA_OFFSET \
Masahiro Yamada627b73e2014-02-07 09:23:03 +0900252 (CONFIG_SYS_INIT_RAM_END - GENERATED_GBL_DATA_SIZE)
Dirk Eibacha605ea72010-10-21 10:50:05 +0200253#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
254
255/*
256 * External Bus Controller (EBC) Setup
257 */
258
259/* Memory Bank 0 (NOR-FLASH) initialization */
260#define CONFIG_SYS_EBC_PB0AP 0xa382a880
261#define CONFIG_SYS_EBC_PB0CR 0xFC0DA000
262
263/* Memory Bank 1 (NVRAM) initializatio */
264#define CONFIG_SYS_EBC_PB1AP 0x92015480
265#define CONFIG_SYS_EBC_PB1CR 0xFB858000
266
Dirk Eibach2da0fc02011-01-21 09:31:21 +0100267/* Memory Bank 2 (FPGA0) initialization */
268#define CONFIG_SYS_FPGA0_BASE 0x7f100000
Dirk Eibacha605ea72010-10-21 10:50:05 +0200269#define CONFIG_SYS_EBC_PB2AP 0x02825080
Dirk Eibach2da0fc02011-01-21 09:31:21 +0100270#define CONFIG_SYS_EBC_PB2CR (CONFIG_SYS_FPGA0_BASE | 0x1a000)
Dirk Eibacha605ea72010-10-21 10:50:05 +0200271
Dirk Eibach2da0fc02011-01-21 09:31:21 +0100272#define CONFIG_SYS_FPGA_BASE(k) CONFIG_SYS_FPGA0_BASE
273#define CONFIG_SYS_FPGA_DONE(k) 0x0010
274
275#define CONFIG_SYS_FPGA_COUNT 1
Dirk Eibacha605ea72010-10-21 10:50:05 +0200276
Dirk Eibache50e8962013-07-25 19:28:13 +0200277#define CONFIG_SYS_MCLINK_MAX 3
Dirk Eibachaba27ac2013-06-26 16:04:26 +0200278
Dirk Eibache50e8962013-07-25 19:28:13 +0200279#define CONFIG_SYS_FPGA_PTR \
280 { (struct ihs_fpga *)CONFIG_SYS_FPGA0_BASE, NULL, NULL, NULL }
Dirk Eibachaba27ac2013-06-26 16:04:26 +0200281
Dirk Eibacha605ea72010-10-21 10:50:05 +0200282/* Memory Bank 3 (Latches) initialization */
283#define CONFIG_SYS_LATCH_BASE 0x7f200000
284#define CONFIG_SYS_EBC_PB3AP 0x02025080
285#define CONFIG_SYS_EBC_PB3CR 0x7f21a000
286
287#define CONFIG_SYS_LATCH0_RESET 0xffef
288#define CONFIG_SYS_LATCH0_BOOT 0xffff
289#define CONFIG_SYS_LATCH1_RESET 0xffff
290#define CONFIG_SYS_LATCH1_BOOT 0xffff
291
Dirk Eibach2da0fc02011-01-21 09:31:21 +0100292/*
293 * OSD Setup
294 */
295#define CONFIG_SYS_MPC92469AC
Dirk Eibache50e8962013-07-25 19:28:13 +0200296#define CONFIG_SYS_OSD_SCREENS 1
Dirk Eibachedfe9fe2014-07-03 09:28:17 +0200297#define CONFIG_SYS_DP501_DIFFERENTIAL
298#define CONFIG_SYS_DP501_VCAPCTRL0 0x01 /* DDR mode 0, DE for H/VSYNC */
Dirk Eibache50e8962013-07-25 19:28:13 +0200299
300#define CONFIG_BITBANGMII /* bit-bang MII PHY management */
301#define CONFIG_BITBANGMII_MULTI
Dirk Eibach2da0fc02011-01-21 09:31:21 +0100302
Dirk Eibacha605ea72010-10-21 10:50:05 +0200303#endif /* __CONFIG_H */