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Albert ARIBAUD \(3ADEV\)931a1d22015-09-21 22:43:39 +02001/*
2 * Copyright 2013 Freescale Semiconductor, Inc.
3 *
4 * Configuration settings for the phytec PCM-052 SoM.
5 *
6 * SPDX-License-Identifier: GPL-2.0+
7 */
8
9#ifndef __CONFIG_H
10#define __CONFIG_H
11
12#include <asm/arch/imx-regs.h>
13
14#define CONFIG_VF610
15
Albert ARIBAUD \(3ADEV\)931a1d22015-09-21 22:43:39 +020016#define CONFIG_DISPLAY_CPUINFO
17#define CONFIG_DISPLAY_BOARDINFO
18#define CONFIG_SYS_THUMB_BUILD
19
20#define CONFIG_SKIP_LOWLEVEL_INIT
21
22/* Enable passing of ATAGs */
23#define CONFIG_CMDLINE_TAG
24
25/* Size of malloc() pool */
26#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2 * 1024 * 1024)
27
28#define CONFIG_BOARD_EARLY_INIT_F
29
30#define CONFIG_FSL_LPUART
31#define LPUART_BASE UART1_BASE
32
33/* Allow to overwrite serial and ethaddr */
34#define CONFIG_ENV_OVERWRITE
35#define CONFIG_SYS_UART_PORT (1)
36#define CONFIG_BAUDRATE 115200
37
38#undef CONFIG_CMD_IMLS
39
40/* NAND support */
41#define CONFIG_CMD_NAND
42#define CONFIG_CMD_NAND_TRIMFFS
43#define CONFIG_SYS_NAND_ONFI_DETECTION
44
45#ifdef CONFIG_CMD_NAND
46#define CONFIG_USE_ARCH_MEMCPY
47#define CONFIG_SYS_MAX_NAND_DEVICE 1
48#define CONFIG_SYS_NAND_BASE NFC_BASE_ADDR
49
50#define CONFIG_JFFS2_NAND
51
52/* UBI */
53#define CONFIG_CMD_UBI
54#define CONFIG_CMD_UBIFS
55#define CONFIG_RBTREE
56#define CONFIG_LZO
57
58/* Dynamic MTD partition support */
59#define CONFIG_CMD_MTDPARTS
60#define CONFIG_MTD_PARTITIONS
61#define CONFIG_MTD_DEVICE
Albert ARIBAUD (3ADEV)040ef8f2015-10-11 20:06:39 +020062#define MTDIDS_DEFAULT "nand0=NAND"
Albert ARIBAUD \(3ADEV\)931a1d22015-09-21 22:43:39 +020063#define MTDPARTS_DEFAULT "mtdparts=NAND:256k(spare)"\
64 ",384k(bootloader)"\
65 ",128k(env1)"\
66 ",128k(env2)"\
Albert ARIBAUD (3ADEV)040ef8f2015-10-11 20:06:39 +020067 ",128k(dtb)"\
68 ",6144k(kernel)"\
69 ",65536k(ramdisk)"\
70 ",450944k(root)"
Albert ARIBAUD \(3ADEV\)931a1d22015-09-21 22:43:39 +020071#endif
72
73#define CONFIG_MMC
74#define CONFIG_FSL_ESDHC
75#define CONFIG_SYS_FSL_ESDHC_ADDR 0
76#define CONFIG_SYS_FSL_ESDHC_NUM 1
77
78/*#define CONFIG_ESDHC_DETECT_USE_EXTERN_IRQ1*/
79#define CONFIG_SYS_FSL_ERRATUM_ESDHC135
80#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
81#define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001
82
83#define CONFIG_CMD_MMC
84#define CONFIG_GENERIC_MMC
85#define CONFIG_CMD_FAT
86#define CONFIG_DOS_PARTITION
87
88#define CONFIG_CMD_PING
89#define CONFIG_CMD_DHCP
90#define CONFIG_CMD_MII
91#define CONFIG_FEC_MXC
92#define CONFIG_MII
93#define IMX_FEC_BASE ENET_BASE_ADDR
94#define CONFIG_FEC_XCV_TYPE RMII
95#define CONFIG_FEC_MXC_PHYADDR 0
96#define CONFIG_PHYLIB
97#define CONFIG_PHY_MICREL
98
99/* QSPI Configs*/
Albert ARIBAUD \(3ADEV\)931a1d22015-09-21 22:43:39 +0200100
101#ifdef CONFIG_FSL_QSPI
102#define CONFIG_CMD_SF
103#define CONFIG_SPI_FLASH
Albert ARIBAUD \(3ADEV\)931a1d22015-09-21 22:43:39 +0200104#define FSL_QSPI_FLASH_SIZE (1 << 24)
105#define FSL_QSPI_FLASH_NUM 2
106#define CONFIG_SYS_FSL_QSPI_LE
107#endif
108
109/* I2C Configs */
110#define CONFIG_CMD_I2C
111#define CONFIG_SYS_I2C
112#define CONFIG_SYS_I2C_MXC_I2C3
113#define CONFIG_SYS_I2C_MXC
114
115/* RTC (actually an RV-4162 but M41T62-compatible) */
116#define CONFIG_CMD_DATE
117#define CONFIG_RTC_M41T62
118#define CONFIG_SYS_I2C_RTC_ADDR 0x68
119#define CONFIG_SYS_RTC_BUS_NUM 2
120
121/* EEPROM (24FC256) */
122#define CONFIG_CMD_EEPROM
123#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
124#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
125#define CONFIG_SYS_I2C_EEPROM_BUS 2
126
127#define CONFIG_BOOTDELAY 3
128
129#define CONFIG_LOADADDR 0x82000000
130
131/* We boot from the gfxRAM area of the OCRAM. */
132#define CONFIG_SYS_TEXT_BASE 0x3f408000
133#define CONFIG_BOARD_SIZE_LIMIT 524288
134
135#define CONFIG_BOOTCOMMAND "run bootcmd_sd"
Albert ARIBAUD (3ADEV)040ef8f2015-10-11 20:06:39 +0200136#define CONFIG_EXTRA_ENV_SETTINGS \
137 "fdt_high=0xffffffff\0" \
138 "initrd_high=0xffffffff\0" \
139 "blimg_file=u-boot.imx\0" \
140 "blsec_addr=0x81000000\0" \
141 "blimg_addr=0x81000400\0" \
142 "kernel_file=zImage\0" \
143 "kernel_addr=0x82000000\0" \
144 "fdt_file=vf610-pcm052.dtb\0" \
145 "fdt_addr=0x81000000\0" \
146 "ram_file=uRamdisk\0" \
147 "ram_addr=0x83000000\0" \
148 "filesys=rootfs.ubifs\0" \
149 "sys_addr=0x81000000\0" \
150 "tftploc=/path/to/tftp/directory/\0" \
151 "nfs_root=/path/to/nfs/root\0" \
152 "tftptimeout=1000\0" \
153 "tftptimeoutcountmax=1000000\0" \
154 "mtdparts=" MTDPARTS_DEFAULT "\0" \
155 "bootargs_base=setenv bootargs rw mem=256M " \
156 "console=ttyLP1,115200n8\0" \
157 "bootargs_sd=setenv bootargs ${bootargs} " \
158 "root=/dev/mmcblk0p2 rootwait\0" \
Albert ARIBAUD \(3ADEV\)931a1d22015-09-21 22:43:39 +0200159 "bootargs_net=setenv bootargs ${bootargs} root=/dev/nfs ip=dhcp " \
Albert ARIBAUD (3ADEV)040ef8f2015-10-11 20:06:39 +0200160 "nfsroot=${serverip}:${nfs_root},v3,tcp\0" \
161 "bootargs_nand=setenv bootargs ${bootargs} " \
162 "ubi.mtd=6 rootfstype=ubifs root=ubi0:rootfs\0" \
163 "bootargs_ram=setenv bootargs ${bootargs} " \
164 "root=/dev/ram rw initrd=${ram_addr}\0" \
165 "bootargs_mtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
166 "bootcmd_sd=run bootargs_base bootargs_sd bootargs_mtd; " \
167 "fatload mmc 0:1 ${kernel_addr} ${kernel_file}; " \
168 "fatload mmc 0:1 ${fdt_addr} ${fdt_file}; " \
169 "bootz ${kernel_addr} - ${fdt_addr}\0" \
170 "bootcmd_net=run bootargs_base bootargs_net bootargs_mtd; " \
171 "tftpboot ${kernel_addr} ${tftpdir}${kernel_file}; " \
172 "tftpboot ${fdt_addr} ${tftpdir}${fdt_file}; " \
173 "bootz ${kernel_addr} - ${fdt_addr}\0" \
174 "bootcmd_nand=run bootargs_base bootargs_nand bootargs_mtd; " \
175 "nand read ${fdt_addr} dtb; " \
176 "nand read ${kernel_addr} kernel; " \
177 "bootz ${kernel_addr} - ${fdt_addr}\0" \
178 "bootcmd_ram=run bootargs_base bootargs_ram bootargs_mtd; " \
179 "nand read ${fdt_addr} dtb; " \
180 "nand read ${kernel_addr} kernel; " \
181 "nand read ${ram_addr} ramdisk; " \
182 "bootz ${kernel_addr} ${ram_addr} ${fdt_addr}\0" \
183 "update_bootloader_from_tftp=mtdparts default; " \
184 "nand read ${blsec_addr} bootloader; " \
185 "mw.b ${blimg_addr} 0xff 0x5FC00; " \
186 "if tftp ${blimg_addr} ${tftpdir}${blimg_file}; then " \
187 "nand erase.part bootloader; " \
188 "nand write ${blsec_addr} bootloader ${filesize}; fi\0" \
189 "update_kernel_from_sd=if fatload mmc 0:2 ${kernel_addr} " \
190 "${kernel_file}; " \
191 "then mtdparts default; " \
192 "nand erase.part kernel; " \
193 "nand write ${kernel_addr} kernel ${filesize}; " \
194 "if fatload mmc 0:2 ${fdt_addr} ${fdt_file}; then " \
195 "nand erase.part dtb; " \
196 "nand write ${fdt_addr} dtb ${filesize}; fi\0" \
197 "update_kernel_from_tftp=if tftp ${fdt_addr} ${tftpdir}${fdt_file}; " \
198 "then setenv fdtsize ${filesize}; " \
199 "if tftp ${kernel_addr} ${tftpdir}${kernel_file}; then " \
200 "mtdparts default; " \
201 "nand erase.part dtb; " \
202 "nand write ${fdt_addr} dtb ${fdtsize}; " \
203 "nand erase.part kernel; " \
204 "nand write ${kernel_addr} kernel ${filesize}; fi; fi\0" \
205 "update_rootfs_from_tftp=if tftp ${sys_addr} ${tftpdir}${filesys}; " \
206 "then mtdparts default; " \
207 "nand erase.part root; " \
208 "ubi part root; " \
209 "ubi create rootfs; " \
210 "ubi write ${sys_addr} rootfs ${filesize}; fi\0" \
211 "update_ramdisk_from_tftp=if tftp ${ram_addr} ${tftpdir}${ram_file}; " \
212 "then mtdparts default; " \
213 "nand erase.part ramdisk; " \
214 "nand write ${ram_addr} ramdisk ${filesize}; fi\0"
Albert ARIBAUD \(3ADEV\)931a1d22015-09-21 22:43:39 +0200215
Albert ARIBAUD \(3ADEV\)931a1d22015-09-21 22:43:39 +0200216/* Miscellaneous configurable options */
217#define CONFIG_SYS_LONGHELP /* undef to save memory */
218#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
219#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
220#define CONFIG_AUTO_COMPLETE
221#define CONFIG_CMDLINE_EDITING
222#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
223#define CONFIG_SYS_PBSIZE \
224 (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
225#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
226#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
227
228#define CONFIG_CMD_MEMTEST
229#define CONFIG_SYS_MEMTEST_START 0x80010000
230#define CONFIG_SYS_MEMTEST_END 0x87C00000
231
232#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
233
234/*
235 * Stack sizes
236 * The stack sizes are set up in start.S using the settings below
237 */
238#define CONFIG_STACKSIZE (128 * 1024) /* regular stack */
239
240/* Physical memory map */
241#define CONFIG_NR_DRAM_BANKS 1
242#define PHYS_SDRAM (0x80000000)
243#define PHYS_SDRAM_SIZE (256 * 1024 * 1024)
244
245#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
246#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
247#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
248
249#define CONFIG_SYS_INIT_SP_OFFSET \
250 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
251#define CONFIG_SYS_INIT_SP_ADDR \
252 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
253
254/* FLASH and environment organization */
255#define CONFIG_SYS_NO_FLASH
256
257#ifdef CONFIG_ENV_IS_IN_MMC
258#define CONFIG_ENV_SIZE (8 * 1024)
259
260#define CONFIG_ENV_OFFSET (12 * 64 * 1024)
261#define CONFIG_SYS_MMC_ENV_DEV 0
262#endif
263
264#ifdef CONFIG_ENV_IS_IN_NAND
265#define CONFIG_ENV_SECT_SIZE (128 * 1024)
266#define CONFIG_ENV_SIZE (8 * 1024)
Albert ARIBAUD (3ADEV)040ef8f2015-10-11 20:06:39 +0200267#define CONFIG_ENV_OFFSET 0xA0000
Albert ARIBAUD \(3ADEV\)931a1d22015-09-21 22:43:39 +0200268#define CONFIG_ENV_SIZE_REDUND (8 * 1024)
Albert ARIBAUD (3ADEV)040ef8f2015-10-11 20:06:39 +0200269#define CONFIG_ENV_OFFSET_REDUND 0xC0000
Albert ARIBAUD \(3ADEV\)931a1d22015-09-21 22:43:39 +0200270#endif
271
272#define CONFIG_OF_LIBFDT
273#define CONFIG_CMD_BOOTZ
274
275#endif