blob: 3ff175c6ded81cd372025096afd54e3cd3ed5b2d [file] [log] [blame]
Ilya Yanok5fb17032010-07-07 20:16:13 +04001/*
2 * Copyright (C) 2009-2010 Freescale Semiconductor, Inc.
3 * Copyright (C) 2010 Ilya Yanok, Emcraft Systems, yanok@emcraft.com
4 *
5 *
6 * See file CREDITS for list of people who contributed to this
7 * project.
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22 * MA 02111-1307 USA
23 */
24
25#ifndef __CONFIG_H
26#define __CONFIG_H
27
28/*
29 * High Level Configuration Options
30 */
31#define CONFIG_E300 1 /* E300 family */
32#define CONFIG_MPC83xx 1 /* MPC83xx family */
33#define CONFIG_MPC8308 1 /* MPC8308 CPU specific */
34#define CONFIG_MPC8308RDB 1 /* MPC8308RDB board specific */
35
Wolfgang Denk2ae18242010-10-06 09:05:45 +020036#define CONFIG_SYS_TEXT_BASE 0xFE000000
37
Ilya Yanok5fb17032010-07-07 20:16:13 +040038#define CONFIG_MISC_INIT_R
39
40/*
41 * On-board devices
42 *
43 * TSEC1 is SoC TSEC
44 * TSEC2 is VSC switch
45 */
46#define CONFIG_TSEC1
47#define CONFIG_VSC7385_ENET
48
49/*
50 * System Clock Setup
51 */
52#define CONFIG_83XX_CLKIN 33333333 /* in Hz */
53#define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN
54
55/*
56 * Hardware Reset Configuration Word
57 * if CLKIN is 66.66MHz, then
58 * CSB = 133MHz, DDRC = 266MHz, LBC = 133MHz
59 * We choose the A type silicon as default, so the core is 400Mhz.
60 */
61#define CONFIG_SYS_HRCW_LOW (\
62 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
63 HRCWL_DDR_TO_SCB_CLK_2X1 |\
64 HRCWL_SVCOD_DIV_2 |\
65 HRCWL_CSB_TO_CLKIN_4X1 |\
66 HRCWL_CORE_TO_CSB_3X1)
67/*
68 * There are neither HRCWH_PCI_HOST nor HRCWH_PCI1_ARBITER_ENABLE bits
69 * in 8308's HRCWH according to the manual, but original Freescale's
70 * code has them and I've expirienced some problems using the board
71 * with BDI3000 attached when I've tried to set these bits to zero
72 * (UART doesn't work after the 'reset run' command).
73 */
74#define CONFIG_SYS_HRCW_HIGH (\
75 HRCWH_PCI_HOST |\
76 HRCWH_PCI1_ARBITER_ENABLE |\
77 HRCWH_CORE_ENABLE |\
78 HRCWH_FROM_0X00000100 |\
79 HRCWH_BOOTSEQ_DISABLE |\
80 HRCWH_SW_WATCHDOG_DISABLE |\
81 HRCWH_ROM_LOC_LOCAL_16BIT |\
82 HRCWH_RL_EXT_LEGACY |\
83 HRCWH_TSEC1M_IN_RGMII |\
84 HRCWH_TSEC2M_IN_RGMII |\
85 HRCWH_BIG_ENDIAN)
86
87/*
88 * System IO Config
89 */
Ilya Yanok65ea7582010-09-17 23:41:49 +020090#define CONFIG_SYS_SICRH (\
91 SICRH_ESDHC_A_SD |\
92 SICRH_ESDHC_B_SD |\
93 SICRH_ESDHC_C_SD |\
94 SICRH_GPIO_A_TSEC2 |\
95 SICRH_GPIO_B_TSEC2_GTX_CLK125 |\
96 SICRH_IEEE1588_A_GPIO |\
97 SICRH_USB |\
98 SICRH_GTM_GPIO |\
99 SICRH_IEEE1588_B_GPIO |\
100 SICRH_ETSEC2_CRS |\
101 SICRH_GPIOSEL_1 |\
102 SICRH_TMROBI_V3P3 |\
103 SICRH_TSOBI1_V2P5 |\
104 SICRH_TSOBI2_V2P5) /* 0x01b7d103 */
105#define CONFIG_SYS_SICRL (\
106 SICRL_SPI_PF0 |\
107 SICRL_UART_PF0 |\
108 SICRL_IRQ_PF0 |\
109 SICRL_I2C2_PF0 |\
110 SICRL_ETSEC1_GTX_CLK125) /* 0x00000040 */
Ilya Yanok5fb17032010-07-07 20:16:13 +0400111
112/*
113 * IMMR new address
114 */
115#define CONFIG_SYS_IMMR 0xE0000000
116
117/*
118 * SERDES
119 */
120#define CONFIG_FSL_SERDES
121#define CONFIG_FSL_SERDES1 0xe3000
122
123/*
124 * Arbiter Setup
125 */
126#define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth is 4 */
127#define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count is 4 */
128#define CONFIG_SYS_SPCR_TSECEP 3 /* eTSEC emergency priority is highest */
129
130/*
131 * DDR Setup
132 */
133#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */
134#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
135#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
136#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
137#define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \
138 | DDRCDR_PZ_LOZ \
139 | DDRCDR_NZ_LOZ \
140 | DDRCDR_ODT \
141 | DDRCDR_Q_DRN)
142 /* 0x7b880001 */
143/*
144 * Manually set up DDR parameters
145 * consist of two chips HY5PS12621BFP-C4 from HYNIX
146 */
147
148#define CONFIG_SYS_DDR_SIZE 128 /* MB */
149
150#define CONFIG_SYS_DDR_CS0_BNDS 0x00000007
151#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \
152 | 0x00010000 /* ODT_WR to CSn */ \
153 | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10)
154 /* 0x80010102 */
155#define CONFIG_SYS_DDR_TIMING_3 0x00000000
156#define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
157 | (0 << TIMING_CFG0_WRT_SHIFT) \
158 | (0 << TIMING_CFG0_RRT_SHIFT) \
159 | (0 << TIMING_CFG0_WWT_SHIFT) \
160 | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
161 | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
162 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
163 | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
164 /* 0x00220802 */
165#define CONFIG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) \
166 | (7 << TIMING_CFG1_ACTTOPRE_SHIFT) \
167 | (2 << TIMING_CFG1_ACTTORW_SHIFT) \
168 | (5 << TIMING_CFG1_CASLAT_SHIFT) \
169 | (6 << TIMING_CFG1_REFREC_SHIFT) \
170 | (2 << TIMING_CFG1_WRREC_SHIFT) \
171 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
172 | (2 << TIMING_CFG1_WRTORD_SHIFT))
173 /* 0x27256222 */
174#define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \
175 | (4 << TIMING_CFG2_CPO_SHIFT) \
176 | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
177 | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
178 | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
179 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
180 | (5 << TIMING_CFG2_FOUR_ACT_SHIFT))
181 /* 0x121048c5 */
182#define CONFIG_SYS_DDR_INTERVAL ((0x0360 << SDRAM_INTERVAL_REFINT_SHIFT) \
183 | (0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
184 /* 0x03600100 */
185#define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \
186 | SDRAM_CFG_SDRAM_TYPE_DDR2 \
187 | SDRAM_CFG_32_BE)
188 /* 0x43080000 */
189
190#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 /* 1 posted refresh */
191#define CONFIG_SYS_DDR_MODE ((0x0448 << SDRAM_MODE_ESD_SHIFT) \
192 | (0x0232 << SDRAM_MODE_SD_SHIFT))
193 /* ODT 150ohm CL=3, AL=1 on SDRAM */
194#define CONFIG_SYS_DDR_MODE2 0x00000000
195
196/*
197 * Memory test
198 */
199#define CONFIG_SYS_MEMTEST_START 0x00001000 /* memtest region */
200#define CONFIG_SYS_MEMTEST_END 0x07f00000
201
202/*
203 * The reserved memory
204 */
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200205#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
Ilya Yanok5fb17032010-07-07 20:16:13 +0400206
207#define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */
208#define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */
209
210/*
211 * Initial RAM Base Address Setup
212 */
213#define CONFIG_SYS_INIT_RAM_LOCK 1
214#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */
Wolfgang Denk553f0982010-10-26 13:32:32 +0200215#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */
Ilya Yanok5fb17032010-07-07 20:16:13 +0400216#define CONFIG_SYS_GBL_DATA_OFFSET \
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200217 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Ilya Yanok5fb17032010-07-07 20:16:13 +0400218
219/*
220 * Local Bus Configuration & Clock Setup
221 */
222#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
223#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2
224#define CONFIG_SYS_LBC_LBCR 0x00040000
225
226/*
227 * FLASH on the Local Bus
228 */
229#define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */
230#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
231#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
232
233#define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */
234#define CONFIG_SYS_FLASH_SIZE 8 /* FLASH size is 8M */
235#define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */
236
237/* Window base at flash base */
238#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
Ilya Yanok65ea7582010-09-17 23:41:49 +0200239#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_8MB)
Ilya Yanok5fb17032010-07-07 20:16:13 +0400240
241#define CONFIG_SYS_BR0_PRELIM (\
242 CONFIG_SYS_FLASH_BASE /* Flash Base address */ |\
243 (2 << BR_PS_SHIFT) /* 16 bit port size */ |\
244 BR_V) /* valid */
245#define CONFIG_SYS_OR0_PRELIM ((~(CONFIG_SYS_FLASH_SIZE - 1) << 20) \
246 | OR_UPM_XAM \
247 | OR_GPCM_CSNT \
248 | OR_GPCM_ACS_DIV2 \
249 | OR_GPCM_XACS \
250 | OR_GPCM_SCY_15 \
251 | OR_GPCM_TRLX \
252 | OR_GPCM_EHTR \
253 | OR_GPCM_EAD)
254
255#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
256/* 127 64KB sectors and 8 8KB top sectors per device */
257#define CONFIG_SYS_MAX_FLASH_SECT 135
258
259#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
260#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
261
262/*
263 * NAND Flash on the Local Bus
264 */
265#define CONFIG_SYS_NAND_BASE 0xE0600000 /* 0xE0600000 */
266#define CONFIG_SYS_BR1_PRELIM ( CONFIG_SYS_NAND_BASE \
267 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
268 | BR_PS_8 /* Port Size = 8 bit */ \
269 | BR_MS_FCM /* MSEL = FCM */ \
270 | BR_V ) /* valid */
271#define CONFIG_SYS_OR1_PRELIM ( 0xFFFF8000 /* length 32K */ \
272 | OR_FCM_CSCT \
273 | OR_FCM_CST \
274 | OR_FCM_CHT \
275 | OR_FCM_SCY_1 \
276 | OR_FCM_TRLX \
277 | OR_FCM_EHTR )
278 /* 0xFFFF8396 */
279
280#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_NAND_BASE
Ilya Yanok65ea7582010-09-17 23:41:49 +0200281#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_32KB)
Ilya Yanok5fb17032010-07-07 20:16:13 +0400282
283#ifdef CONFIG_VSC7385_ENET
284#define CONFIG_TSEC2
285#define CONFIG_SYS_VSC7385_BASE 0xF0000000
286#define CONFIG_SYS_BR2_PRELIM 0xf0000801 /* VSC7385 Base address */
287#define CONFIG_SYS_OR2_PRELIM 0xfffe09ff /* VSC7385, 128K bytes*/
288/* Access window base at VSC7385 base */
289#define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_VSC7385_BASE
290/* Access window size 128K */
Ilya Yanok65ea7582010-09-17 23:41:49 +0200291#define CONFIG_SYS_LBLAWAR2_PRELIM (LBLAWAR_EN | LBLAWAR_128KB)
Ilya Yanok5fb17032010-07-07 20:16:13 +0400292/* The flash address and size of the VSC7385 firmware image */
293#define CONFIG_VSC7385_IMAGE 0xFE7FE000
294#define CONFIG_VSC7385_IMAGE_SIZE 8192
295#endif
296/*
297 * Serial Port
298 */
299#define CONFIG_CONS_INDEX 1
Ilya Yanok5fb17032010-07-07 20:16:13 +0400300#define CONFIG_SYS_NS16550
301#define CONFIG_SYS_NS16550_SERIAL
302#define CONFIG_SYS_NS16550_REG_SIZE 1
303#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
304
305#define CONFIG_SYS_BAUDRATE_TABLE \
306 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
307
308#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500)
309#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600)
310
311/* Use the HUSH parser */
312#define CONFIG_SYS_HUSH_PARSER
313#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
314
315/* Pass open firmware flat tree */
316#define CONFIG_OF_LIBFDT 1
317#define CONFIG_OF_BOARD_SETUP 1
318#define CONFIG_OF_STDOUT_VIA_ALIAS 1
319
320/* I2C */
321#define CONFIG_HARD_I2C /* I2C with hardware support */
322#define CONFIG_FSL_I2C
323#define CONFIG_I2C_MULTI_BUS
324#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
325#define CONFIG_SYS_I2C_SLAVE 0x7F
326#define CONFIG_SYS_I2C_NOPROBES {{0x51}} /* Don't probe these addrs */
327#define CONFIG_SYS_I2C_OFFSET 0x3000
328#define CONFIG_SYS_I2C2_OFFSET 0x3100
329
330
331/*
332 * Board info - revision and where boot from
333 */
334#define CONFIG_SYS_I2C_PCF8574A_ADDR 0x39
335
336/*
337 * Config on-board RTC
338 */
339#define CONFIG_RTC_DS1337 /* ds1339 on board, use ds1337 rtc via i2c */
340#define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */
341
342/*
343 * General PCI
344 * Addresses are mapped 1-1.
345 */
346#define CONFIG_SYS_PCIE1_BASE 0xA0000000
347#define CONFIG_SYS_PCIE1_MEM_BASE 0xA0000000
348#define CONFIG_SYS_PCIE1_MEM_PHYS 0xA0000000
349#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000
350#define CONFIG_SYS_PCIE1_CFG_BASE 0xB0000000
351#define CONFIG_SYS_PCIE1_CFG_SIZE 0x01000000
352#define CONFIG_SYS_PCIE1_IO_BASE 0x00000000
353#define CONFIG_SYS_PCIE1_IO_PHYS 0xB1000000
354#define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000
355
Ilya Yanok65ea7582010-09-17 23:41:49 +0200356/* enable PCIE clock */
357#define CONFIG_SYS_SCCR_PCIEXP1CM 1
Ilya Yanok5fb17032010-07-07 20:16:13 +0400358
359#define CONFIG_PCI
360#define CONFIG_PCIE
361
362#define CONFIG_PCI_PNP /* do pci plug-and-play */
363
364#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
365#define CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES 1
366
367/*
368 * TSEC
369 */
370#define CONFIG_NET_MULTI
371#define CONFIG_TSEC_ENET /* TSEC ethernet support */
372#define CONFIG_SYS_TSEC1_OFFSET 0x24000
373#define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
374#define CONFIG_SYS_TSEC2_OFFSET 0x25000
375#define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET)
376
377/*
378 * TSEC ethernet configuration
379 */
380#define CONFIG_MII 1 /* MII PHY management */
381#define CONFIG_TSEC1_NAME "eTSEC0"
382#define CONFIG_TSEC2_NAME "eTSEC1"
383#define TSEC1_PHY_ADDR 2
384#define TSEC2_PHY_ADDR 1
385#define TSEC1_PHYIDX 0
386#define TSEC2_PHYIDX 0
387#define TSEC1_FLAGS TSEC_GIGABIT
388#define TSEC2_FLAGS TSEC_GIGABIT
389
390/* Options are: eTSEC[0-1] */
391#define CONFIG_ETHPRIME "eTSEC0"
392
393/*
394 * Environment
395 */
396#define CONFIG_ENV_IS_IN_FLASH 1
397#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \
398 CONFIG_SYS_MONITOR_LEN)
399#define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */
400#define CONFIG_ENV_SIZE 0x2000
401#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
402#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
403
404#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
405#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
406
407/*
408 * BOOTP options
409 */
410#define CONFIG_BOOTP_BOOTFILESIZE
411#define CONFIG_BOOTP_BOOTPATH
412#define CONFIG_BOOTP_GATEWAY
413#define CONFIG_BOOTP_HOSTNAME
414
415/*
416 * Command line configuration.
417 */
418#include <config_cmd_default.h>
419
420#define CONFIG_CMD_DATE
421#define CONFIG_CMD_DHCP
422#define CONFIG_CMD_I2C
423#define CONFIG_CMD_MII
424#define CONFIG_CMD_NET
425#define CONFIG_CMD_PCI
426#define CONFIG_CMD_PING
427
428#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
429
430/*
431 * Miscellaneous configurable options
432 */
433#define CONFIG_SYS_LONGHELP /* undef to save memory */
434#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
435#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
436
437#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
438
439/* Print Buffer Size */
440#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
441#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
442/* Boot Argument Buffer Size */
443#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
444#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
445
446/*
447 * For booting Linux, the board info and command line data
Ira W. Snyder9f530d52010-09-10 15:42:32 -0700448 * have to be in the first 256 MB of memory, since this is
Ilya Yanok5fb17032010-07-07 20:16:13 +0400449 * the maximum mapped by the Linux kernel during initialization.
450 */
Ira W. Snyder9f530d52010-09-10 15:42:32 -0700451#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */
Ilya Yanok5fb17032010-07-07 20:16:13 +0400452
453/*
454 * Core HID Setup
455 */
456#define CONFIG_SYS_HID0_INIT 0x000000000
457#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \
458 HID0_ENABLE_INSTRUCTION_CACHE | \
459 HID0_ENABLE_DYNAMIC_POWER_MANAGMENT)
460#define CONFIG_SYS_HID2 HID2_HBE
461
462/*
463 * MMU Setup
464 */
465
466/* DDR: cache cacheable */
467#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | \
468 BATL_MEMCOHERENCE)
469#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_128M | \
470 BATU_VS | BATU_VP)
471#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
472#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
473
474/* IMMRBAR, PCI IO and NAND: cache-inhibit and guarded */
475#define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR | BATL_PP_10 | \
476 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
477#define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR | BATU_BL_8M | BATU_VS | \
478 BATU_VP)
479#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
480#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
481
482/* FLASH: icache cacheable, but dcache-inhibit and guarded */
483#define CONFIG_SYS_IBAT2L (CONFIG_SYS_FLASH_BASE | BATL_PP_10 | \
484 BATL_MEMCOHERENCE)
485#define CONFIG_SYS_IBAT2U (CONFIG_SYS_FLASH_BASE | BATU_BL_8M | \
486 BATU_VS | BATU_VP)
487#define CONFIG_SYS_DBAT2L (CONFIG_SYS_FLASH_BASE | BATL_PP_10 | \
488 BATL_CACHEINHIBIT | \
489 BATL_GUARDEDSTORAGE)
490#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
491
492/* Stack in dcache: cacheable, no memory coherence */
493#define CONFIG_SYS_IBAT3L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10)
494#define CONFIG_SYS_IBAT3U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | \
495 BATU_VS | BATU_VP)
496#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
497#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
498
499/*
Ilya Yanok5fb17032010-07-07 20:16:13 +0400500 * Environment Configuration
501 */
502
503#define CONFIG_ENV_OVERWRITE
504
505#if defined(CONFIG_TSEC_ENET)
506#define CONFIG_HAS_ETH0
507#define CONFIG_HAS_ETH1
508#endif
509
510#define CONFIG_BAUDRATE 115200
511
512#define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */
513
514#define CONFIG_BOOTDELAY 5 /* -1 disables auto-boot */
515
516#define xstr(s) str(s)
517#define str(s) #s
518
519#define CONFIG_EXTRA_ENV_SETTINGS \
520 "netdev=eth0\0" \
521 "consoledev=ttyS0\0" \
522 "nfsargs=setenv bootargs root=/dev/nfs rw " \
523 "nfsroot=${serverip}:${rootpath}\0" \
524 "ramargs=setenv bootargs root=/dev/ram rw\0" \
525 "addip=setenv bootargs ${bootargs} " \
526 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
527 ":${hostname}:${netdev}:off panic=1\0" \
528 "addtty=setenv bootargs ${bootargs}" \
529 " console=${consoledev},${baudrate}\0" \
530 "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
531 "addmisc=setenv bootargs ${bootargs}\0" \
532 "kernel_addr=FE080000\0" \
533 "fdt_addr=FE280000\0" \
534 "ramdisk_addr=FE290000\0" \
535 "u-boot=mpc8308rdb/u-boot.bin\0" \
536 "kernel_addr_r=1000000\0" \
537 "fdt_addr_r=C00000\0" \
538 "hostname=mpc8308rdb\0" \
539 "bootfile=mpc8308rdb/uImage\0" \
540 "fdtfile=mpc8308rdb/mpc8308rdb.dtb\0" \
541 "rootpath=/opt/eldk-4.2/ppc_6xx\0" \
542 "flash_self=run ramargs addip addtty addmtd addmisc;" \
543 "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \
544 "flash_nfs=run nfsargs addip addtty addmtd addmisc;" \
545 "bootm ${kernel_addr} - ${fdt_addr}\0" \
546 "net_nfs=tftp ${kernel_addr_r} ${bootfile};" \
547 "tftp ${fdt_addr_r} ${fdtfile};" \
548 "run nfsargs addip addtty addmtd addmisc;" \
549 "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \
550 "bootcmd=run flash_self\0" \
551 "load=tftp ${loadaddr} ${u-boot}\0" \
552 "update=protect off " xstr(CONFIG_SYS_MONITOR_BASE) \
553 " +${filesize};era " xstr(CONFIG_SYS_MONITOR_BASE) \
554 " +${filesize};cp.b ${fileaddr} " \
555 xstr(CONFIG_SYS_MONITOR_BASE) " ${filesize}\0" \
556 "upd=run load update\0" \
557
558#endif /* __CONFIG_H */