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Matthias Fuchs1a3ac862008-01-17 10:53:08 +01001/*
2 * (C) Copyright 2008
3 * Matthias Fuchs, esd gmbh, matthias.fuchs@esd-electronics.com
4 *
5 * based on the Sequoia board configuration by
6 * Stefan Roese, Jacqueline Pira-Ferriol and Alain Saurel
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/*
25 **********************************************************************
26 * DU440.h - configuration for esd's DU440 board (Power PC440EPx)
27 **********************************************************************
28 */
29#ifndef __CONFIG_H
30#define __CONFIG_H
31
32/*
33 * High Level Configuration Options
34 */
35#define CONFIG_DU440 1 /* Board is esd DU440 */
36#define CONFIG_440EPX 1 /* Specific PPC440EPx */
37#define CONFIG_4xx 1 /* ... PPC4xx family */
38#define CONFIG_SYS_CLK_FREQ 33333400 /* external freq to pll */
39
Wolfgang Denk2ae18242010-10-06 09:05:45 +020040#ifndef CONFIG_SYS_TEXT_BASE
41#define CONFIG_SYS_TEXT_BASE 0xFFFA0000
42#endif
43
Matthias Fuchs1a3ac862008-01-17 10:53:08 +010044#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
45#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */
46#define CONFIG_LAST_STAGE_INIT 1 /* last_stage_init */
47
48/*
49 * Base addresses -- Note these are effective addresses where the
50 * actual resources get mapped (not physical addresses)
51 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020052#define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Monitor */
53#define CONFIG_SYS_MALLOC_LEN (8 << 20) /* Reserve 8 MB for malloc() */
Matthias Fuchs1a3ac862008-01-17 10:53:08 +010054
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020055#define CONFIG_SYS_BOOT_BASE_ADDR 0xf0000000
56#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* _must_ be 0 */
57#define CONFIG_SYS_FLASH_BASE 0xfc000000 /* start of FLASH */
Wolfgang Denk14d0a022010-10-07 21:51:12 +020058#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020059#define CONFIG_SYS_NAND0_ADDR 0xd0000000 /* NAND Flash */
60#define CONFIG_SYS_NAND1_ADDR 0xd0100000 /* NAND Flash */
61#define CONFIG_SYS_OCM_BASE 0xe0010000 /* ocm */
62#define CONFIG_SYS_PCI_BASE 0xe0000000 /* Internal PCI regs */
63#define CONFIG_SYS_PCI_MEMBASE 0x80000000 /* mapped pci memory */
64#define CONFIG_SYS_PCI_MEMBASE1 CONFIG_SYS_PCI_MEMBASE + 0x10000000
65#define CONFIG_SYS_PCI_MEMBASE2 CONFIG_SYS_PCI_MEMBASE1 + 0x10000000
66#define CONFIG_SYS_PCI_MEMBASE3 CONFIG_SYS_PCI_MEMBASE2 + 0x10000000
Stefan Roese10954932009-11-12 12:00:49 +010067#define CONFIG_SYS_PCI_IOBASE 0xe8000000
68#define CONFIG_SYS_PCI_SUBSYS_VENDORID PCI_VENDOR_ID_ESDGMBH
69#define CONFIG_SYS_PCI_SUBSYS_ID 0x0444 /* device ID for DU440 */
Matthias Fuchs1a3ac862008-01-17 10:53:08 +010070
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020071#define CONFIG_SYS_USB2D0_BASE 0xe0000100
72#define CONFIG_SYS_USB_DEVICE 0xe0000000
73#define CONFIG_SYS_USB_HOST 0xe0000400
Matthias Fuchs1a3ac862008-01-17 10:53:08 +010074
75/*
76 * Initial RAM & stack pointer
77 */
78/* 440EPx/440GRx have 16KB of internal SRAM, so no need for D-Cache */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020079#define CONFIG_SYS_INIT_RAM_OCM 1 /* OCM as init ram */
80#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_BASE /* OCM */
Matthias Fuchs1a3ac862008-01-17 10:53:08 +010081
Wolfgang Denk553f0982010-10-26 13:32:32 +020082#define CONFIG_SYS_INIT_RAM_SIZE (4 << 10)
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +020083#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020084#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
Matthias Fuchs1a3ac862008-01-17 10:53:08 +010085
86/*
87 * Serial Port
88 */
Stefan Roese550650d2010-09-20 16:05:31 +020089#define CONFIG_CONS_INDEX 1 /* Use UART0 */
90#define CONFIG_SYS_NS16550
91#define CONFIG_SYS_NS16550_SERIAL
92#define CONFIG_SYS_NS16550_REG_SIZE 1
93#define CONFIG_SYS_NS16550_CLK get_serial_clock()
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020094#undef CONFIG_SYS_EXT_SERIAL_CLOCK
Matthias Fuchs1a3ac862008-01-17 10:53:08 +010095#define CONFIG_BAUDRATE 115200
96#define CONFIG_SERIAL_MULTI 1
Matthias Fuchs1a3ac862008-01-17 10:53:08 +010097
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020098#define CONFIG_SYS_BAUDRATE_TABLE \
Matthias Fuchs1a3ac862008-01-17 10:53:08 +010099 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
100
101/*
102 * Video Port
103 */
104#define CONFIG_VIDEO
105#define CONFIG_VIDEO_SMI_LYNXEM
106#define CONFIG_CFB_CONSOLE
107#define CONFIG_VIDEO_LOGO
108#define CONFIG_VGA_AS_SINGLE_DEVICE
109#define CONFIG_SPLASH_SCREEN
110#define CONFIG_SPLASH_SCREEN_ALIGN
111#define CONFIG_VIDEO_BMP_GZIP /* gzip compressed bmp images */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200112#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (4 << 20) /* for decompressed img */
113#define CONFIG_SYS_DEFAULT_VIDEO_MODE 0x31a /* 1280x1024,16bpp */
114#define CONFIG_SYS_CONSOLE_IS_IN_ENV
115#define CONFIG_SYS_ISA_IO CONFIG_SYS_PCI_IOBASE
Matthias Fuchs1a3ac862008-01-17 10:53:08 +0100116
117/*
118 * Environment
119 */
Jean-Christophe PLAGNIOL-VILLARDbb1f8b42008-09-05 09:19:30 +0200120#define CONFIG_ENV_IS_IN_EEPROM 1 /* use FLASH for environment vars */
Matthias Fuchs1a3ac862008-01-17 10:53:08 +0100121
122/*
123 * FLASH related
124 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200125#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +0200126#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
Matthias Fuchs1a3ac862008-01-17 10:53:08 +0100127
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200128#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
Matthias Fuchs1a3ac862008-01-17 10:53:08 +0100129
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200130#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
131#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max number of sectors on one chip */
Matthias Fuchs1a3ac862008-01-17 10:53:08 +0100132
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200133#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
134#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
Matthias Fuchs1a3ac862008-01-17 10:53:08 +0100135
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200136#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
Matthias Fuchs1a3ac862008-01-17 10:53:08 +0100137/* CFI_FLASH_PROTECTION make flash_protect hang sometimes -> disabled */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200138#define CONFIG_SYS_FLASH_PROTECTION 1 /* use hardware flash protection */
Matthias Fuchs1a3ac862008-01-17 10:53:08 +0100139
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200140#define CONFIG_SYS_FLASH_EMPTY_INFO
141#define CONFIG_SYS_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash */
Matthias Fuchs1a3ac862008-01-17 10:53:08 +0100142
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200143#ifdef CONFIG_ENV_IS_IN_FLASH
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200144#define CONFIG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200145#define CONFIG_ENV_ADDR ((-CONFIG_SYS_MONITOR_LEN)-CONFIG_ENV_SECT_SIZE)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200146#define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
Matthias Fuchs1a3ac862008-01-17 10:53:08 +0100147
148/* Address and size of Redundant Environment Sector */
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200149#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
150#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
Matthias Fuchs1a3ac862008-01-17 10:53:08 +0100151#endif
152
Jean-Christophe PLAGNIOL-VILLARDbb1f8b42008-09-05 09:19:30 +0200153#ifdef CONFIG_ENV_IS_IN_EEPROM
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200154#define CONFIG_ENV_OFFSET 0 /* environment starts at */
Matthias Fuchs1a3ac862008-01-17 10:53:08 +0100155 /* the beginning of the EEPROM */
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200156#define CONFIG_ENV_SIZE 0x1000 /* 4096 bytes may be used for env vars */
Matthias Fuchs1a3ac862008-01-17 10:53:08 +0100157#endif
158
159/*
160 * DDR SDRAM
161 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200162#define CONFIG_SYS_MBYTES_SDRAM (1024) /* 512 MiB TODO: remove */
Matthias Fuchs1a3ac862008-01-17 10:53:08 +0100163#define CONFIG_DDR_DATA_EYE /* use DDR2 optimization */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200164#define CONFIG_SYS_MEM_TOP_HIDE (4 << 10) /* don't use last 4kbytes */
Stefan Roese02e38922008-03-31 12:20:48 +0200165 /* 440EPx errata CHIP 11 */
Matthias Fuchs1a3ac862008-01-17 10:53:08 +0100166#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for setup */
Matthias Fuchs1a3ac862008-01-17 10:53:08 +0100167#define CONFIG_DDR_ECC /* Use ECC when available */
168#define SPD_EEPROM_ADDRESS {0x50}
169#define CONFIG_PROG_SDRAM_TLB
170
171/*
172 * I2C
173 */
174#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
175#undef CONFIG_SOFT_I2C /* I2C bit-banged */
Stefan Roesed0b0dca2010-04-01 14:37:24 +0200176#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200177#define CONFIG_SYS_I2C_SPEED 100000 /* I2C speed and slave address */
178#define CONFIG_SYS_I2C_SLAVE 0x7F
Matthias Fuchs1a3ac862008-01-17 10:53:08 +0100179#define CONFIG_I2C_MULTI_BUS 1
180
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200181#define CONFIG_SYS_SPD_BUS_NUM 0
Matthias Fuchs1a3ac862008-01-17 10:53:08 +0100182#define IIC1_MCP3021_ADDR 0x4d
183#define IIC1_USB2507_ADDR 0x2c
184#ifdef CONFIG_I2C_MULTI_BUS
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200185#define CONFIG_SYS_I2C_NOPROBES {{1, IIC1_USB2507_ADDR}}
Matthias Fuchs1a3ac862008-01-17 10:53:08 +0100186#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200187#define CONFIG_SYS_I2C_MULTI_EEPROMS
188#define CONFIG_SYS_I2C_EEPROM_ADDR 0x54
189#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
190#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5
191#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
192#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x01
Matthias Fuchs1a3ac862008-01-17 10:53:08 +0100193
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200194#define CONFIG_SYS_EEPROM_WREN 1
195#define CONFIG_SYS_I2C_BOOT_EEPROM_ADDR 0x52
Matthias Fuchs1a3ac862008-01-17 10:53:08 +0100196
197/*
198 * standard dtt sensor configuration - bottom bit will determine local or
199 * remote sensor of the TMP401
200 */
201#define CONFIG_DTT_SENSORS { 0, 1 }
202
203/*
204 * The PMC440 uses a TI TMP401 temperature sensor. This part
205 * is basically compatible to the ADM1021 that is supported
206 * by U-Boot.
207 *
208 * - i2c addr 0x4c
209 * - conversion rate 0x02 = 0.25 conversions/second
210 * - ALERT ouput disabled
211 * - local temp sensor enabled, min set to 0 deg, max set to 70 deg
212 * - remote temp sensor enabled, min set to 0 deg, max set to 70 deg
213 */
214#define CONFIG_DTT_ADM1021
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200215#define CONFIG_SYS_DTT_ADM1021 { { 0x4c, 0x02, 0, 1, 70, 0, 1, 70, 0} }
Matthias Fuchs1a3ac862008-01-17 10:53:08 +0100216
217/*
218 * RTC stuff
219 */
220#define CONFIG_RTC_DS1338
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200221#define CONFIG_SYS_I2C_RTC_ADDR 0x68
Matthias Fuchs1a3ac862008-01-17 10:53:08 +0100222
223#undef CONFIG_BOOTARGS
224
225#define CONFIG_EXTRA_ENV_SETTINGS \
226 "netdev=eth0\0" \
227 "ethrotate=no\0" \
228 "hostname=du440\0" \
229 "nfsargs=setenv bootargs root=/dev/nfs rw " \
230 "nfsroot=${serverip}:${rootpath}\0" \
231 "ramargs=setenv bootargs root=/dev/ram rw\0" \
232 "addip=setenv bootargs ${bootargs} " \
233 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
234 ":${hostname}:${netdev}:off panic=1\0" \
235 "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
236 "flash_self=run ramargs addip addtty optargs;" \
237 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
238 "net_nfs=tftp 200000 ${img};run nfsargs addip addtty optargs;" \
239 "bootm\0" \
240 "rootpath=/tftpboot/du440/target_root_du440\0" \
241 "img=/tftpboot/du440/uImage\0" \
242 "kernel_addr=FFC00000\0" \
243 "ramdisk_addr=FFE00000\0" \
244 "initrd_high=30000000\0" \
245 "load=tftp 100000 /tftpboot/du440/u-boot.bin\0" \
246 "update=protect off FFFA0000 FFFFFFFF;era FFFA0000 FFFFFFFF;" \
247 "cp.b 100000 FFFA0000 60000\0" \
248 ""
Matthias Fuchs1a3ac862008-01-17 10:53:08 +0100249
250#define CONFIG_PREBOOT /* enable preboot variable */
251
252#define CONFIG_BOOTDELAY 3 /* autoboot after 5 seconds */
253
254#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200255#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
Matthias Fuchs1a3ac862008-01-17 10:53:08 +0100256
257#ifndef __ASSEMBLY__
258int du440_phy_addr(int devnum);
259#endif
260
Ben Warren96e21f82008-10-27 23:50:15 -0700261#define CONFIG_PPC4xx_EMAC
Matthias Fuchs1a3ac862008-01-17 10:53:08 +0100262#define CONFIG_IBM_EMAC4_V4 1
263#define CONFIG_MII 1 /* MII PHY management */
264#define CONFIG_PHY_ADDR du440_phy_addr(0) /* PHY address */
265
266#define CONFIG_PHY_RESET 1 /* reset phy upon startup */
Matthias Fuchs7c91f512008-03-30 18:01:15 +0200267#undef CONFIG_PHY_GIGE /* no GbE detection */
Matthias Fuchs1a3ac862008-01-17 10:53:08 +0100268
269#define CONFIG_HAS_ETH0
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200270#define CONFIG_SYS_RX_ETH_BUFFER 128
Matthias Fuchs1a3ac862008-01-17 10:53:08 +0100271
Matthias Fuchs1a3ac862008-01-17 10:53:08 +0100272#define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */
273#define CONFIG_PHY1_ADDR du440_phy_addr(1)
274
275/*
276 * USB
277 */
278#define CONFIG_USB_OHCI_NEW
279#define CONFIG_USB_STORAGE
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200280#define CONFIG_SYS_OHCI_BE_CONTROLLER
Matthias Fuchs1a3ac862008-01-17 10:53:08 +0100281
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200282#define CONFIG_SYS_USB_OHCI_CPU_INIT 1
283#define CONFIG_SYS_USB_OHCI_REGS_BASE CONFIG_SYS_USB_HOST
284#define CONFIG_SYS_USB_OHCI_SLOT_NAME "du440"
285#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15
Matthias Fuchs1a3ac862008-01-17 10:53:08 +0100286
287/* Comment this out to enable USB 1.1 device */
288#define USB_2_0_DEVICE
289
290/* Partitions */
291#define CONFIG_MAC_PARTITION
292#define CONFIG_DOS_PARTITION
293#define CONFIG_ISO_PARTITION
294
295#include <config_cmd_default.h>
296
Matthias Fuchs1a3ac862008-01-17 10:53:08 +0100297#define CONFIG_CMD_ASKENV
Wolfgang Denk74de7ae2009-04-01 23:34:12 +0200298#define CONFIG_CMD_BMP
299#define CONFIG_CMD_BSP
300#define CONFIG_CMD_DATE
Matthias Fuchs1a3ac862008-01-17 10:53:08 +0100301#define CONFIG_CMD_DHCP
Matthias Fuchs1a3ac862008-01-17 10:53:08 +0100302#define CONFIG_CMD_DIAG
Wolfgang Denk74de7ae2009-04-01 23:34:12 +0200303#define CONFIG_CMD_DTT
Matthias Fuchs1a3ac862008-01-17 10:53:08 +0100304#define CONFIG_CMD_EEPROM
305#define CONFIG_CMD_ELF
306#define CONFIG_CMD_FAT
307#define CONFIG_CMD_I2C
308#define CONFIG_CMD_IRQ
309#define CONFIG_CMD_MII
310#define CONFIG_CMD_NAND
311#define CONFIG_CMD_NET
312#define CONFIG_CMD_NFS
313#define CONFIG_CMD_PCI
314#define CONFIG_CMD_PING
Matthias Fuchs1a3ac862008-01-17 10:53:08 +0100315#define CONFIG_CMD_REGINFO
316#define CONFIG_CMD_SDRAM
Wolfgang Denk74de7ae2009-04-01 23:34:12 +0200317#define CONFIG_CMD_SOURCE
318#define CONFIG_CMD_USB
Matthias Fuchs1a3ac862008-01-17 10:53:08 +0100319
320#define CONFIG_SUPPORT_VFAT
321
322/*
323 * Miscellaneous configurable options
324 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200325#define CONFIG_SYS_LONGHELP /* undef to save memory */
326#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
Matthias Fuchs1a3ac862008-01-17 10:53:08 +0100327#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200328#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
Matthias Fuchs1a3ac862008-01-17 10:53:08 +0100329#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200330#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
Matthias Fuchs1a3ac862008-01-17 10:53:08 +0100331#endif
332/* Print Buffer Size */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200333#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
334#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
335#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
Matthias Fuchs1a3ac862008-01-17 10:53:08 +0100336
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200337#define CONFIG_SYS_MEMTEST_START 0x00400000 /* memtest works on */
338#define CONFIG_SYS_MEMTEST_END 0x3f000000 /* 4 ... < 1GB DRAM */
Matthias Fuchs1a3ac862008-01-17 10:53:08 +0100339
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200340#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
341#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */
Matthias Fuchs1a3ac862008-01-17 10:53:08 +0100342
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200343#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
Matthias Fuchs1a3ac862008-01-17 10:53:08 +0100344
345#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
346#define CONFIG_LOOPW 1 /* enable loopw command */
347#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */
348#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
349#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
350
Wolfgang Denkc37207d2008-07-16 16:38:59 +0200351#define CONFIG_AUTOBOOT_KEYED 1
352#define CONFIG_AUTOBOOT_PROMPT \
353 "Press SPACE to abort autoboot in %d seconds\n", bootdelay
Matthias Fuchs1a3ac862008-01-17 10:53:08 +0100354#define CONFIG_AUTOBOOT_DELAY_STR "d"
355#define CONFIG_AUTOBOOT_STOP_STR " "
356
357/*
358 * PCI stuff
359 */
360#define CONFIG_PCI /* include pci support */
361#define CONFIG_PCI_PNP /* do (not) pci plug-and-play */
362#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200363#define CONFIG_SYS_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CONFIG_SYS_PCI_MEMBASE*/
Matthias Fuchs1a3ac862008-01-17 10:53:08 +0100364
365/* Board-specific PCI */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200366#define CONFIG_SYS_PCI_TARGET_INIT
367#define CONFIG_SYS_PCI_MASTER_INIT
Matthias Fuchs1a3ac862008-01-17 10:53:08 +0100368
369/*
370 * For booting Linux, the board info and command line data
371 * have to be in the first 8 MB of memory, since this is
372 * the maximum mapped by the Linux kernel during initialization.
373 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200374#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
Matthias Fuchs1a3ac862008-01-17 10:53:08 +0100375
376/*
377 * External Bus Controller (EBC) Setup
378 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200379#define CONFIG_SYS_FLASH CONFIG_SYS_FLASH_BASE
Matthias Fuchs1a3ac862008-01-17 10:53:08 +0100380
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200381#define CONFIG_SYS_CPLD_BASE 0xC0000000
382#define CONFIG_SYS_CPLD_RANGE 0x00000010
383#define CONFIG_SYS_DUMEM_BASE 0xC0100000
384#define CONFIG_SYS_DUMEM_RANGE 0x00100000
385#define CONFIG_SYS_DUIO_BASE 0xC0200000
386#define CONFIG_SYS_DUIO_RANGE 0x00010000
Matthias Fuchs1a3ac862008-01-17 10:53:08 +0100387
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200388#define CONFIG_SYS_NAND0_CS 2 /* NAND chip connected to CSx */
389#define CONFIG_SYS_NAND1_CS 3 /* NAND chip connected to CSx */
Matthias Fuchs1a3ac862008-01-17 10:53:08 +0100390/* Memory Bank 0 (NOR-FLASH) initialization */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200391#define CONFIG_SYS_EBC_PB0AP 0x04017200
392#define CONFIG_SYS_EBC_PB0CR (CONFIG_SYS_FLASH_BASE | 0xda000)
Matthias Fuchs1a3ac862008-01-17 10:53:08 +0100393
394/* Memory Bank 1 (CPLD, 16 bytes needed, but 1MB is minimum) */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200395#define CONFIG_SYS_EBC_PB1AP 0x018003c0
396#define CONFIG_SYS_EBC_PB1CR (CONFIG_SYS_CPLD_BASE | 0x18000)
Matthias Fuchs1a3ac862008-01-17 10:53:08 +0100397
398/* Memory Bank 2 (NAND-FLASH) initialization */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200399#define CONFIG_SYS_EBC_PB2AP 0x018003c0
400#define CONFIG_SYS_EBC_PB2CR (CONFIG_SYS_NAND0_ADDR | 0x1c000)
Matthias Fuchs1a3ac862008-01-17 10:53:08 +0100401
402/* Memory Bank 3 (NAND-FLASH) initialization */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200403#define CONFIG_SYS_EBC_PB3AP 0x018003c0
404#define CONFIG_SYS_EBC_PB3CR (CONFIG_SYS_NAND1_ADDR | 0x1c000)
Matthias Fuchs1a3ac862008-01-17 10:53:08 +0100405
406/* Memory Bank 4 (DUMEM, 1MB) initialization */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200407#define CONFIG_SYS_EBC_PB4AP 0x018053c0
408#define CONFIG_SYS_EBC_PB4CR (CONFIG_SYS_DUMEM_BASE | 0x18000)
Matthias Fuchs1a3ac862008-01-17 10:53:08 +0100409
410/* Memory Bank 5 (DUIO, 64KB needed, but 1MB is minimum) */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200411#define CONFIG_SYS_EBC_PB5AP 0x018053c0
412#define CONFIG_SYS_EBC_PB5CR (CONFIG_SYS_DUIO_BASE | 0x18000)
Matthias Fuchs1a3ac862008-01-17 10:53:08 +0100413
414/*
415 * NAND FLASH
416 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200417#define CONFIG_SYS_MAX_NAND_DEVICE 2
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200418#define CONFIG_SYS_NAND_SELECT_DEVICE 1 /* nand driver supports mutipl. chips */
419#define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND0_ADDR + CONFIG_SYS_NAND0_CS, \
420 CONFIG_SYS_NAND1_ADDR + CONFIG_SYS_NAND1_CS}
Matthias Fuchs1a3ac862008-01-17 10:53:08 +0100421
Matthias Fuchs1a3ac862008-01-17 10:53:08 +0100422#if defined(CONFIG_CMD_KGDB)
423#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
424#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
425#endif
426
Wolfgang Denk74de7ae2009-04-01 23:34:12 +0200427#define CONFIG_SOURCE 1
Matthias Fuchs1a3ac862008-01-17 10:53:08 +0100428
Matthias Fuchs35dd0252008-10-07 13:13:07 +0200429#define CONFIG_OF_LIBFDT
430#define CONFIG_OF_BOARD_SETUP
431
Matthias Fuchs1a3ac862008-01-17 10:53:08 +0100432#endif /* __CONFIG_H */