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Tom Rini83d290c2018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Jin Zhengxiong4782ac82006-08-23 19:10:44 +08002/*
Kumar Gala4c2e3da2009-07-28 21:49:52 -05003 * Copyright (C) Freescale Semiconductor, Inc. 2006.
Jin Zhengxiong4782ac82006-08-23 19:10:44 +08004 * Author: Jason Jin<Jason.jin@freescale.com>
5 * Zhang Wei<wei.zhang@freescale.com>
Jin Zhengxiong4782ac82006-08-23 19:10:44 +08006 */
7#ifndef _AHCI_H_
8#define _AHCI_H_
9
Rob Herring942e3142011-07-06 16:13:36 +000010#include <pci.h>
11
Jin Zhengxiong4782ac82006-08-23 19:10:44 +080012#define AHCI_PCI_BAR 0x24
13#define AHCI_MAX_SG 56 /* hardware max is 64K */
14#define AHCI_CMD_SLOT_SZ 32
Stefano Babic9f472e62012-02-22 00:24:39 +000015#define AHCI_MAX_CMD_SLOT 32
Jin Zhengxiong4782ac82006-08-23 19:10:44 +080016#define AHCI_RX_FIS_SZ 256
17#define AHCI_CMD_TBL_HDR 0x80
18#define AHCI_CMD_TBL_CDB 0x40
19#define AHCI_CMD_TBL_SZ AHCI_CMD_TBL_HDR + (AHCI_MAX_SG * 16)
Stefano Babic9f472e62012-02-22 00:24:39 +000020#define AHCI_PORT_PRIV_DMA_SZ (AHCI_CMD_SLOT_SZ * AHCI_MAX_CMD_SLOT + \
21 AHCI_CMD_TBL_SZ + AHCI_RX_FIS_SZ)
Jin Zhengxiong4782ac82006-08-23 19:10:44 +080022#define AHCI_CMD_ATAPI (1 << 5)
23#define AHCI_CMD_WRITE (1 << 6)
24#define AHCI_CMD_PREFETCH (1 << 7)
25#define AHCI_CMD_RESET (1 << 8)
26#define AHCI_CMD_CLR_BUSY (1 << 10)
27
28#define RX_FIS_D2H_REG 0x40 /* offset of D2H Register FIS data */
29
30/* Global controller registers */
31#define HOST_CAP 0x00 /* host capabilities */
32#define HOST_CTL 0x04 /* global host control */
33#define HOST_IRQ_STAT 0x08 /* interrupt status */
34#define HOST_PORTS_IMPL 0x0c /* bitmap of implemented ports */
35#define HOST_VERSION 0x10 /* AHCI spec. version compliancy */
Stefan Reinauer4e422bc2012-10-29 05:23:51 +000036#define HOST_CAP2 0x24 /* host capabilities, extended */
Jin Zhengxiong4782ac82006-08-23 19:10:44 +080037
38/* HOST_CTL bits */
39#define HOST_RESET (1 << 0) /* reset controller; self-clear */
40#define HOST_IRQ_EN (1 << 1) /* global IRQ enable */
41#define HOST_AHCI_EN (1 << 31) /* AHCI enabled */
42
43/* Registers for each SATA port */
44#define PORT_LST_ADDR 0x00 /* command list DMA addr */
45#define PORT_LST_ADDR_HI 0x04 /* command list DMA addr hi */
46#define PORT_FIS_ADDR 0x08 /* FIS rx buf addr */
47#define PORT_FIS_ADDR_HI 0x0c /* FIS rx buf addr hi */
48#define PORT_IRQ_STAT 0x10 /* interrupt status */
49#define PORT_IRQ_MASK 0x14 /* interrupt enable/disable mask */
50#define PORT_CMD 0x18 /* port command */
51#define PORT_TFDATA 0x20 /* taskfile data */
52#define PORT_SIG 0x24 /* device TF signature */
53#define PORT_CMD_ISSUE 0x38 /* command issue */
54#define PORT_SCR 0x28 /* SATA phy register block */
55#define PORT_SCR_STAT 0x28 /* SATA phy register: SStatus */
56#define PORT_SCR_CTL 0x2c /* SATA phy register: SControl */
57#define PORT_SCR_ERR 0x30 /* SATA phy register: SError */
58#define PORT_SCR_ACT 0x34 /* SATA phy register: SActive */
59
Ian Campbella6e50a82014-07-18 20:38:41 +010060#ifdef CONFIG_SUNXI_AHCI
61#define PORT_P0DMACR 0x70 /* SUNXI specific "DMA register" */
62#endif
63
Jin Zhengxiong4782ac82006-08-23 19:10:44 +080064/* PORT_IRQ_{STAT,MASK} bits */
65#define PORT_IRQ_COLD_PRES (1 << 31) /* cold presence detect */
66#define PORT_IRQ_TF_ERR (1 << 30) /* task file error */
67#define PORT_IRQ_HBUS_ERR (1 << 29) /* host bus fatal error */
68#define PORT_IRQ_HBUS_DATA_ERR (1 << 28) /* host bus data error */
69#define PORT_IRQ_IF_ERR (1 << 27) /* interface fatal error */
70#define PORT_IRQ_IF_NONFATAL (1 << 26) /* interface non-fatal error */
71#define PORT_IRQ_OVERFLOW (1 << 24) /* xfer exhausted available S/G */
72#define PORT_IRQ_BAD_PMP (1 << 23) /* incorrect port multiplier */
73
74#define PORT_IRQ_PHYRDY (1 << 22) /* PhyRdy changed */
75#define PORT_IRQ_DEV_ILCK (1 << 7) /* device interlock */
76#define PORT_IRQ_CONNECT (1 << 6) /* port connect change status */
77#define PORT_IRQ_SG_DONE (1 << 5) /* descriptor processed */
78#define PORT_IRQ_UNK_FIS (1 << 4) /* unknown FIS rx'd */
79#define PORT_IRQ_SDB_FIS (1 << 3) /* Set Device Bits FIS rx'd */
80#define PORT_IRQ_DMAS_FIS (1 << 2) /* DMA Setup FIS rx'd */
81#define PORT_IRQ_PIOS_FIS (1 << 1) /* PIO Setup FIS rx'd */
82#define PORT_IRQ_D2H_REG_FIS (1 << 0) /* D2H Register FIS rx'd */
83
Wolfgang Denk53677ef2008-05-20 16:00:29 +020084#define PORT_IRQ_FATAL PORT_IRQ_TF_ERR | PORT_IRQ_HBUS_ERR \
Jin Zhengxiong4782ac82006-08-23 19:10:44 +080085 | PORT_IRQ_HBUS_DATA_ERR | PORT_IRQ_IF_ERR
86
Wolfgang Denk53677ef2008-05-20 16:00:29 +020087#define DEF_PORT_IRQ PORT_IRQ_FATAL | PORT_IRQ_PHYRDY \
88 | PORT_IRQ_CONNECT | PORT_IRQ_SG_DONE \
89 | PORT_IRQ_UNK_FIS | PORT_IRQ_SDB_FIS \
Jin Zhengxiong4782ac82006-08-23 19:10:44 +080090 | PORT_IRQ_DMAS_FIS | PORT_IRQ_PIOS_FIS \
91 | PORT_IRQ_D2H_REG_FIS
92
Rob Herring2bdb10d2013-08-24 10:10:50 -050093/* PORT_SCR_STAT bits */
94#define PORT_SCR_STAT_DET_MASK 0x3
95#define PORT_SCR_STAT_DET_COMINIT 0x1
96#define PORT_SCR_STAT_DET_PHYRDY 0x3
97
Jin Zhengxiong4782ac82006-08-23 19:10:44 +080098/* PORT_CMD bits */
99#define PORT_CMD_ATAPI (1 << 24) /* Device is ATAPI */
100#define PORT_CMD_LIST_ON (1 << 15) /* cmd list DMA engine running */
101#define PORT_CMD_FIS_ON (1 << 14) /* FIS DMA engine running */
102#define PORT_CMD_FIS_RX (1 << 4) /* Enable FIS receive DMA engine */
103#define PORT_CMD_CLO (1 << 3) /* Command list override */
104#define PORT_CMD_POWER_ON (1 << 2) /* Power up device */
105#define PORT_CMD_SPIN_UP (1 << 1) /* Spin up device */
106#define PORT_CMD_START (1 << 0) /* Enable port DMA engine */
107
108#define PORT_CMD_ICC_ACTIVE (0x1 << 28) /* Put i/f in active state */
109#define PORT_CMD_ICC_PARTIAL (0x2 << 28) /* Put i/f in partial state */
110#define PORT_CMD_ICC_SLUMBER (0x6 << 28) /* Put i/f in slumber state */
111
112#define AHCI_MAX_PORTS 32
113
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800114#define ATA_FLAG_SATA (1 << 3)
115#define ATA_FLAG_NO_LEGACY (1 << 4) /* no legacy mode check */
116#define ATA_FLAG_MMIO (1 << 6) /* use MMIO, not PIO */
117#define ATA_FLAG_SATA_RESET (1 << 7) /* (obsolete) use COMRESET */
118#define ATA_FLAG_PIO_DMA (1 << 8) /* PIO cmds via DMA */
119#define ATA_FLAG_NO_ATAPI (1 << 11) /* No ATAPI support */
120
121struct ahci_cmd_hdr {
122 u32 opts;
123 u32 status;
124 u32 tbl_addr;
125 u32 tbl_addr_hi;
126 u32 reserved[4];
127};
128
129struct ahci_sg {
130 u32 addr;
131 u32 addr_hi;
132 u32 reserved;
133 u32 flags_size;
134};
135
136struct ahci_ioports {
Tang Yuantianfa313772015-07-09 14:37:30 +0800137 void __iomem *port_mmio;
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800138 struct ahci_cmd_hdr *cmd_slot;
139 struct ahci_sg *cmd_tbl_sg;
Tang Yuantianfa313772015-07-09 14:37:30 +0800140 ulong cmd_tbl;
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800141 u32 rx_fis;
142};
143
Simon Glass2c9f9ef2017-06-14 21:28:32 -0600144/**
145 * struct ahci_uc_priv - information about an AHCI controller
146 *
147 * When driver model is used, this is accessible using dev_get_uclass_priv(dev)
148 * where dev is the controller (although at present it sometimes stands alone).
149 */
150struct ahci_uc_priv {
Michal Simeke8a016b2016-09-08 15:06:45 +0200151#if defined(CONFIG_DM_PCI) || defined(CONFIG_DM_SCSI)
Simon Glass2c9f9ef2017-06-14 21:28:32 -0600152 /*
153 * TODO(sjg@chromium.org): Drop this once this structure is only used
154 * in a driver-model context (i.e. attached to a device with
155 * dev_get_uclass_priv()
156 */
Simon Glassff758cc2015-11-29 13:18:06 -0700157 struct udevice *dev;
158#else
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200159 pci_dev_t dev;
Simon Glassff758cc2015-11-29 13:18:06 -0700160#endif
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800161 struct ahci_ioports port[AHCI_MAX_PORTS];
Simon Glass4b62b2f2017-06-14 21:28:33 -0600162 u16 *ataid[AHCI_MAX_PORTS];
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800163 u32 n_ports;
164 u32 hard_port_no;
165 u32 host_flags;
166 u32 host_set_flags;
Scott Wood9efaca32015-04-17 09:19:01 -0500167 void __iomem *mmio_base;
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800168 u32 pio_mask;
169 u32 udma_mask;
170 u32 flags;
171 u32 cap; /* cache of HOST_CAP register */
172 u32 port_map; /* cache of HOST_PORTS_IMPL reg */
173 u32 link_port_map; /*linkup port map*/
174};
175
Simon Glassb8341f12017-07-29 11:35:15 -0600176struct ahci_ops {
177 /**
178 * reset() - reset the controller
179 *
180 * @dev: Controller to reset
181 * @return 0 if OK, -ve on error
182 */
183 int (*reset)(struct udevice *dev);
184
185 /**
186 * port_status() - get the status of a SATA port
187 *
188 * @dev: Controller to reset
189 * @port: Port number to check (0 for first)
190 * @return 0 if detected, -ENXIO if nothing on port, other -ve on error
191 */
192 int (*port_status)(struct udevice *dev, int port);
193
194 /**
195 * scan() - scan SATA ports
196 *
197 * @dev: Controller to scan
198 * @return 0 if OK, -ve on error
199 */
200 int (*scan)(struct udevice *dev);
201};
202
203#define ahci_get_ops(dev) ((struct ahci_ops *)(dev)->driver->ops)
204
205/**
206 * sata_reset() - reset the controller
207 *
208 * @dev: Controller to reset
209 * @return 0 if OK, -ve on error
210 */
211int sata_reset(struct udevice *dev);
212
213/**
214 * sata_port_status() - get the status of a SATA port
215 *
216 * @dev: Controller to reset
217 * @port: Port number to check (0 for first)
218 * @return 0 if detected, -ENXIO if nothin on port, other -ve on error
219 */
220int sata_dm_port_status(struct udevice *dev, int port);
221
222/**
223 * sata_scan() - scan SATA ports
224 *
225 * @dev: Controller to scan
226 * @return 0 if OK, -ve on error
227 */
228int sata_scan(struct udevice *dev);
229
Scott Wood9efaca32015-04-17 09:19:01 -0500230int ahci_init(void __iomem *base);
231int ahci_reset(void __iomem *base);
Rob Herring942e3142011-07-06 16:13:36 +0000232
Simon Glass7cf1afc2017-06-14 21:28:37 -0600233/**
Michal Simeke81589e2017-11-02 15:53:56 +0100234 * ahci_init_one_dm() - set up a single AHCI port
Simon Glass7cf1afc2017-06-14 21:28:37 -0600235 *
236 * @dev: Controller to init
237 */
Michal Simeke81589e2017-11-02 15:53:56 +0100238int ahci_init_one_dm(struct udevice *dev);
Simon Glass7cf1afc2017-06-14 21:28:37 -0600239
240/**
Michal Simeke81589e2017-11-02 15:53:56 +0100241 * ahci_start_ports_dm() - start all AHCI ports for a controller
Simon Glass7cf1afc2017-06-14 21:28:37 -0600242 *
243 * @dev: Controller containing ports to start
244 */
Michal Simeke81589e2017-11-02 15:53:56 +0100245int ahci_start_ports_dm(struct udevice *dev);
Simon Glass7cf1afc2017-06-14 21:28:37 -0600246
Simon Glass4279efc2017-06-14 21:28:38 -0600247/**
248 * ahci_init_dm() - init AHCI for a controller, finding all ports
249 *
250 * @dev: Device to init
251 */
252int ahci_init_dm(struct udevice *dev, void __iomem *base);
253
Simon Glass681357f2017-06-14 21:28:46 -0600254/**
255 * ahci_bind_scsi() - bind a new SCSI bus as a child
256 *
257 * Note that the SCSI bus device will itself bind block devices
258 *
259 * @ahci_dev: AHCI parent device
260 * @devp: Returns new SCSI bus device
261 * @return 0 if OK, -ve on error
262 */
263int ahci_bind_scsi(struct udevice *ahci_dev, struct udevice **devp);
264
265/**
266 * ahci_probe_scsi() - probe and scan the attached SCSI bus
267 *
268 * Note that the SCSI device will itself bind block devices for any storage
269 * devices it finds.
270 *
271 * @ahci_dev: AHCI parent device
Simon Glass745a94f2017-07-04 13:31:18 -0600272 * @base: Base address of AHCI port
Simon Glass681357f2017-06-14 21:28:46 -0600273 * @return 0 if OK, -ve on error
274 */
Simon Glass745a94f2017-07-04 13:31:18 -0600275int ahci_probe_scsi(struct udevice *ahci_dev, ulong base);
276
277/**
278 * ahci_probe_scsi_pci() - probe and scan the attached SCSI bus on PCI
279 *
280 * Note that the SCSI device will itself bind block devices for any storage
281 * devices it finds.
282 *
283 * @ahci_dev: AHCI parent device
284 * @return 0 if OK, -ve on error
285 */
286int ahci_probe_scsi_pci(struct udevice *ahci_dev);
Simon Glass681357f2017-06-14 21:28:46 -0600287
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800288#endif