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Tom Rini83d290c2018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Adrian Alonso50a082a2015-09-02 13:54:15 -05002/*
3 * Copyright 2015 Freescale Semiconductor, Inc.
Adrian Alonso50a082a2015-09-02 13:54:15 -05004 */
5
6#include <asm/io.h>
7#include <asm/arch/imx-regs.h>
8#include <asm/arch/clock.h>
9#include <asm/arch/sys_proto.h>
Stefano Babic552a8482017-06-29 10:16:06 +020010#include <asm/mach-imx/boot_mode.h>
Adrian Alonso50a082a2015-09-02 13:54:15 -050011#include <asm/arch/crm_regs.h>
12
13void init_aips(void)
14{
Adrian Alonso75a565f2015-09-02 13:54:20 -050015 struct aipstz_regs *aips1, *aips2, *aips3;
Adrian Alonso50a082a2015-09-02 13:54:15 -050016
17 aips1 = (struct aipstz_regs *)AIPS1_BASE_ADDR;
18 aips2 = (struct aipstz_regs *)AIPS2_BASE_ADDR;
Adrian Alonso50a082a2015-09-02 13:54:15 -050019 aips3 = (struct aipstz_regs *)AIPS3_BASE_ADDR;
Adrian Alonso50a082a2015-09-02 13:54:15 -050020
21 /*
22 * Set all MPROTx to be non-bufferable, trusted for R/W,
23 * not forced to user-mode.
24 */
25 writel(0x77777777, &aips1->mprot0);
26 writel(0x77777777, &aips1->mprot1);
27 writel(0x77777777, &aips2->mprot0);
28 writel(0x77777777, &aips2->mprot1);
29
30 /*
31 * Set all OPACRx to be non-bufferable, not require
32 * supervisor privilege level for access,allow for
33 * write access and untrusted master access.
34 */
35 writel(0x00000000, &aips1->opacr0);
36 writel(0x00000000, &aips1->opacr1);
37 writel(0x00000000, &aips1->opacr2);
38 writel(0x00000000, &aips1->opacr3);
39 writel(0x00000000, &aips1->opacr4);
40 writel(0x00000000, &aips2->opacr0);
41 writel(0x00000000, &aips2->opacr1);
42 writel(0x00000000, &aips2->opacr2);
43 writel(0x00000000, &aips2->opacr3);
44 writel(0x00000000, &aips2->opacr4);
45
Peng Fan2d4bbd02016-08-11 14:02:49 +080046 if (is_mx6ull() || is_mx6sx() || is_mx7()) {
Adrian Alonso75a565f2015-09-02 13:54:20 -050047 /*
48 * Set all MPROTx to be non-bufferable, trusted for R/W,
49 * not forced to user-mode.
50 */
51 writel(0x77777777, &aips3->mprot0);
52 writel(0x77777777, &aips3->mprot1);
Adrian Alonso50a082a2015-09-02 13:54:15 -050053
Adrian Alonso75a565f2015-09-02 13:54:20 -050054 /*
55 * Set all OPACRx to be non-bufferable, not require
56 * supervisor privilege level for access,allow for
57 * write access and untrusted master access.
58 */
59 writel(0x00000000, &aips3->opacr0);
60 writel(0x00000000, &aips3->opacr1);
61 writel(0x00000000, &aips3->opacr2);
62 writel(0x00000000, &aips3->opacr3);
63 writel(0x00000000, &aips3->opacr4);
64 }
Adrian Alonso50a082a2015-09-02 13:54:15 -050065}
66
Fabio Estevame2162d72017-11-23 10:55:33 -020067void imx_wdog_disable_powerdown(void)
Adrian Alonso648539c2015-09-02 13:54:21 -050068{
69 struct wdog_regs *wdog1 = (struct wdog_regs *)WDOG1_BASE_ADDR;
70 struct wdog_regs *wdog2 = (struct wdog_regs *)WDOG2_BASE_ADDR;
71 struct wdog_regs *wdog3 = (struct wdog_regs *)WDOG3_BASE_ADDR;
72#ifdef CONFIG_MX7D
73 struct wdog_regs *wdog4 = (struct wdog_regs *)WDOG4_BASE_ADDR;
74#endif
75
76 /* Write to the PDE (Power Down Enable) bit */
Fabio Estevame2162d72017-11-23 10:55:33 -020077 writew(0, &wdog1->wmcr);
78 writew(0, &wdog2->wmcr);
Adrian Alonso648539c2015-09-02 13:54:21 -050079
Fabio Estevamb42287f2017-11-23 09:18:54 -020080 if (is_mx6sx() || is_mx6ul() || is_mx6ull() || is_mx7())
Fabio Estevame2162d72017-11-23 10:55:33 -020081 writew(0, &wdog3->wmcr);
Adrian Alonso648539c2015-09-02 13:54:21 -050082#ifdef CONFIG_MX7D
Fabio Estevame2162d72017-11-23 10:55:33 -020083 writew(0, &wdog4->wmcr);
Adrian Alonso648539c2015-09-02 13:54:21 -050084#endif
85}
86
Adrian Alonso50a082a2015-09-02 13:54:15 -050087#define SRC_SCR_WARM_RESET_ENABLE 0
88
89void init_src(void)
90{
91 struct src *src_regs = (struct src *)SRC_BASE_ADDR;
92 u32 val;
93
94 /*
95 * force warm reset sources to generate cold reset
96 * for a more reliable restart
97 */
98 val = readl(&src_regs->scr);
99 val &= ~(1 << SRC_SCR_WARM_RESET_ENABLE);
100 writel(val, &src_regs->scr);
101}
102
Peng Fan4406da02015-09-15 14:05:06 +0800103#ifdef CONFIG_CMD_BMODE
Adrian Alonso50a082a2015-09-02 13:54:15 -0500104void boot_mode_apply(unsigned cfg_val)
105{
106 unsigned reg;
107 struct src *psrc = (struct src *)SRC_BASE_ADDR;
108 writel(cfg_val, &psrc->gpr9);
109 reg = readl(&psrc->gpr10);
110 if (cfg_val)
Claudius Heinedde31a12019-10-29 13:08:44 +0100111 reg |= IMX6_SRC_GPR10_BMODE;
Adrian Alonso50a082a2015-09-02 13:54:15 -0500112 else
Claudius Heinedde31a12019-10-29 13:08:44 +0100113 reg &= ~IMX6_SRC_GPR10_BMODE;
Adrian Alonso50a082a2015-09-02 13:54:15 -0500114 writel(reg, &psrc->gpr10);
115}
Peng Fan4406da02015-09-15 14:05:06 +0800116#endif
Jagan Tekicba586b2017-02-24 15:45:12 +0530117
118#if defined(CONFIG_MX6)
119u32 imx6_src_get_boot_mode(void)
120{
Claudius Heinee01c8cf2019-10-29 13:08:43 +0100121 if (readl(&src_base->gpr10) & IMX6_SRC_GPR10_BMODE)
Jagan Teki7b54f5a2017-02-24 15:45:15 +0530122 return readl(&src_base->gpr9);
Jagan Tekicba586b2017-02-24 15:45:12 +0530123 else
Jagan Teki7b54f5a2017-02-24 15:45:15 +0530124 return readl(&src_base->sbmr1);
Jagan Tekicba586b2017-02-24 15:45:12 +0530125}
126#endif