Sergey Kubushyn | c74b210 | 2007-08-10 20:26:18 +0200 | [diff] [blame] | 1 | /* |
| 2 | * NAND driver for TI DaVinci based boards. |
| 3 | * |
| 4 | * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net> |
| 5 | * |
| 6 | * Based on Linux DaVinci NAND driver by TI. Original copyright follows: |
| 7 | */ |
| 8 | |
| 9 | /* |
| 10 | * |
| 11 | * linux/drivers/mtd/nand/nand_davinci.c |
| 12 | * |
| 13 | * NAND Flash Driver |
| 14 | * |
| 15 | * Copyright (C) 2006 Texas Instruments. |
| 16 | * |
| 17 | * ---------------------------------------------------------------------------- |
| 18 | * |
| 19 | * This program is free software; you can redistribute it and/or modify |
| 20 | * it under the terms of the GNU General Public License as published by |
| 21 | * the Free Software Foundation; either version 2 of the License, or |
| 22 | * (at your option) any later version. |
| 23 | * |
| 24 | * This program is distributed in the hope that it will be useful, |
| 25 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 26 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 27 | * GNU General Public License for more details. |
| 28 | * |
| 29 | * You should have received a copy of the GNU General Public License |
| 30 | * along with this program; if not, write to the Free Software |
| 31 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. |
| 32 | * ---------------------------------------------------------------------------- |
| 33 | * |
| 34 | * Overview: |
| 35 | * This is a device driver for the NAND flash device found on the |
| 36 | * DaVinci board which utilizes the Samsung k9k2g08 part. |
| 37 | * |
| 38 | Modifications: |
| 39 | ver. 1.0: Feb 2005, Vinod/Sudhakar |
| 40 | - |
| 41 | * |
| 42 | */ |
| 43 | |
| 44 | #include <common.h> |
William Juul | cfa460a | 2007-10-31 13:53:06 +0100 | [diff] [blame] | 45 | #include <asm/io.h> |
Sergey Kubushyn | c74b210 | 2007-08-10 20:26:18 +0200 | [diff] [blame] | 46 | #include <nand.h> |
| 47 | #include <asm/arch/nand_defs.h> |
| 48 | #include <asm/arch/emif_defs.h> |
| 49 | |
Sandeep Paulraj | 77b351c | 2009-08-18 10:10:42 -0400 | [diff] [blame] | 50 | /* Definitions for 4-bit hardware ECC */ |
| 51 | #define NAND_TIMEOUT 10240 |
| 52 | #define NAND_ECC_BUSY 0xC |
| 53 | #define NAND_4BITECC_MASK 0x03FF03FF |
| 54 | #define EMIF_NANDFSR_ECC_STATE_MASK 0x00000F00 |
| 55 | #define ECC_STATE_NO_ERR 0x0 |
| 56 | #define ECC_STATE_TOO_MANY_ERRS 0x1 |
| 57 | #define ECC_STATE_ERR_CORR_COMP_P 0x2 |
| 58 | #define ECC_STATE_ERR_CORR_COMP_N 0x3 |
| 59 | |
David Brownell | fcb7747 | 2009-04-28 13:19:50 -0700 | [diff] [blame] | 60 | static emif_registers *const emif_regs = (void *) DAVINCI_ASYNC_EMIF_CNTRL_BASE; |
| 61 | |
William Juul | cfa460a | 2007-10-31 13:53:06 +0100 | [diff] [blame] | 62 | static void nand_davinci_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl) |
Sergey Kubushyn | c74b210 | 2007-08-10 20:26:18 +0200 | [diff] [blame] | 63 | { |
| 64 | struct nand_chip *this = mtd->priv; |
| 65 | u_int32_t IO_ADDR_W = (u_int32_t)this->IO_ADDR_W; |
| 66 | |
| 67 | IO_ADDR_W &= ~(MASK_ALE|MASK_CLE); |
| 68 | |
William Juul | cfa460a | 2007-10-31 13:53:06 +0100 | [diff] [blame] | 69 | if (ctrl & NAND_CTRL_CHANGE) { |
| 70 | if ( ctrl & NAND_CLE ) |
Sergey Kubushyn | c74b210 | 2007-08-10 20:26:18 +0200 | [diff] [blame] | 71 | IO_ADDR_W |= MASK_CLE; |
William Juul | cfa460a | 2007-10-31 13:53:06 +0100 | [diff] [blame] | 72 | if ( ctrl & NAND_ALE ) |
Sergey Kubushyn | c74b210 | 2007-08-10 20:26:18 +0200 | [diff] [blame] | 73 | IO_ADDR_W |= MASK_ALE; |
William Juul | cfa460a | 2007-10-31 13:53:06 +0100 | [diff] [blame] | 74 | this->IO_ADDR_W = (void __iomem *) IO_ADDR_W; |
Sergey Kubushyn | c74b210 | 2007-08-10 20:26:18 +0200 | [diff] [blame] | 75 | } |
| 76 | |
William Juul | 5e1dae5 | 2007-11-09 13:32:30 +0100 | [diff] [blame] | 77 | if (cmd != NAND_CMD_NONE) |
William Juul | cfa460a | 2007-10-31 13:53:06 +0100 | [diff] [blame] | 78 | writeb(cmd, this->IO_ADDR_W); |
Sergey Kubushyn | c74b210 | 2007-08-10 20:26:18 +0200 | [diff] [blame] | 79 | } |
| 80 | |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 81 | #ifdef CONFIG_SYS_NAND_HW_ECC |
Sergey Kubushyn | c74b210 | 2007-08-10 20:26:18 +0200 | [diff] [blame] | 82 | |
| 83 | static void nand_davinci_enable_hwecc(struct mtd_info *mtd, int mode) |
| 84 | { |
Nick Thompson | 97f4eb8 | 2009-12-12 12:12:26 -0500 | [diff] [blame] | 85 | u_int32_t val; |
Sergey Kubushyn | c74b210 | 2007-08-10 20:26:18 +0200 | [diff] [blame] | 86 | |
Nick Thompson | 97f4eb8 | 2009-12-12 12:12:26 -0500 | [diff] [blame] | 87 | (void)readl(&(emif_regs->NANDFECC[CONFIG_SYS_NAND_CS - 2])); |
Sergey Kubushyn | c74b210 | 2007-08-10 20:26:18 +0200 | [diff] [blame] | 88 | |
Nick Thompson | 97f4eb8 | 2009-12-12 12:12:26 -0500 | [diff] [blame] | 89 | val = readl(&emif_regs->NANDFCR); |
Nick Thompson | 26be2c5 | 2009-12-12 12:13:10 -0500 | [diff] [blame^] | 90 | val |= DAVINCI_NANDFCR_NAND_ENABLE(CONFIG_SYS_NAND_CS); |
Nick Thompson | 97f4eb8 | 2009-12-12 12:12:26 -0500 | [diff] [blame] | 91 | val |= DAVINCI_NANDFCR_1BIT_ECC_START(CONFIG_SYS_NAND_CS); |
| 92 | writel(val, &emif_regs->NANDFCR); |
Sergey Kubushyn | c74b210 | 2007-08-10 20:26:18 +0200 | [diff] [blame] | 93 | } |
| 94 | |
| 95 | static u_int32_t nand_davinci_readecc(struct mtd_info *mtd, u_int32_t region) |
| 96 | { |
| 97 | u_int32_t ecc = 0; |
Sergey Kubushyn | c74b210 | 2007-08-10 20:26:18 +0200 | [diff] [blame] | 98 | |
Nick Thompson | 97f4eb8 | 2009-12-12 12:12:26 -0500 | [diff] [blame] | 99 | ecc = readl(&(emif_regs->NANDFECC[region - 1])); |
Sergey Kubushyn | c74b210 | 2007-08-10 20:26:18 +0200 | [diff] [blame] | 100 | |
| 101 | return(ecc); |
| 102 | } |
| 103 | |
| 104 | static int nand_davinci_calculate_ecc(struct mtd_info *mtd, const u_char *dat, u_char *ecc_code) |
| 105 | { |
| 106 | u_int32_t tmp; |
Hugo Villeneuve | 9b05aa7 | 2008-08-30 17:06:55 -0400 | [diff] [blame] | 107 | const int region = 1; |
| 108 | |
| 109 | tmp = nand_davinci_readecc(mtd, region); |
| 110 | |
| 111 | /* Squeeze 4 bytes ECC into 3 bytes by removing RESERVED bits |
| 112 | * and shifting. RESERVED bits are 31 to 28 and 15 to 12. */ |
| 113 | tmp = (tmp & 0x00000fff) | ((tmp & 0x0fff0000) >> 4); |
| 114 | |
| 115 | /* Invert so that erased block ECC is correct */ |
| 116 | tmp = ~tmp; |
| 117 | |
| 118 | *ecc_code++ = tmp; |
| 119 | *ecc_code++ = tmp >> 8; |
| 120 | *ecc_code++ = tmp >> 16; |
David Brownell | 6e29ed8 | 2009-04-28 13:19:53 -0700 | [diff] [blame] | 121 | |
| 122 | /* NOTE: the above code matches mainline Linux: |
| 123 | * .PQR.stu ==> ~PQRstu |
| 124 | * |
| 125 | * MontaVista/TI kernels encode those bytes differently, use |
| 126 | * complicated (and allegedly sometimes-wrong) correction code, |
| 127 | * and usually shipped with U-Boot that uses software ECC: |
| 128 | * .PQR.stu ==> PsQRtu |
| 129 | * |
| 130 | * If you need MV/TI compatible NAND I/O in U-Boot, it should |
| 131 | * be possible to (a) change the mangling above, (b) reverse |
| 132 | * that mangling in nand_davinci_correct_data() below. |
| 133 | */ |
| 134 | |
| 135 | return 0; |
Sergey Kubushyn | c74b210 | 2007-08-10 20:26:18 +0200 | [diff] [blame] | 136 | } |
| 137 | |
Sergey Kubushyn | c74b210 | 2007-08-10 20:26:18 +0200 | [diff] [blame] | 138 | static int nand_davinci_correct_data(struct mtd_info *mtd, u_char *dat, u_char *read_ecc, u_char *calc_ecc) |
| 139 | { |
Hugo Villeneuve | 9b05aa7 | 2008-08-30 17:06:55 -0400 | [diff] [blame] | 140 | struct nand_chip *this = mtd->priv; |
Hugo Villeneuve | 9b05aa7 | 2008-08-30 17:06:55 -0400 | [diff] [blame] | 141 | u_int32_t ecc_nand = read_ecc[0] | (read_ecc[1] << 8) | |
| 142 | (read_ecc[2] << 16); |
| 143 | u_int32_t ecc_calc = calc_ecc[0] | (calc_ecc[1] << 8) | |
| 144 | (calc_ecc[2] << 16); |
| 145 | u_int32_t diff = ecc_calc ^ ecc_nand; |
| 146 | |
| 147 | if (diff) { |
| 148 | if ((((diff >> 12) ^ diff) & 0xfff) == 0xfff) { |
| 149 | /* Correctable error */ |
| 150 | if ((diff >> (12 + 3)) < this->ecc.size) { |
| 151 | uint8_t find_bit = 1 << ((diff >> 12) & 7); |
| 152 | uint32_t find_byte = diff >> (12 + 3); |
| 153 | |
| 154 | dat[find_byte] ^= find_bit; |
| 155 | MTDDEBUG(MTD_DEBUG_LEVEL0, "Correcting single " |
| 156 | "bit ECC error at offset: %d, bit: " |
| 157 | "%d\n", find_byte, find_bit); |
| 158 | return 1; |
| 159 | } else { |
| 160 | return -1; |
| 161 | } |
| 162 | } else if (!(diff & (diff - 1))) { |
| 163 | /* Single bit ECC error in the ECC itself, |
| 164 | nothing to fix */ |
| 165 | MTDDEBUG(MTD_DEBUG_LEVEL0, "Single bit ECC error in " |
| 166 | "ECC.\n"); |
| 167 | return 1; |
| 168 | } else { |
| 169 | /* Uncorrectable error */ |
| 170 | MTDDEBUG(MTD_DEBUG_LEVEL0, "ECC UNCORRECTED_ERROR 1\n"); |
| 171 | return -1; |
| 172 | } |
| 173 | } |
Sergey Kubushyn | c74b210 | 2007-08-10 20:26:18 +0200 | [diff] [blame] | 174 | return(0); |
| 175 | } |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 176 | #endif /* CONFIG_SYS_NAND_HW_ECC */ |
Sergey Kubushyn | c74b210 | 2007-08-10 20:26:18 +0200 | [diff] [blame] | 177 | |
Sandeep Paulraj | 77b351c | 2009-08-18 10:10:42 -0400 | [diff] [blame] | 178 | #ifdef CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST |
| 179 | static struct nand_ecclayout nand_davinci_4bit_layout_oobfirst = { |
Sandeep Paulraj | 10a5a799 | 2009-11-19 23:04:42 -0500 | [diff] [blame] | 180 | #if defined(CONFIG_SYS_NAND_PAGE_2K) |
Sandeep Paulraj | 77b351c | 2009-08-18 10:10:42 -0400 | [diff] [blame] | 181 | .eccbytes = 40, |
| 182 | .eccpos = { |
| 183 | 24, 25, 26, 27, 28, |
| 184 | 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, |
| 185 | 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, |
| 186 | 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, |
| 187 | 59, 60, 61, 62, 63, |
| 188 | }, |
| 189 | .oobfree = { |
| 190 | {.offset = 2, .length = 22, }, |
| 191 | }, |
Sandeep Paulraj | 10a5a799 | 2009-11-19 23:04:42 -0500 | [diff] [blame] | 192 | #elif defined(CONFIG_SYS_NAND_PAGE_4K) |
| 193 | .eccbytes = 80, |
| 194 | .eccpos = { |
| 195 | 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, |
| 196 | 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, |
| 197 | 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, |
| 198 | 78, 79, 80, 81, 82, 83, 84, 85, 86, 87, |
| 199 | 88, 89, 90, 91, 92, 93, 94, 95, 96, 97, |
| 200 | 98, 99, 100, 101, 102, 103, 104, 105, 106, 107, |
| 201 | 108, 109, 110, 111, 112, 113, 114, 115, 116, 117, |
| 202 | 118, 119, 120, 121, 122, 123, 124, 125, 126, 127, |
| 203 | }, |
| 204 | .oobfree = { |
| 205 | {.offset = 2, .length = 46, }, |
| 206 | }, |
Sandeep Paulraj | 77b351c | 2009-08-18 10:10:42 -0400 | [diff] [blame] | 207 | #endif |
| 208 | }; |
Sandeep Paulraj | 77b351c | 2009-08-18 10:10:42 -0400 | [diff] [blame] | 209 | |
| 210 | static void nand_davinci_4bit_enable_hwecc(struct mtd_info *mtd, int mode) |
| 211 | { |
| 212 | u32 val; |
| 213 | |
| 214 | switch (mode) { |
| 215 | case NAND_ECC_WRITE: |
| 216 | case NAND_ECC_READ: |
| 217 | /* |
| 218 | * Start a new ECC calculation for reading or writing 512 bytes |
| 219 | * of data. |
| 220 | */ |
Nick Thompson | 97f4eb8 | 2009-12-12 12:12:26 -0500 | [diff] [blame] | 221 | val = readl(&emif_regs->NANDFCR); |
| 222 | val &= ~DAVINCI_NANDFCR_4BIT_ECC_SEL_MASK; |
Nick Thompson | 26be2c5 | 2009-12-12 12:13:10 -0500 | [diff] [blame^] | 223 | val |= DAVINCI_NANDFCR_NAND_ENABLE(CONFIG_SYS_NAND_CS); |
Nick Thompson | 97f4eb8 | 2009-12-12 12:12:26 -0500 | [diff] [blame] | 224 | val |= DAVINCI_NANDFCR_4BIT_ECC_SEL(CONFIG_SYS_NAND_CS); |
| 225 | val |= DAVINCI_NANDFCR_4BIT_ECC_START; |
| 226 | writel(val, &emif_regs->NANDFCR); |
Sandeep Paulraj | 77b351c | 2009-08-18 10:10:42 -0400 | [diff] [blame] | 227 | break; |
| 228 | case NAND_ECC_READSYN: |
| 229 | val = emif_regs->NAND4BITECC1; |
| 230 | break; |
| 231 | default: |
| 232 | break; |
| 233 | } |
| 234 | } |
| 235 | |
| 236 | static u32 nand_davinci_4bit_readecc(struct mtd_info *mtd, unsigned int ecc[4]) |
| 237 | { |
| 238 | ecc[0] = emif_regs->NAND4BITECC1 & NAND_4BITECC_MASK; |
| 239 | ecc[1] = emif_regs->NAND4BITECC2 & NAND_4BITECC_MASK; |
| 240 | ecc[2] = emif_regs->NAND4BITECC3 & NAND_4BITECC_MASK; |
| 241 | ecc[3] = emif_regs->NAND4BITECC4 & NAND_4BITECC_MASK; |
| 242 | |
| 243 | return 0; |
| 244 | } |
| 245 | |
| 246 | static int nand_davinci_4bit_calculate_ecc(struct mtd_info *mtd, |
| 247 | const uint8_t *dat, |
| 248 | uint8_t *ecc_code) |
| 249 | { |
| 250 | unsigned int hw_4ecc[4] = { 0, 0, 0, 0 }; |
| 251 | unsigned int const1 = 0, const2 = 0; |
| 252 | unsigned char count1 = 0; |
| 253 | |
| 254 | nand_davinci_4bit_readecc(mtd, hw_4ecc); |
| 255 | |
| 256 | /*Convert 10 bit ecc value to 8 bit */ |
| 257 | for (count1 = 0; count1 < 2; count1++) { |
| 258 | const2 = count1 * 5; |
| 259 | const1 = count1 * 2; |
| 260 | |
| 261 | /* Take first 8 bits from val1 (count1=0) or val5 (count1=1) */ |
| 262 | ecc_code[const2] = hw_4ecc[const1] & 0xFF; |
| 263 | |
| 264 | /* |
| 265 | * Take 2 bits as LSB bits from val1 (count1=0) or val5 |
| 266 | * (count1=1) and 6 bits from val2 (count1=0) or |
| 267 | * val5 (count1=1) |
| 268 | */ |
| 269 | ecc_code[const2 + 1] = |
| 270 | ((hw_4ecc[const1] >> 8) & 0x3) | ((hw_4ecc[const1] >> 14) & |
| 271 | 0xFC); |
| 272 | |
| 273 | /* |
| 274 | * Take 4 bits from val2 (count1=0) or val5 (count1=1) and |
| 275 | * 4 bits from val3 (count1=0) or val6 (count1=1) |
| 276 | */ |
| 277 | ecc_code[const2 + 2] = |
| 278 | ((hw_4ecc[const1] >> 22) & 0xF) | |
| 279 | ((hw_4ecc[const1 + 1] << 4) & 0xF0); |
| 280 | |
| 281 | /* |
| 282 | * Take 6 bits from val3(count1=0) or val6 (count1=1) and |
| 283 | * 2 bits from val4 (count1=0) or val7 (count1=1) |
| 284 | */ |
| 285 | ecc_code[const2 + 3] = |
| 286 | ((hw_4ecc[const1 + 1] >> 4) & 0x3F) | |
| 287 | ((hw_4ecc[const1 + 1] >> 10) & 0xC0); |
| 288 | |
| 289 | /* Take 8 bits from val4 (count1=0) or val7 (count1=1) */ |
| 290 | ecc_code[const2 + 4] = (hw_4ecc[const1 + 1] >> 18) & 0xFF; |
| 291 | } |
| 292 | return 0; |
| 293 | } |
| 294 | |
| 295 | |
| 296 | static int nand_davinci_4bit_correct_data(struct mtd_info *mtd, uint8_t *dat, |
| 297 | uint8_t *read_ecc, uint8_t *calc_ecc) |
| 298 | { |
Sandeep Paulraj | 77b351c | 2009-08-18 10:10:42 -0400 | [diff] [blame] | 299 | unsigned short ecc_10bit[8] = { 0, 0, 0, 0, 0, 0, 0, 0 }; |
| 300 | int i; |
| 301 | unsigned int hw_4ecc[4] = { 0, 0, 0, 0 }, iserror = 0; |
| 302 | unsigned short *pspare = NULL, *pspare1 = NULL; |
| 303 | unsigned int numerrors, erroraddress, errorvalue; |
| 304 | u32 val; |
| 305 | |
| 306 | /* |
| 307 | * Check for an ECC where all bytes are 0xFF. If this is the case, we |
| 308 | * will assume we are looking at an erased page and we should ignore |
| 309 | * the ECC. |
| 310 | */ |
| 311 | for (i = 0; i < 10; i++) { |
| 312 | if (read_ecc[i] != 0xFF) |
| 313 | break; |
| 314 | } |
| 315 | if (i == 10) |
| 316 | return 0; |
| 317 | |
| 318 | /* Convert 8 bit in to 10 bit */ |
| 319 | pspare = (unsigned short *)&read_ecc[2]; |
| 320 | pspare1 = (unsigned short *)&read_ecc[0]; |
| 321 | |
| 322 | /* Take 10 bits from 0th and 1st bytes */ |
| 323 | ecc_10bit[0] = (*pspare1) & 0x3FF; |
| 324 | |
| 325 | /* Take 6 bits from 1st byte and 4 bits from 2nd byte */ |
| 326 | ecc_10bit[1] = (((*pspare1) >> 10) & 0x3F) |
| 327 | | (((pspare[0]) << 6) & 0x3C0); |
| 328 | |
| 329 | /* Take 4 bits form 2nd bytes and 6 bits from 3rd bytes */ |
| 330 | ecc_10bit[2] = ((pspare[0]) >> 4) & 0x3FF; |
| 331 | |
| 332 | /*Take 2 bits from 3rd byte and 8 bits from 4th byte */ |
| 333 | ecc_10bit[3] = (((pspare[0]) >> 14) & 0x3) |
| 334 | | ((((pspare[1])) << 2) & 0x3FC); |
| 335 | |
| 336 | /* Take 8 bits from 5th byte and 2 bits from 6th byte */ |
| 337 | ecc_10bit[4] = ((pspare[1]) >> 8) |
| 338 | | ((((pspare[2])) << 8) & 0x300); |
| 339 | |
| 340 | /* Take 6 bits from 6th byte and 4 bits from 7th byte */ |
| 341 | ecc_10bit[5] = (pspare[2] >> 2) & 0x3FF; |
| 342 | |
| 343 | /* Take 4 bits from 7th byte and 6 bits from 8th byte */ |
| 344 | ecc_10bit[6] = (((pspare[2]) >> 12) & 0xF) |
| 345 | | ((((pspare[3])) << 4) & 0x3F0); |
| 346 | |
| 347 | /*Take 2 bits from 8th byte and 8 bits from 9th byte */ |
| 348 | ecc_10bit[7] = ((pspare[3]) >> 6) & 0x3FF; |
| 349 | |
| 350 | /* |
| 351 | * Write the parity values in the NAND Flash 4-bit ECC Load register. |
| 352 | * Write each parity value one at a time starting from 4bit_ecc_val8 |
| 353 | * to 4bit_ecc_val1. |
| 354 | */ |
| 355 | for (i = 7; i >= 0; i--) |
| 356 | emif_regs->NAND4BITECCLOAD = ecc_10bit[i]; |
| 357 | |
| 358 | /* |
| 359 | * Perform a dummy read to the EMIF Revision Code and Status register. |
| 360 | * This is required to ensure time for syndrome calculation after |
| 361 | * writing the ECC values in previous step. |
| 362 | */ |
| 363 | |
| 364 | val = emif_regs->NANDFSR; |
| 365 | |
| 366 | /* |
| 367 | * Read the syndrome from the NAND Flash 4-Bit ECC 1-4 registers. |
| 368 | * A syndrome value of 0 means no bit errors. If the syndrome is |
| 369 | * non-zero then go further otherwise return. |
| 370 | */ |
| 371 | nand_davinci_4bit_readecc(mtd, hw_4ecc); |
| 372 | |
| 373 | if (hw_4ecc[0] == ECC_STATE_NO_ERR && hw_4ecc[1] == ECC_STATE_NO_ERR && |
| 374 | hw_4ecc[2] == ECC_STATE_NO_ERR && hw_4ecc[3] == ECC_STATE_NO_ERR) |
| 375 | return 0; |
| 376 | |
| 377 | /* |
| 378 | * Clear any previous address calculation by doing a dummy read of an |
| 379 | * error address register. |
| 380 | */ |
| 381 | val = emif_regs->NANDERRADD1; |
| 382 | |
| 383 | /* |
| 384 | * Set the addr_calc_st bit(bit no 13) in the NAND Flash Control |
| 385 | * register to 1. |
| 386 | */ |
| 387 | emif_regs->NANDFCR |= 1 << 13; |
| 388 | |
| 389 | /* |
| 390 | * Wait for the corr_state field (bits 8 to 11)in the |
| 391 | * NAND Flash Status register to be equal to 0x0, 0x1, 0x2, or 0x3. |
| 392 | */ |
| 393 | i = NAND_TIMEOUT; |
| 394 | do { |
| 395 | val = emif_regs->NANDFSR; |
| 396 | val &= 0xc00; |
| 397 | i--; |
| 398 | } while ((i > 0) && val); |
| 399 | |
| 400 | iserror = emif_regs->NANDFSR; |
| 401 | iserror &= EMIF_NANDFSR_ECC_STATE_MASK; |
| 402 | iserror = iserror >> 8; |
| 403 | |
| 404 | /* |
| 405 | * ECC_STATE_TOO_MANY_ERRS (0x1) means errors cannot be |
| 406 | * corrected (five or more errors). The number of errors |
| 407 | * calculated (err_num field) differs from the number of errors |
| 408 | * searched. ECC_STATE_ERR_CORR_COMP_P (0x2) means error |
| 409 | * correction complete (errors on bit 8 or 9). |
| 410 | * ECC_STATE_ERR_CORR_COMP_N (0x3) means error correction |
| 411 | * complete (error exists). |
| 412 | */ |
| 413 | |
| 414 | if (iserror == ECC_STATE_NO_ERR) { |
| 415 | val = emif_regs->NANDERRVAL1; |
| 416 | return 0; |
| 417 | } else if (iserror == ECC_STATE_TOO_MANY_ERRS) { |
| 418 | val = emif_regs->NANDERRVAL1; |
| 419 | return -1; |
| 420 | } |
| 421 | |
| 422 | numerrors = ((emif_regs->NANDFSR >> 16) & 0x3) + 1; |
| 423 | |
| 424 | /* Read the error address, error value and correct */ |
| 425 | for (i = 0; i < numerrors; i++) { |
| 426 | if (i > 1) { |
| 427 | erroraddress = |
| 428 | ((emif_regs->NANDERRADD2 >> |
| 429 | (16 * (i & 1))) & 0x3FF); |
| 430 | erroraddress = ((512 + 7) - erroraddress); |
| 431 | errorvalue = |
| 432 | ((emif_regs->NANDERRVAL2 >> |
| 433 | (16 * (i & 1))) & 0xFF); |
| 434 | } else { |
| 435 | erroraddress = |
| 436 | ((emif_regs->NANDERRADD1 >> |
| 437 | (16 * (i & 1))) & 0x3FF); |
| 438 | erroraddress = ((512 + 7) - erroraddress); |
| 439 | errorvalue = |
| 440 | ((emif_regs->NANDERRVAL1 >> |
| 441 | (16 * (i & 1))) & 0xFF); |
| 442 | } |
| 443 | /* xor the corrupt data with error value */ |
| 444 | if (erroraddress < 512) |
| 445 | dat[erroraddress] ^= errorvalue; |
| 446 | } |
| 447 | |
| 448 | return numerrors; |
| 449 | } |
Scott Wood | d44e9c1 | 2009-09-28 16:33:18 -0500 | [diff] [blame] | 450 | #endif /* CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST */ |
Sandeep Paulraj | 77b351c | 2009-08-18 10:10:42 -0400 | [diff] [blame] | 451 | |
Sergey Kubushyn | c74b210 | 2007-08-10 20:26:18 +0200 | [diff] [blame] | 452 | static int nand_davinci_dev_ready(struct mtd_info *mtd) |
| 453 | { |
David Brownell | fcb7747 | 2009-04-28 13:19:50 -0700 | [diff] [blame] | 454 | return emif_regs->NANDFSR & 0x1; |
Sergey Kubushyn | c74b210 | 2007-08-10 20:26:18 +0200 | [diff] [blame] | 455 | } |
| 456 | |
| 457 | static void nand_flash_init(void) |
| 458 | { |
David Brownell | fcb7747 | 2009-04-28 13:19:50 -0700 | [diff] [blame] | 459 | /* This is for DM6446 EVM and *very* similar. DO NOT GROW THIS! |
| 460 | * Instead, have your board_init() set EMIF timings, based on its |
| 461 | * knowledge of the clocks and what devices are hooked up ... and |
| 462 | * don't even do that unless no UBL handled it. |
| 463 | */ |
David Brownell | ed727d3 | 2009-07-13 16:29:04 -0700 | [diff] [blame] | 464 | #ifdef CONFIG_SOC_DM644X |
Wolfgang Denk | 950a392 | 2008-04-11 15:11:26 +0200 | [diff] [blame] | 465 | u_int32_t acfg1 = 0x3ffffffc; |
Wolfgang Denk | 950a392 | 2008-04-11 15:11:26 +0200 | [diff] [blame] | 466 | |
| 467 | /*------------------------------------------------------------------* |
| 468 | * NAND FLASH CHIP TIMEOUT @ 459 MHz * |
| 469 | * * |
| 470 | * AEMIF.CLK freq = PLL1/6 = 459/6 = 76.5 MHz * |
| 471 | * AEMIF.CLK period = 1/76.5 MHz = 13.1 ns * |
| 472 | * * |
| 473 | *------------------------------------------------------------------*/ |
| 474 | acfg1 = 0 |
Wolfgang Denk | 53677ef | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 475 | | (0 << 31 ) /* selectStrobe */ |
| 476 | | (0 << 30 ) /* extWait */ |
| 477 | | (1 << 26 ) /* writeSetup 10 ns */ |
| 478 | | (3 << 20 ) /* writeStrobe 40 ns */ |
| 479 | | (1 << 17 ) /* writeHold 10 ns */ |
| 480 | | (1 << 13 ) /* readSetup 10 ns */ |
| 481 | | (5 << 7 ) /* readStrobe 60 ns */ |
| 482 | | (1 << 4 ) /* readHold 10 ns */ |
| 483 | | (3 << 2 ) /* turnAround ?? ns */ |
| 484 | | (0 << 0 ) /* asyncSize 8-bit bus */ |
| 485 | ; |
Wolfgang Denk | 950a392 | 2008-04-11 15:11:26 +0200 | [diff] [blame] | 486 | |
Thomas Lange | d583ef5 | 2009-06-20 11:02:17 +0200 | [diff] [blame] | 487 | emif_regs->AB1CR = acfg1; /* CS2 */ |
| 488 | |
| 489 | emif_regs->NANDFCR = 0x00000101; /* NAND flash on CS2 */ |
David Brownell | fcb7747 | 2009-04-28 13:19:50 -0700 | [diff] [blame] | 490 | #endif |
Sergey Kubushyn | c74b210 | 2007-08-10 20:26:18 +0200 | [diff] [blame] | 491 | } |
| 492 | |
David Brownell | 154b548 | 2009-05-10 15:43:01 -0700 | [diff] [blame] | 493 | void davinci_nand_init(struct nand_chip *nand) |
Sergey Kubushyn | c74b210 | 2007-08-10 20:26:18 +0200 | [diff] [blame] | 494 | { |
Sergey Kubushyn | c74b210 | 2007-08-10 20:26:18 +0200 | [diff] [blame] | 495 | nand->chip_delay = 0; |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 496 | #ifdef CONFIG_SYS_NAND_USE_FLASH_BBT |
Sandeep Paulraj | 77b351c | 2009-08-18 10:10:42 -0400 | [diff] [blame] | 497 | nand->options |= NAND_USE_FLASH_BBT; |
Sergey Kubushyn | c74b210 | 2007-08-10 20:26:18 +0200 | [diff] [blame] | 498 | #endif |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 499 | #ifdef CONFIG_SYS_NAND_HW_ECC |
William Juul | 5e1dae5 | 2007-11-09 13:32:30 +0100 | [diff] [blame] | 500 | nand->ecc.mode = NAND_ECC_HW; |
William Juul | 5e1dae5 | 2007-11-09 13:32:30 +0100 | [diff] [blame] | 501 | nand->ecc.size = 512; |
| 502 | nand->ecc.bytes = 3; |
William Juul | cfa460a | 2007-10-31 13:53:06 +0100 | [diff] [blame] | 503 | nand->ecc.calculate = nand_davinci_calculate_ecc; |
| 504 | nand->ecc.correct = nand_davinci_correct_data; |
William Juul | 4cbb651 | 2007-11-08 10:39:53 +0100 | [diff] [blame] | 505 | nand->ecc.hwctl = nand_davinci_enable_hwecc; |
Sergey Kubushyn | c74b210 | 2007-08-10 20:26:18 +0200 | [diff] [blame] | 506 | #else |
William Juul | 5e1dae5 | 2007-11-09 13:32:30 +0100 | [diff] [blame] | 507 | nand->ecc.mode = NAND_ECC_SOFT; |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 508 | #endif /* CONFIG_SYS_NAND_HW_ECC */ |
Sandeep Paulraj | 77b351c | 2009-08-18 10:10:42 -0400 | [diff] [blame] | 509 | #ifdef CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST |
| 510 | nand->ecc.mode = NAND_ECC_HW_OOB_FIRST; |
| 511 | nand->ecc.size = 512; |
| 512 | nand->ecc.bytes = 10; |
| 513 | nand->ecc.calculate = nand_davinci_4bit_calculate_ecc; |
| 514 | nand->ecc.correct = nand_davinci_4bit_correct_data; |
| 515 | nand->ecc.hwctl = nand_davinci_4bit_enable_hwecc; |
| 516 | nand->ecc.layout = &nand_davinci_4bit_layout_oobfirst; |
| 517 | #endif |
Sergey Kubushyn | c74b210 | 2007-08-10 20:26:18 +0200 | [diff] [blame] | 518 | /* Set address of hardware control function */ |
William Juul | cfa460a | 2007-10-31 13:53:06 +0100 | [diff] [blame] | 519 | nand->cmd_ctrl = nand_davinci_hwcontrol; |
Sergey Kubushyn | c74b210 | 2007-08-10 20:26:18 +0200 | [diff] [blame] | 520 | |
| 521 | nand->dev_ready = nand_davinci_dev_ready; |
Sergey Kubushyn | c74b210 | 2007-08-10 20:26:18 +0200 | [diff] [blame] | 522 | |
| 523 | nand_flash_init(); |
David Brownell | 154b548 | 2009-05-10 15:43:01 -0700 | [diff] [blame] | 524 | } |
Sergey Kubushyn | c74b210 | 2007-08-10 20:26:18 +0200 | [diff] [blame] | 525 | |
David Brownell | 154b548 | 2009-05-10 15:43:01 -0700 | [diff] [blame] | 526 | int board_nand_init(struct nand_chip *chip) __attribute__((weak)); |
| 527 | |
| 528 | int board_nand_init(struct nand_chip *chip) |
| 529 | { |
| 530 | davinci_nand_init(chip); |
| 531 | return 0; |
Sergey Kubushyn | c74b210 | 2007-08-10 20:26:18 +0200 | [diff] [blame] | 532 | } |