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Artur Rojek27347892023-10-18 16:00:59 +02001// SPDX-License-Identifier: GPL-2.0+ OR X11
2/*
3 * at91-kstr-sama5d27.dts - Device Tree file for Conclusive KSTR-SAMA5D27 board
4 *
5 * Copyright (C) 2019-2023 Conclusive Engineering Sp. z o. o.
6 *
7 */
8/dts-v1/;
9
10#include "sama5d2.dtsi"
11#include "sama5d2-pinfunc.h"
12#include <dt-bindings/gpio/gpio.h>
13#include <dt-bindings/interrupt-controller/irq.h>
14#include <dt-bindings/mfd/atmel-flexcom.h>
15
16/ {
17 model = "Conclusive KSTR-SAMA5D27";
18 compatible = "conclusive,kstr-sama5d27", "atmel,sama5d2", "atmel,sama5";
19
20 chosen {
21 stdout-path = &uart1;
22 };
23
24 aliases {
25 i2c2 = &i2c6;
26 };
27};
28
29&main_xtal {
30 clock-frequency = <12000000>;
31};
32
33&sdmmc0 {
34 bus-width = <4>;
35 pinctrl-names = "default";
36 pinctrl-0 = <&pinctrl_sdmmc0_cmd_dat_default &pinctrl_sdmmc0_ck_cd_default>;
37 status = "okay";
38};
39
40&uart1 {
41 pinctrl-names = "default";
42 pinctrl-0 = <&pinctrl_uart1_default>;
43 status = "okay";
44};
45
46&macb0 {
47 pinctrl-names = "default";
48 pinctrl-0 = <&pinctrl_macb0_rmii &pinctrl_macb0_phy_irq>;
49 phy-mode = "rmii";
50 status = "okay";
51
52 ethernet-phy@0 {
53 reg = <0x0>;
54 reset-gpios = <&pioA 44 GPIO_ACTIVE_LOW>;
55 };
56};
57
58&flx4 {
59 atmel,flexcom-mode = <ATMEL_FLEXCOM_MODE_TWI>;
60 status = "okay";
61};
62
63&i2c6 {
64 clock-frequency = <100000>;
65 pinctrl-names = "default";
66 pinctrl-0 = <&pinctrl_flx4_i2c>;
67 status = "okay";
68
69 eeprom: eeprom@50 {
70 compatible = "microchip,24c32", "atmel,24c32";
71 reg = <0x50>;
72 read-only;
73 pagesize = <32>;
74 status = "okay";
75 };
76};
77
78&pioA {
79 pinctrl {
80 pinctrl_uart1_default: uart1_default {
81 pinmux = <PIN_PD2__URXD1>,
82 <PIN_PD3__UTXD1>;
83 bias-disable;
84 };
85
86 pinctrl_macb0_phy_irq: macb0_phy_irq {
87 pinmux = <PIN_PB13__GPIO>;
88 bias-disable;
89 };
90
91 pinctrl_macb0_rmii: macb0_rmii {
92 pinmux = <PIN_PB14__GTXCK>,
93 <PIN_PB15__GTXEN>,
94 <PIN_PB16__GRXDV>,
95 <PIN_PB17__GRXER>,
96 <PIN_PB18__GRX0>,
97 <PIN_PB19__GRX1>,
98 <PIN_PB20__GTX0>,
99 <PIN_PB21__GTX1>,
100 <PIN_PB22__GMDC>,
101 <PIN_PB23__GMDIO>;
102 bias-disable;
103 };
104
105 pinctrl_sdmmc0_cmd_dat_default: sdmmc0_cmd_dat_default {
106 pinmux = <PIN_PA1__SDMMC0_CMD>,
107 <PIN_PA2__SDMMC0_DAT0>,
108 <PIN_PA3__SDMMC0_DAT1>,
109 <PIN_PA4__SDMMC0_DAT2>,
110 <PIN_PA5__SDMMC0_DAT3>;
111 bias-pull-up;
112 };
113
114 pinctrl_sdmmc0_ck_cd_default: sdmmc0_ck_cd_default {
115 pinmux = <PIN_PA0__SDMMC0_CK>,
116 <PIN_PA11__SDMMC0_VDDSEL>,
117 <PIN_PA13__SDMMC0_CD>;
118 bias-disable;
119 };
120
121 pinctrl_flx4_i2c: flx4_i2c {
122 pinmux = <PIN_PC28__FLEXCOM4_IO0>,
123 <PIN_PC29__FLEXCOM4_IO1>;
124 bias-disable;
125 };
126 };
127};