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wdenkf4675562002-10-02 14:20:15 +00001/*
wdenk414eec32005-04-02 22:37:54 +00002 * (C) Copyright 2000-2005
wdenkf4675562002-10-02 14:20:15 +00003 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/*
25 * board/config.h - configuration options, board specific
26 */
27
28#ifndef __CONFIG_H
29#define __CONFIG_H
30
31/*
32 * High Level Configuration Options
33 * (easy to change)
34 */
35
36#define CONFIG_MPC860 1 /* This is a MPC860 CPU */
37#define CONFIG_TQM860L 1 /* ...on a TQM8xxL module */
38
39#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
40#undef CONFIG_8xx_CONS_SMC2
41#undef CONFIG_8xx_CONS_NONE
42
43#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */
44
wdenkae3af052003-08-07 22:18:11 +000045#define CONFIG_BOOTCOUNT_LIMIT
wdenkf4675562002-10-02 14:20:15 +000046
wdenkae3af052003-08-07 22:18:11 +000047#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
wdenkf4675562002-10-02 14:20:15 +000048
49#define CONFIG_BOARD_TYPES 1 /* support board types */
50
51#define CONFIG_PREBOOT "echo;" \
wdenk6aff3112002-12-17 01:51:00 +000052 "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
53 "echo"
wdenkf4675562002-10-02 14:20:15 +000054
55#undef CONFIG_BOOTARGS
wdenk6aff3112002-12-17 01:51:00 +000056
57#define CONFIG_EXTRA_ENV_SETTINGS \
wdenkae3af052003-08-07 22:18:11 +000058 "netdev=eth0\0" \
wdenk6aff3112002-12-17 01:51:00 +000059 "nfsargs=setenv bootargs root=/dev/nfs rw " \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010060 "nfsroot=${serverip}:${rootpath}\0" \
wdenk6aff3112002-12-17 01:51:00 +000061 "ramargs=setenv bootargs root=/dev/ram rw\0" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010062 "addip=setenv bootargs ${bootargs} " \
63 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
64 ":${hostname}:${netdev}:off panic=1\0" \
wdenk6aff3112002-12-17 01:51:00 +000065 "flash_nfs=run nfsargs addip;" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010066 "bootm ${kernel_addr}\0" \
wdenk6aff3112002-12-17 01:51:00 +000067 "flash_self=run ramargs addip;" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010068 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
69 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
wdenk6aff3112002-12-17 01:51:00 +000070 "rootpath=/opt/eldk/ppc_8xx\0" \
wdenk3bac3512003-03-12 10:41:04 +000071 "bootfile=/tftpboot/TQM860L/uImage\0" \
wdenk6aff3112002-12-17 01:51:00 +000072 "kernel_addr=40040000\0" \
73 "ramdisk_addr=40100000\0" \
74 ""
75#define CONFIG_BOOTCOMMAND "run flash_self"
wdenkf4675562002-10-02 14:20:15 +000076
77#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
78#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */
79
80#undef CONFIG_WATCHDOG /* watchdog disabled */
81
82#define CONFIG_STATUS_LED 1 /* Status LED enabled */
83
84#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */
85
86#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
87
88#define CONFIG_MAC_PARTITION
89#define CONFIG_DOS_PARTITION
90
91#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
92
93#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
94 CFG_CMD_ASKENV | \
wdenkea287de2005-04-01 00:25:43 +000095 CFG_CMD_DATE | \
wdenkf4675562002-10-02 14:20:15 +000096 CFG_CMD_DHCP | \
wdenk66fd3d12003-05-18 11:30:09 +000097 CFG_CMD_ELF | \
wdenkf4675562002-10-02 14:20:15 +000098 CFG_CMD_IDE | \
wdenk414eec32005-04-02 22:37:54 +000099 CFG_CMD_NFS | \
wdenkea287de2005-04-01 00:25:43 +0000100 CFG_CMD_SNTP )
wdenkf4675562002-10-02 14:20:15 +0000101
wdenk68ceb292004-08-02 21:11:11 +0000102#define CONFIG_NETCONSOLE
103
wdenkf4675562002-10-02 14:20:15 +0000104/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
105#include <cmd_confdefs.h>
106
107/*
108 * Miscellaneous configurable options
109 */
110#define CFG_LONGHELP /* undef to save memory */
111#define CFG_PROMPT "=> " /* Monitor Command Prompt */
112
Wolfgang Denk2751a952006-10-28 02:29:14 +0200113#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
114#define CFG_HUSH_PARSER 1 /* Use the HUSH parser */
wdenkf4675562002-10-02 14:20:15 +0000115#ifdef CFG_HUSH_PARSER
116#define CFG_PROMPT_HUSH_PS2 "> "
117#endif
118
119#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
120#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
121#else
122#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
123#endif
124#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
125#define CFG_MAXARGS 16 /* max number of command args */
126#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
127
128#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
129#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
130
131#define CFG_LOAD_ADDR 0x100000 /* default load address */
132
133#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
134
135#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
136
137/*
138 * Low Level Configuration Settings
139 * (address mappings, register initial values, etc.)
140 * You should know what you are doing if you make changes here.
141 */
142/*-----------------------------------------------------------------------
143 * Internal Memory Mapped Register
144 */
145#define CFG_IMMR 0xFFF00000
146
147/*-----------------------------------------------------------------------
148 * Definitions for initial stack pointer and data area (in DPRAM)
149 */
150#define CFG_INIT_RAM_ADDR CFG_IMMR
151#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
152#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
153#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
154#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
155
156/*-----------------------------------------------------------------------
157 * Start addresses for the final memory configuration
158 * (Set up by the startup code)
159 * Please note that CFG_SDRAM_BASE _must_ start at 0
160 */
161#define CFG_SDRAM_BASE 0x00000000
162#define CFG_FLASH_BASE 0x40000000
163#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
164#define CFG_MONITOR_BASE CFG_FLASH_BASE
165#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
166
167/*
168 * For booting Linux, the board info and command line data
169 * have to be in the first 8 MB of memory, since this is
170 * the maximum mapped by the Linux kernel during initialization.
171 */
172#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
173
174/*-----------------------------------------------------------------------
175 * FLASH organization
176 */
177#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
wdenkaacf9a42003-01-17 16:27:01 +0000178#define CFG_MAX_FLASH_SECT 71 /* max number of sectors on one chip */
wdenkf4675562002-10-02 14:20:15 +0000179
180#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
181#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
182
183#define CFG_ENV_IS_IN_FLASH 1
184#define CFG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */
185#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
186
187/* Address and size of Redundant Environment Sector */
188#define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SIZE)
189#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
190
191/*-----------------------------------------------------------------------
192 * Hardware Information Block
193 */
194#define CFG_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */
195#define CFG_HWINFO_SIZE 0x00000040 /* size of HW Info block */
196#define CFG_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */
197
198/*-----------------------------------------------------------------------
199 * Cache Configuration
200 */
201#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
202#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
203#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
204#endif
205
206/*-----------------------------------------------------------------------
207 * SYPCR - System Protection Control 11-9
208 * SYPCR can only be written once after reset!
209 *-----------------------------------------------------------------------
210 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
211 */
212#if defined(CONFIG_WATCHDOG)
213#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
214 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
215#else
216#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
217#endif
218
219/*-----------------------------------------------------------------------
220 * SIUMCR - SIU Module Configuration 11-6
221 *-----------------------------------------------------------------------
222 * PCMCIA config., multi-function pin tri-state
223 */
224#ifndef CONFIG_CAN_DRIVER
225#define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
226#else /* we must activate GPL5 in the SIUMCR for CAN */
227#define CFG_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
228#endif /* CONFIG_CAN_DRIVER */
229
230/*-----------------------------------------------------------------------
231 * TBSCR - Time Base Status and Control 11-26
232 *-----------------------------------------------------------------------
233 * Clear Reference Interrupt Status, Timebase freezing enabled
234 */
235#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
236
237/*-----------------------------------------------------------------------
238 * RTCSC - Real-Time Clock Status and Control Register 11-27
239 *-----------------------------------------------------------------------
240 */
241#define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
242
243/*-----------------------------------------------------------------------
244 * PISCR - Periodic Interrupt Status and Control 11-31
245 *-----------------------------------------------------------------------
246 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
247 */
248#define CFG_PISCR (PISCR_PS | PISCR_PITF)
249
250/*-----------------------------------------------------------------------
251 * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
252 *-----------------------------------------------------------------------
253 * Reset PLL lock status sticky bit, timer expired status bit and timer
254 * interrupt status bit
wdenkf4675562002-10-02 14:20:15 +0000255 */
wdenkf4675562002-10-02 14:20:15 +0000256#define CFG_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
wdenkf4675562002-10-02 14:20:15 +0000257
258/*-----------------------------------------------------------------------
259 * SCCR - System Clock and reset Control Register 15-27
260 *-----------------------------------------------------------------------
261 * Set clock output, timebase and RTC source and divider,
262 * power management and some other internal clocks
263 */
264#define SCCR_MASK SCCR_EBDF11
wdenke9132ea2004-04-24 23:23:30 +0000265#define CFG_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
wdenkf4675562002-10-02 14:20:15 +0000266 SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
267 SCCR_DFALCD00)
wdenkf4675562002-10-02 14:20:15 +0000268
269/*-----------------------------------------------------------------------
270 * PCMCIA stuff
271 *-----------------------------------------------------------------------
272 *
273 */
274#define CFG_PCMCIA_MEM_ADDR (0xE0000000)
275#define CFG_PCMCIA_MEM_SIZE ( 64 << 20 )
276#define CFG_PCMCIA_DMA_ADDR (0xE4000000)
277#define CFG_PCMCIA_DMA_SIZE ( 64 << 20 )
278#define CFG_PCMCIA_ATTRB_ADDR (0xE8000000)
279#define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 )
280#define CFG_PCMCIA_IO_ADDR (0xEC000000)
281#define CFG_PCMCIA_IO_SIZE ( 64 << 20 )
282
283/*-----------------------------------------------------------------------
284 * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
285 *-----------------------------------------------------------------------
286 */
287
288#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
289
290#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
291#undef CONFIG_IDE_LED /* LED for ide not supported */
292#undef CONFIG_IDE_RESET /* reset for ide not supported */
293
294#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */
295#define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
296
297#define CFG_ATA_IDE0_OFFSET 0x0000
298
299#define CFG_ATA_BASE_ADDR CFG_PCMCIA_MEM_ADDR
300
301/* Offset for data I/O */
302#define CFG_ATA_DATA_OFFSET (CFG_PCMCIA_MEM_SIZE + 0x320)
303
304/* Offset for normal register accesses */
305#define CFG_ATA_REG_OFFSET (2 * CFG_PCMCIA_MEM_SIZE + 0x320)
306
307/* Offset for alternate registers */
308#define CFG_ATA_ALT_OFFSET 0x0100
309
310/*-----------------------------------------------------------------------
311 *
312 *-----------------------------------------------------------------------
313 *
314 */
wdenkf4675562002-10-02 14:20:15 +0000315#define CFG_DER 0
316
317/*
318 * Init Memory Controller:
319 *
320 * BR0/1 and OR0/1 (FLASH)
321 */
322
323#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
324#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */
325
326/* used to re-map FLASH both when starting from SRAM or FLASH:
327 * restrict access enough to keep SRAM working (if any)
328 * but not too much to meddle with FLASH accesses
329 */
330#define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */
331#define CFG_PRELIM_OR_AM 0xE0000000 /* OR addr mask */
332
333/*
334 * FLASH timing:
335 */
wdenkf4675562002-10-02 14:20:15 +0000336#define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \
337 OR_SCY_3_CLK | OR_EHTR | OR_BI)
wdenkf4675562002-10-02 14:20:15 +0000338
339#define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH)
340#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
341#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
342
343#define CFG_OR1_REMAP CFG_OR0_REMAP
344#define CFG_OR1_PRELIM CFG_OR0_PRELIM
345#define CFG_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V )
346
347/*
348 * BR2/3 and OR2/3 (SDRAM)
349 *
350 */
351#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */
352#define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */
353#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */
354
355/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
356#define CFG_OR_TIMING_SDRAM 0x00000A00
357
358#define CFG_OR2_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM )
359#define CFG_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
360
361#ifndef CONFIG_CAN_DRIVER
362#define CFG_OR3_PRELIM CFG_OR2_PRELIM
363#define CFG_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
364#else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */
365#define CFG_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */
366#define CFG_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */
367#define CFG_OR3_CAN (CFG_CAN_OR_AM | OR_G5LA | OR_BI)
368#define CFG_BR3_CAN ((CFG_CAN_BASE & BR_BA_MSK) | \
369 BR_PS_8 | BR_MS_UPMB | BR_V )
370#endif /* CONFIG_CAN_DRIVER */
371
372/*
373 * Memory Periodic Timer Prescaler
374 *
375 * The Divider for PTA (refresh timer) configuration is based on an
376 * example SDRAM configuration (64 MBit, one bank). The adjustment to
377 * the number of chip selects (NCS) and the actually needed refresh
378 * rate is done by setting MPTPR.
379 *
380 * PTA is calculated from
381 * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS)
382 *
383 * gclk CPU clock (not bus clock!)
384 * Trefresh Refresh cycle * 4 (four word bursts used)
385 *
386 * 4096 Rows from SDRAM example configuration
387 * 1000 factor s -> ms
388 * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration
389 * 4 Number of refresh cycles per period
390 * 64 Refresh cycle in ms per number of rows
391 * --------------------------------------------
392 * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000
393 *
394 * 50 MHz => 50.000.000 / Divider = 98
395 * 66 Mhz => 66.000.000 / Divider = 129
396 * 80 Mhz => 80.000.000 / Divider = 156
397 */
wdenke9132ea2004-04-24 23:23:30 +0000398
399#define CFG_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64))
400#define CFG_MAMR_PTA 98
wdenkf4675562002-10-02 14:20:15 +0000401
402/*
403 * For 16 MBit, refresh rates could be 31.3 us
404 * (= 64 ms / 2K = 125 / quad bursts).
405 * For a simpler initialization, 15.6 us is used instead.
406 *
407 * #define CFG_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks
408 * #define CFG_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank
409 */
410#define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
411#define CFG_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */
412
413/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
414#define CFG_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */
415#define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
416
417/*
418 * MAMR settings for SDRAM
419 */
420
421/* 8 column SDRAM */
422#define CFG_MAMR_8COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
423 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
424 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
425/* 9 column SDRAM */
426#define CFG_MAMR_9COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
427 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
428 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
429
430
431/*
432 * Internal Definitions
433 *
434 * Boot Flags
435 */
436#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
437#define BOOTFLAG_WARM 0x02 /* Software reboot */
438
439#define CONFIG_SCC1_ENET
440#define CONFIG_FEC_ENET
441#define CONFIG_ETHPRIME "SCC ETHERNET"
442
443#endif /* __CONFIG_H */