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Roy Zang3f7f6b82011-06-09 11:30:52 +08001Overview
2--------
3The P1023 process includes a performance optimized implementation of the
4QorIQ data Path Acceleration Architecture (DPAA). This architecture
5provides the infrastructure to support simplified sharing of networking
6interfaces and accelerators by multiple CPU cores. P1023 is an e500 based
7dual core SOC.
8
9P1023RDS board is a Low End Dual core platform supporting the P1023
10processor of QorIQ series.
11
12Building U-boot
13---------------
14To build the u-boot for P1023RDS:
15Configure to NOR boot:
16 make P1023RDS_config
17Configure to NAND boot:
18 make P1023RDS_NAND_config
19Build:
20 make
21
22Board Switches
23--------------
24Most switches on the board should not be changed. The most frequent
25user-settable switches on the board are used to configure
26the flash banks.
27
28J4: all open
29
30Default NOR flash boot switch setting:
31 Sw3[1:8]: off on on off on on off off
32 Sw4[1:8]: off off off on off off off off
33 Sw6[1:8]: off on off on off on on off
34 Sw7[1:8]: off on off off on off off off
35 Sw8[1:8]: on off off off off off off off
36
37For NAND flash boot,set
38Sw4[1:4]: off on on on
39
40The default native ethernet setting is for RGMII mode.
41To use SGMII mode, set
42SW8[1:2]: OFF OFF
43SW7[6:7]: ON ON
44
45Memory Map
46----------
470x0000_0000 0x7fff_ffff DDR 2G Cacheable
480x8000_0000 0xbfff_ffff PCI Express Mem 1G non-cacheable
490xc000_0000 0xdfff_ffff PCI 512M non-cacheable
500xe100_0000 0xe3ff_ffff PCI IO range 4M non-cacheable
51
520xe000_0000 0xe003_ffff BCSR 256K BCSR
530xee00_0000 0xefff_ffff NOR flash 32M NOR flash
540xff00_0000 0xff3f_ffff DPAA_QBMAN 4M
550xff60_0000 0xff7f_ffff CCSR 2M non-cacheable
560xffa0_0000 0xffaf_ffff NAND FLASH 1M non-cacheable
570xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0
58
59Flashing u-boot Images
60---------------
61To program the image in the boot flash bank:
62NOR flash boot:
63 => tftp 1000000 u-boot.bin
64 => protect off all
Prabhakar Kushwahae222b1f2014-01-14 11:34:26 +053065 => erase eff40000 efffffff
66 => cp.b 1000000 eff40000 c0000
Roy Zang3f7f6b82011-06-09 11:30:52 +080067
68NAND flash boot:
69 => tftp 1000000 u-boot-nand.bin
70 => nand erase 0 80000
71 => nand write 1000000 0 80000
72
73Firmware ucode location
74---------------------------------
75Microcode(ucode) to FMAN's IRAM is needed to make FMAN Ethernet work.
76u-boot loads ucode FLASH. The location for ucode:
77NOR Flash: 0xfe000000
78NAND Flash: 0x1f00000
79
80Using the Device Tree Source File
81---------------------------------
82To create the DTB (Device Tree Binary) image file,
83use a command similar to this:
84
85 dtc -b 0 -f -I dts -O dtb p1023rds.dts > p1023rds.dtb
86
87Likely, that .dts file will come from here;
88
89 linux-2.6/arch/powerpc/boot/dts/p1023rds.dts
90or
91 make p1023rds.dtb ARCH=powerpc
92in linux-2.6 directory.
93
94Booting Linux
95-------------
96Place a linux uImage in the TFTP disk area.
97
98 tftp 1000000 uImage
99 tftp 2000000 rootfs.ext2.gz.uboot
100 tftp c00000 p1023rds.dtb
101 bootm 1000000 2000000 c00000