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Stelian Popd99a8ff2008-05-08 20:52:22 +02001/*
2 * (C) Copyright 2007-2008
Stelian Popc9e798d2011-11-01 00:00:39 +01003 * Stelian Pop <stelian@popies.net>
Stelian Popd99a8ff2008-05-08 20:52:22 +02004 * Lead Tech Design <www.leadtechdesign.com>
5 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02006 * SPDX-License-Identifier: GPL-2.0+
Stelian Popd99a8ff2008-05-08 20:52:22 +02007 */
8
9#include <common.h>
Xu, Hongf7aea462011-07-31 22:49:00 +000010#include <asm/io.h>
Stelian Popd99a8ff2008-05-08 20:52:22 +020011#include <asm/arch/at91sam9261.h>
12#include <asm/arch/at91sam9261_matrix.h>
13#include <asm/arch/at91sam9_smc.h>
Jean-Christophe PLAGNIOL-VILLARD1332a2a2009-03-21 21:07:59 +010014#include <asm/arch/at91_common.h>
Stelian Popd99a8ff2008-05-08 20:52:22 +020015#include <asm/arch/at91_pmc.h>
16#include <asm/arch/at91_rstc.h>
Jean-Christophe PLAGNIOL-VILLARDdc39ae92009-04-16 21:30:44 +020017#include <asm/arch/clk.h>
Stelian Popd99a8ff2008-05-08 20:52:22 +020018#include <asm/arch/gpio.h>
Stelian Pop820f2a92008-05-08 14:52:30 +020019#include <lcd.h>
20#include <atmel_lcdc.h>
Stelian Popd99a8ff2008-05-08 20:52:22 +020021#if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_DRIVER_DM9000)
22#include <net.h>
Remy Bohmer60f61e62009-05-02 21:49:18 +020023#include <netdev.h>
Stelian Popd99a8ff2008-05-08 20:52:22 +020024#endif
25
26DECLARE_GLOBAL_DATA_PTR;
27
28/* ------------------------------------------------------------------------- */
29/*
30 * Miscelaneous platform dependent initialisations
31 */
32
Stelian Popd99a8ff2008-05-08 20:52:22 +020033#ifdef CONFIG_CMD_NAND
34static void at91sam9261ek_nand_hw_init(void)
35{
Xu, Hongf7aea462011-07-31 22:49:00 +000036 struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
37 struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
38 struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
Stelian Popd99a8ff2008-05-08 20:52:22 +020039 unsigned long csa;
40
41 /* Enable CS3 */
Xu, Hongf7aea462011-07-31 22:49:00 +000042 csa = readl(&matrix->ebicsa);
43 csa |= AT91_MATRIX_CS3A_SMC_SMARTMEDIA;
44
45 writel(csa, &matrix->ebicsa);
Stelian Popd99a8ff2008-05-08 20:52:22 +020046
47 /* Configure SMC CS3 for NAND/SmartMedia */
Sedji Gaouaou5ccc2d92009-06-25 17:04:15 +020048#ifdef CONFIG_AT91SAM9G10EK
Xu, Hongf7aea462011-07-31 22:49:00 +000049 writel(AT91_SMC_SETUP_NWE(2) | AT91_SMC_SETUP_NCS_WR(0) |
50 AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(0),
51 &smc->cs[3].setup);
52 writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(7) |
53 AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(7),
54 &smc->cs[3].pulse);
55 writel(AT91_SMC_CYCLE_NWE(7) | AT91_SMC_CYCLE_NRD(7),
56 &smc->cs[3].cycle);
Sedji Gaouaou5ccc2d92009-06-25 17:04:15 +020057#else
Xu, Hongf7aea462011-07-31 22:49:00 +000058 writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
59 AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
60 &smc->cs[3].setup);
61 writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) |
62 AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3),
63 &smc->cs[3].pulse);
64 writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5),
65 &smc->cs[3].cycle);
Sedji Gaouaou5ccc2d92009-06-25 17:04:15 +020066#endif
Xu, Hongf7aea462011-07-31 22:49:00 +000067 writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
68 AT91_SMC_MODE_EXNW_DISABLE |
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020069#ifdef CONFIG_SYS_NAND_DBW_16
Xu, Hongf7aea462011-07-31 22:49:00 +000070 AT91_SMC_MODE_DBW_16 |
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020071#else /* CONFIG_SYS_NAND_DBW_8 */
Xu, Hongf7aea462011-07-31 22:49:00 +000072 AT91_SMC_MODE_DBW_8 |
Stelian Popd99a8ff2008-05-08 20:52:22 +020073#endif
Xu, Hongf7aea462011-07-31 22:49:00 +000074 AT91_SMC_MODE_TDF_CYCLE(2),
75 &smc->cs[3].mode);
Stelian Popd99a8ff2008-05-08 20:52:22 +020076
Xu, Hongf7aea462011-07-31 22:49:00 +000077 writel(1 << ATMEL_ID_PIOC, &pmc->pcer);
Stelian Popd99a8ff2008-05-08 20:52:22 +020078
79 /* Configure RDY/BSY */
Jean-Christophe PLAGNIOL-VILLARD74c076d2009-03-22 10:22:34 +010080 at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
Stelian Popd99a8ff2008-05-08 20:52:22 +020081
82 /* Enable NandFlash */
Jean-Christophe PLAGNIOL-VILLARD74c076d2009-03-22 10:22:34 +010083 at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
Stelian Popd99a8ff2008-05-08 20:52:22 +020084
85 at91_set_A_periph(AT91_PIN_PC0, 0); /* NANDOE */
86 at91_set_A_periph(AT91_PIN_PC1, 0); /* NANDWE */
87}
88#endif
89
Stelian Popd99a8ff2008-05-08 20:52:22 +020090#ifdef CONFIG_DRIVER_DM9000
91static void at91sam9261ek_dm9000_hw_init(void)
92{
Xu, Hongf7aea462011-07-31 22:49:00 +000093 struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
94
Stelian Popd99a8ff2008-05-08 20:52:22 +020095 /* Configure SMC CS2 for DM9000 */
Sedji Gaouaou5ccc2d92009-06-25 17:04:15 +020096#ifdef CONFIG_AT91SAM9G10EK
Xu, Hongf7aea462011-07-31 22:49:00 +000097 writel(AT91_SMC_SETUP_NWE(3) | AT91_SMC_SETUP_NCS_WR(0) |
98 AT91_SMC_SETUP_NRD(3) | AT91_SMC_SETUP_NCS_RD(0),
99 &smc->cs[2].setup);
100 writel(AT91_SMC_PULSE_NWE(6) | AT91_SMC_PULSE_NCS_WR(8) |
101 AT91_SMC_PULSE_NRD(6) | AT91_SMC_PULSE_NCS_RD(8),
102 &smc->cs[2].pulse);
103 writel(AT91_SMC_CYCLE_NWE(20) | AT91_SMC_CYCLE_NRD(20),
104 &smc->cs[2].cycle);
105 writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
106 AT91_SMC_MODE_EXNW_DISABLE |
107 AT91_SMC_MODE_BAT | AT91_SMC_MODE_DBW_16 |
108 AT91_SMC_MODE_TDF_CYCLE(1),
109 &smc->cs[2].mode);
Sedji Gaouaou5ccc2d92009-06-25 17:04:15 +0200110#else
Xu, Hongf7aea462011-07-31 22:49:00 +0000111 writel(AT91_SMC_SETUP_NWE(3) | AT91_SMC_SETUP_NCS_WR(0) |
112 AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(0),
113 &smc->cs[2].setup);
114 writel(AT91_SMC_PULSE_NWE(4) | AT91_SMC_PULSE_NCS_WR(8) |
115 AT91_SMC_PULSE_NRD(4) | AT91_SMC_PULSE_NCS_RD(8),
116 &smc->cs[2].pulse);
117 writel(AT91_SMC_CYCLE_NWE(16) | AT91_SMC_CYCLE_NRD(16),
118 &smc->cs[2].cycle);
119 writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
120 AT91_SMC_MODE_EXNW_DISABLE |
121 AT91_SMC_MODE_BAT | AT91_SMC_MODE_DBW_16 |
122 AT91_SMC_MODE_TDF_CYCLE(1),
123 &smc->cs[2].mode);
Sedji Gaouaou5ccc2d92009-06-25 17:04:15 +0200124#endif
Stelian Popd99a8ff2008-05-08 20:52:22 +0200125
126 /* Configure Reset signal as output */
127 at91_set_gpio_output(AT91_PIN_PC10, 0);
128
129 /* Configure Interrupt pin as input, no pull-up */
130 at91_set_gpio_input(AT91_PIN_PC11, 0);
131}
132#endif
133
Stelian Pop820f2a92008-05-08 14:52:30 +0200134#ifdef CONFIG_LCD
135vidinfo_t panel_info = {
Jeroen Hofsteec346e462014-06-10 00:16:23 +0200136 .vl_col = 240,
137 .vl_row = 320,
138 .vl_clk = 4965000,
139 .vl_sync = ATMEL_LCDC_INVLINE_INVERTED |
140 ATMEL_LCDC_INVFRAME_INVERTED,
141 .vl_bpix = 3,
142 .vl_tft = 1,
143 .vl_hsync_len = 5,
144 .vl_left_margin = 1,
145 .vl_right_margin = 33,
146 .vl_vsync_len = 1,
147 .vl_upper_margin = 1,
148 .vl_lower_margin = 0,
149 .mmio = ATMEL_BASE_LCDC,
Stelian Pop820f2a92008-05-08 14:52:30 +0200150};
151
152void lcd_enable(void)
153{
154 at91_set_gpio_value(AT91_PIN_PA12, 0); /* power up */
155}
156
157void lcd_disable(void)
158{
159 at91_set_gpio_value(AT91_PIN_PA12, 1); /* power down */
160}
161
162static void at91sam9261ek_lcd_hw_init(void)
163{
Xu, Hongf7aea462011-07-31 22:49:00 +0000164 struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
165
Stelian Pop820f2a92008-05-08 14:52:30 +0200166 at91_set_A_periph(AT91_PIN_PB1, 0); /* LCDHSYNC */
167 at91_set_A_periph(AT91_PIN_PB2, 0); /* LCDDOTCK */
168 at91_set_A_periph(AT91_PIN_PB3, 0); /* LCDDEN */
169 at91_set_A_periph(AT91_PIN_PB4, 0); /* LCDCC */
170 at91_set_A_periph(AT91_PIN_PB7, 0); /* LCDD2 */
171 at91_set_A_periph(AT91_PIN_PB8, 0); /* LCDD3 */
172 at91_set_A_periph(AT91_PIN_PB9, 0); /* LCDD4 */
173 at91_set_A_periph(AT91_PIN_PB10, 0); /* LCDD5 */
174 at91_set_A_periph(AT91_PIN_PB11, 0); /* LCDD6 */
175 at91_set_A_periph(AT91_PIN_PB12, 0); /* LCDD7 */
176 at91_set_A_periph(AT91_PIN_PB15, 0); /* LCDD10 */
177 at91_set_A_periph(AT91_PIN_PB16, 0); /* LCDD11 */
178 at91_set_A_periph(AT91_PIN_PB17, 0); /* LCDD12 */
179 at91_set_A_periph(AT91_PIN_PB18, 0); /* LCDD13 */
180 at91_set_A_periph(AT91_PIN_PB19, 0); /* LCDD14 */
181 at91_set_A_periph(AT91_PIN_PB20, 0); /* LCDD15 */
182 at91_set_B_periph(AT91_PIN_PB23, 0); /* LCDD18 */
183 at91_set_B_periph(AT91_PIN_PB24, 0); /* LCDD19 */
184 at91_set_B_periph(AT91_PIN_PB25, 0); /* LCDD20 */
185 at91_set_B_periph(AT91_PIN_PB26, 0); /* LCDD21 */
186 at91_set_B_periph(AT91_PIN_PB27, 0); /* LCDD22 */
187 at91_set_B_periph(AT91_PIN_PB28, 0); /* LCDD23 */
188
Xu, Hongf7aea462011-07-31 22:49:00 +0000189 writel(AT91_PMC_HCK1, &pmc->scer);
Stelian Pop820f2a92008-05-08 14:52:30 +0200190
Xu, Hongf7aea462011-07-31 22:49:00 +0000191 /* For 9G10EK, let U-Boot allocate the framebuffer in SDRAM */
192#ifdef CONFIG_AT91SAM9261EK
193 gd->fb_base = ATMEL_BASE_SRAM;
Sedji Gaouaou5ccc2d92009-06-25 17:04:15 +0200194#endif
Stelian Pop820f2a92008-05-08 14:52:30 +0200195}
Haavard Skinnemoen6b59e032008-09-01 16:21:22 +0200196
197#ifdef CONFIG_LCD_INFO
198#include <nand.h>
199#include <version.h>
200
201void lcd_show_board_info(void)
202{
203 ulong dram_size, nand_size;
204 int i;
205 char temp[32];
206
207 lcd_printf ("%s\n", U_BOOT_VERSION);
208 lcd_printf ("(C) 2008 ATMEL Corp\n");
209 lcd_printf ("at91support@atmel.com\n");
210 lcd_printf ("%s CPU at %s MHz\n",
Xu, Hongf7aea462011-07-31 22:49:00 +0000211 ATMEL_CPU_NAME,
Jean-Christophe PLAGNIOL-VILLARDdc39ae92009-04-16 21:30:44 +0200212 strmhz(temp, get_cpu_clk_rate()));
Haavard Skinnemoen6b59e032008-09-01 16:21:22 +0200213
214 dram_size = 0;
215 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
216 dram_size += gd->bd->bi_dram[i].size;
217 nand_size = 0;
218 for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
219 nand_size += nand_info[i].size;
220 lcd_printf (" %ld MB SDRAM, %ld MB NAND\n",
221 dram_size >> 20,
222 nand_size >> 20 );
223}
224#endif /* CONFIG_LCD_INFO */
Stelian Pop820f2a92008-05-08 14:52:30 +0200225#endif
226
Stelian Popd99a8ff2008-05-08 20:52:22 +0200227int board_init(void)
228{
Sedji Gaouaou5ccc2d92009-06-25 17:04:15 +0200229#ifdef CONFIG_AT91SAM9G10EK
230 /* arch number of AT91SAM9G10EK-Board */
231 gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9G10EK;
232#else
Stelian Popd99a8ff2008-05-08 20:52:22 +0200233 /* arch number of AT91SAM9261EK-Board */
234 gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9261EK;
Sedji Gaouaou5ccc2d92009-06-25 17:04:15 +0200235#endif
Stelian Popd99a8ff2008-05-08 20:52:22 +0200236 /* adress of boot parameters */
Xu, Hongf7aea462011-07-31 22:49:00 +0000237 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
Stelian Popd99a8ff2008-05-08 20:52:22 +0200238
Xu, Hongf7aea462011-07-31 22:49:00 +0000239 at91_seriald_hw_init();
Stelian Popd99a8ff2008-05-08 20:52:22 +0200240#ifdef CONFIG_CMD_NAND
241 at91sam9261ek_nand_hw_init();
242#endif
243#ifdef CONFIG_HAS_DATAFLASH
Jean-Christophe PLAGNIOL-VILLARD7ebafb72009-03-21 21:07:59 +0100244 at91_spi0_hw_init(1 << 0);
Stelian Popd99a8ff2008-05-08 20:52:22 +0200245#endif
246#ifdef CONFIG_DRIVER_DM9000
247 at91sam9261ek_dm9000_hw_init();
248#endif
Stelian Pop820f2a92008-05-08 14:52:30 +0200249#ifdef CONFIG_LCD
250 at91sam9261ek_lcd_hw_init();
251#endif
Stelian Popd99a8ff2008-05-08 20:52:22 +0200252 return 0;
253}
254
Remy Bohmer60f61e62009-05-02 21:49:18 +0200255#ifdef CONFIG_DRIVER_DM9000
Wolfgang Denke8fac252009-12-07 21:06:40 +0100256int board_eth_init(bd_t *bis)
257{
Remy Bohmer60f61e62009-05-02 21:49:18 +0200258 return dm9000_initialize(bis);
Wolfgang Denke8fac252009-12-07 21:06:40 +0100259}
260#endif
261
Stelian Popd99a8ff2008-05-08 20:52:22 +0200262int dram_init(void)
263{
Xu, Hongf7aea462011-07-31 22:49:00 +0000264 gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
265 CONFIG_SYS_SDRAM_SIZE);
266
Stelian Popd99a8ff2008-05-08 20:52:22 +0200267 return 0;
268}
269
270#ifdef CONFIG_RESET_PHY_R
271void reset_phy(void)
272{
273#ifdef CONFIG_DRIVER_DM9000
274 /*
275 * Initialize ethernet HW addr prior to starting Linux,
276 * needed for nfsroot
277 */
Joe Hershbergerd2eaec62015-03-22 17:09:06 -0500278 eth_init();
Stelian Popd99a8ff2008-05-08 20:52:22 +0200279#endif
280}
281#endif