blob: 7626fee88ec4fd554f9129e203363b81e0414d61 [file] [log] [blame]
Wu, Josh9e336902013-04-16 23:42:44 +00001/*
2 * (C) Copyright 2013 Atmel Corporation.
3 * Josh Wu <josh.wu@atmel.com>
4 *
5 * Configuation settings for the AT91SAM9N12-EK boards.
6 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02007 * SPDX-License-Identifier: GPL-2.0+
Wu, Josh9e336902013-04-16 23:42:44 +00008 */
9
10#ifndef __AT91SAM9N12_CONFIG_H_
11#define __AT91SAM9N12_CONFIG_H_
12
Wu, Josh9e336902013-04-16 23:42:44 +000013/* ARM asynchronous clock */
14#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */
15#define CONFIG_SYS_AT91_MAIN_CLOCK 16000000 /* main clock xtal */
Wu, Josh9e336902013-04-16 23:42:44 +000016
17/* Misc CPU related */
18#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
19#define CONFIG_SETUP_MEMORY_TAGS
20#define CONFIG_INITRD_TAG
21#define CONFIG_SKIP_LOWLEVEL_INIT
Wu, Josh9e336902013-04-16 23:42:44 +000022
Wu, Josh9e336902013-04-16 23:42:44 +000023/* LCD */
Wu, Josh9e336902013-04-16 23:42:44 +000024#define LCD_BPP LCD_COLOR16
25#define LCD_OUTPUT_BPP 24
26#define CONFIG_LCD_LOGO
27#define CONFIG_LCD_INFO
28#define CONFIG_LCD_INFO_BELOW_LOGO
Wu, Josh9e336902013-04-16 23:42:44 +000029#define CONFIG_ATMEL_HLCD
30#define CONFIG_ATMEL_LCD_RGB565
Wu, Josh9e336902013-04-16 23:42:44 +000031
Wu, Josh9e336902013-04-16 23:42:44 +000032/*
33 * BOOTP options
34 */
35#define CONFIG_BOOTP_BOOTFILESIZE
36#define CONFIG_BOOTP_BOOTPATH
37#define CONFIG_BOOTP_GATEWAY
38#define CONFIG_BOOTP_HOSTNAME
39
Wu, Josh9e336902013-04-16 23:42:44 +000040#define CONFIG_NR_DRAM_BANKS 1
41#define CONFIG_SYS_SDRAM_BASE 0x20000000
42#define CONFIG_SYS_SDRAM_SIZE 0x08000000
43
44/*
45 * Initial stack pointer: 4k - GENERATED_GBL_DATA_SIZE in internal SRAM,
46 * leaving the correct space for initial global data structure above
47 * that address while providing maximum stack area below.
48 */
49# define CONFIG_SYS_INIT_SP_ADDR \
Wenyou Yange61ed482017-09-14 11:07:42 +080050 (0x00300000 + 16 * 1024 - GENERATED_GBL_DATA_SIZE)
Wu, Josh9e336902013-04-16 23:42:44 +000051
52/* DataFlash */
53#ifdef CONFIG_CMD_SF
Wu, Josh9e336902013-04-16 23:42:44 +000054#define CONFIG_SF_DEFAULT_SPEED 30000000
Wu, Josh9e336902013-04-16 23:42:44 +000055#endif
56
57/* NAND flash */
58#ifdef CONFIG_CMD_NAND
59#define CONFIG_NAND_ATMEL
60#define CONFIG_SYS_MAX_NAND_DEVICE 1
61#define CONFIG_SYS_NAND_BASE 0x40000000
62#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
63#define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
Andreas Bießmannac45bb12013-11-29 12:13:45 +010064#define CONFIG_SYS_NAND_ENABLE_PIN GPIO_PIN_PD(4)
65#define CONFIG_SYS_NAND_READY_PIN GPIO_PIN_PD(5)
Tom Rini8f1a80e2017-07-28 21:31:42 -040066#endif
Wu, Josh9e336902013-04-16 23:42:44 +000067
68/* PMECC & PMERRLOC */
69#define CONFIG_ATMEL_NAND_HWECC
70#define CONFIG_ATMEL_NAND_HW_PMECC
71#define CONFIG_PMECC_CAP 2
72#define CONFIG_PMECC_SECTOR_SIZE 512
Bo Shence76f0a2013-06-26 10:48:53 +080073
Wu, Josh9e336902013-04-16 23:42:44 +000074#define CONFIG_MTD_PARTITIONS
75#define CONFIG_MTD_DEVICE
Wu, Josh9e336902013-04-16 23:42:44 +000076
77#define CONFIG_EXTRA_ENV_SETTINGS \
78 "console=console=ttyS0,115200\0" \
Tom Rini43ede0b2017-10-22 17:55:07 -040079 "mtdparts="CONFIG_MTDPARTS_DEFAULT"\0" \
Wu, Josh9e336902013-04-16 23:42:44 +000080 "bootargs_nand=rootfstype=ubifs ubi.mtd=7 root=ubi0:rootfs rw\0"\
81 "bootargs_mmc=root=/dev/mmcblk0p2 rw rootfstype=ext4 rootwait\0"
82
Bo Shen16276222013-04-24 10:46:18 +080083/* Ethernet */
84#define CONFIG_KS8851_MLL
85#define CONFIG_KS8851_MLL_BASEADDR 0x30000000 /* use NCS2 */
86
Wu, Josh9e336902013-04-16 23:42:44 +000087#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */
88
89#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
90#define CONFIG_SYS_MEMTEST_END 0x26e00000
91
Bo Shend9bef0a2013-10-21 16:13:59 +080092/* USB host */
93#ifdef CONFIG_CMD_USB
94#define CONFIG_USB_ATMEL
Bo Shendcd2f1a2013-10-21 16:14:00 +080095#define CONFIG_USB_ATMEL_CLK_SEL_PLLB
Bo Shend9bef0a2013-10-21 16:13:59 +080096#define CONFIG_USB_OHCI_NEW
97#define CONFIG_SYS_USB_OHCI_CPU_INIT
98#define CONFIG_SYS_USB_OHCI_REGS_BASE ATMEL_BASE_OHCI
99#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9n12"
100#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 1
Bo Shend9bef0a2013-10-21 16:13:59 +0800101#endif
102
Wenyou Yang55415432017-09-14 11:07:44 +0800103#ifdef CONFIG_SPI_BOOT
Wu, Josh9e336902013-04-16 23:42:44 +0000104
105/* bootstrap + u-boot + env + linux in dataflash on CS0 */
Wu, Josh9e336902013-04-16 23:42:44 +0000106#define CONFIG_ENV_OFFSET 0x5000
107#define CONFIG_ENV_SIZE 0x3000
108#define CONFIG_ENV_SECT_SIZE 0x1000
109#define CONFIG_BOOTCOMMAND \
110 "setenv bootargs ${console} ${mtdparts} ${bootargs_nand};" \
111 "sf probe 0; sf read 0x22000000 0x100000 0x300000; " \
112 "bootm 0x22000000"
113
Wenyou Yang55415432017-09-14 11:07:44 +0800114#elif defined(CONFIG_NAND_BOOT)
Wu, Josh9e336902013-04-16 23:42:44 +0000115
116/* bootstrap + u-boot + env + linux in nandflash */
Wenyou Yang0ab54332017-04-18 14:54:51 +0800117#define CONFIG_ENV_OFFSET 0x120000
Wu, Josh9e336902013-04-16 23:42:44 +0000118#define CONFIG_ENV_OFFSET_REDUND 0x100000
119#define CONFIG_ENV_SIZE 0x20000 /* 1 sector = 128 kB */
120#define CONFIG_BOOTCOMMAND \
121 "setenv bootargs ${console} ${mtdparts} ${bootargs_nand};" \
122 "nand read 0x21000000 0x180000 0x080000;" \
123 "nand read 0x22000000 0x200000 0x400000;" \
124 "bootm 0x22000000 - 0x21000000"
125
Wenyou Yang55415432017-09-14 11:07:44 +0800126#else /* CONFIG_SD_BOOT */
Wu, Josh9e336902013-04-16 23:42:44 +0000127
128/* bootstrap + u-boot + env + linux in mmc */
Wu, Josh23ac62d2015-03-24 17:07:22 +0800129
130#ifdef CONFIG_ENV_IS_IN_MMC
131/* Use raw reserved sectors to save environment */
Wu, Josh9e336902013-04-16 23:42:44 +0000132#define CONFIG_ENV_OFFSET 0x2000
133#define CONFIG_ENV_SIZE 0x1000
134#define CONFIG_SYS_MMC_ENV_DEV 0
Wu, Josh23ac62d2015-03-24 17:07:22 +0800135#else
136/* Use file in FAT file to save environment */
Wu, Josh23ac62d2015-03-24 17:07:22 +0800137#define CONFIG_ENV_SIZE 0x4000
138#endif
139
Wu, Josh9e336902013-04-16 23:42:44 +0000140#define CONFIG_BOOTCOMMAND \
141 "setenv bootargs ${console} ${mtdparts} ${bootargs_mmc};" \
142 "fatload mmc 0:1 0x21000000 dtb;" \
143 "fatload mmc 0:1 0x22000000 uImage;" \
144 "bootm 0x22000000 - 0x21000000"
145
146#endif
147
Wu, Josh9e336902013-04-16 23:42:44 +0000148#define CONFIG_SYS_LONGHELP
149#define CONFIG_CMDLINE_EDITING
150#define CONFIG_AUTO_COMPLETE
Wu, Josh9e336902013-04-16 23:42:44 +0000151
152/*
153 * Size of malloc() pool
154 */
155#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
Bo Shenff255e82015-03-27 14:23:36 +0800156
157/* SPL */
158#define CONFIG_SPL_FRAMEWORK
159#define CONFIG_SPL_TEXT_BASE 0x300000
160#define CONFIG_SPL_MAX_SIZE 0x6000
161#define CONFIG_SPL_STACK 0x308000
162
163#define CONFIG_SPL_BSS_START_ADDR 0x20000000
164#define CONFIG_SPL_BSS_MAX_SIZE 0x80000
165#define CONFIG_SYS_SPL_MALLOC_START 0x20080000
166#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000
167
Bo Shenff255e82015-03-27 14:23:36 +0800168#define CONFIG_SYS_MONITOR_LEN (512 << 10)
169
170#define CONFIG_SYS_MASTER_CLOCK 132096000
171#define CONFIG_SYS_AT91_PLLA 0x20953f03
172#define CONFIG_SYS_MCKR 0x1301
173#define CONFIG_SYS_MCKR_CSS 0x1302
174
Wenyou Yang55415432017-09-14 11:07:44 +0800175#ifdef CONFIG_SD_BOOT
Bo Shenff255e82015-03-27 14:23:36 +0800176#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
177#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
Bo Shenff255e82015-03-27 14:23:36 +0800178
179#elif CONFIG_SYS_USE_NANDFLASH
Wenyou Yang55415432017-09-14 11:07:44 +0800180#elif CONFIG_SPI_BOOT
181#define CONFIG_SPL_SPI_LOAD
182#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x8400
183
184#elif CONFIG_NAND_BOOT
Bo Shenff255e82015-03-27 14:23:36 +0800185#define CONFIG_SPL_NAND_DRIVERS
186#define CONFIG_SPL_NAND_BASE
Wenyou Yang55415432017-09-14 11:07:44 +0800187#endif
Bo Shenff255e82015-03-27 14:23:36 +0800188#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000
189#define CONFIG_SYS_NAND_5_ADDR_CYCLE
190#define CONFIG_SYS_NAND_PAGE_SIZE 0x800
191#define CONFIG_SYS_NAND_PAGE_COUNT 64
192#define CONFIG_SYS_NAND_OOBSIZE 64
193#define CONFIG_SYS_NAND_BLOCK_SIZE 0x20000
194#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0x0
195#define CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER
196
Wu, Josh9e336902013-04-16 23:42:44 +0000197#endif