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Tom Rini83d290c2018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Mark Jonas3313e0e2008-03-10 11:37:10 +01002/*
3 * Configuation settings for MPR2
4 *
5 * Copyright (C) 2008
6 * Mark Jonas <mark.jonas@de.bosch.com>
Mark Jonas3313e0e2008-03-10 11:37:10 +01007 */
8
9#ifndef __MPR2_H
10#define __MPR2_H
11
12/* Supported commands */
Mark Jonas3313e0e2008-03-10 11:37:10 +010013
14/* Default environment variables */
Joe Hershbergerb3f44c22011-10-13 13:03:48 +000015#define CONFIG_BOOTFILE "/boot/zImage"
Mark Jonas3313e0e2008-03-10 11:37:10 +010016#define CONFIG_LOADADDR 0x8E000000
Mark Jonas3313e0e2008-03-10 11:37:10 +010017
18/* CPU and platform */
Mark Jonas3313e0e2008-03-10 11:37:10 +010019#define CONFIG_CPU_SH7720 1
Mark Jonas3313e0e2008-03-10 11:37:10 +010020
Vladimir Zapolskiy18a40e82016-11-28 00:15:30 +020021#define CONFIG_DISPLAY_BOARDINFO
22
Mark Jonas3313e0e2008-03-10 11:37:10 +010023/* U-Boot internals */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020024#define CONFIG_SYS_BAUDRATE_TABLE { 115200 } /* List of legal baudrate settings for this board */
25#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 32 * 1024 * 1024)
26#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
27#define CONFIG_SYS_MONITOR_LEN (128 * 1024)
28#define CONFIG_SYS_MALLOC_LEN (256 * 1024)
Mark Jonas3313e0e2008-03-10 11:37:10 +010029
30/* Memory */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020031#define CONFIG_SYS_SDRAM_BASE 0x8C000000
32#define CONFIG_SYS_SDRAM_SIZE (64 * 1024 * 1024)
33#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
34#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + (60 * 1024 * 1024))
Mark Jonas3313e0e2008-03-10 11:37:10 +010035
36/* Flash */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020037#define CONFIG_SYS_FLASH_CFI
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +020038#define CONFIG_FLASH_CFI_DRIVER
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020039#define CONFIG_SYS_FLASH_EMPTY_INFO
40#define CONFIG_SYS_FLASH_BASE 0xA0000000
41#define CONFIG_SYS_MAX_FLASH_SECT 256
42#define CONFIG_SYS_MAX_FLASH_BANKS 1
43#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +020044#define CONFIG_ENV_SECT_SIZE (128 * 1024)
45#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020046#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
47#define CONFIG_SYS_FLASH_ERASE_TOUT 120000
48#define CONFIG_SYS_FLASH_WRITE_TOUT 500
Mark Jonas3313e0e2008-03-10 11:37:10 +010049
50/* Clocks */
51#define CONFIG_SYS_CLK_FREQ 24000000
Nobuhiro Iwamatsu684a5012013-08-21 16:11:21 +090052#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
53#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
Jean-Christophe PLAGNIOL-VILLARDbe45c632009-06-04 12:06:48 +020054#define CONFIG_SYS_TMU_CLK_DIV 4 /* 4 (default), 16, 64, 256 or 1024 */
Mark Jonas3313e0e2008-03-10 11:37:10 +010055
56/* UART */
Mark Jonas3313e0e2008-03-10 11:37:10 +010057#define CONFIG_CONS_SCIF0 1
58
59#endif /* __MPR2_H */