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wdenk7d393ae2002-10-25 21:08:05 +00001/*
2 * (C) Copyright 2001, 2002
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/*
25 * board/config.h - configuration options, board specific
26 */
27
28#ifndef __CONFIG_H
29#define __CONFIG_H
30
31/***********************************************************
32 * High Level Configuration Options
33 * (easy to change)
34 ***********************************************************/
35#define CONFIG_405GP 1 /* This is a PPC405 CPU */
36#define CONFIG_4xx 1 /* ...member of PPC4xx family */
37#define CONFIG_MIP405 1 /* ...on a MIP405 board */
Wolfgang Denk2ae18242010-10-06 09:05:45 +020038
39#define CONFIG_SYS_TEXT_BASE 0xFFF80000
40
wdenk7d393ae2002-10-25 21:08:05 +000041/***********************************************************
wdenkf3e0de62003-06-04 15:05:30 +000042 * Note that it may also be a MIP405T board which is a subset of the
43 * MIP405
44 ***********************************************************/
45/***********************************************************
46 * WARNING:
47 * CONFIG_BOOT_PCI is only used for first boot-up and should
48 * NOT be enabled for production bootloader
49 ***********************************************************/
wdenk8bde7f72003-06-27 21:31:46 +000050/*#define CONFIG_BOOT_PCI 1*/
wdenkf3e0de62003-06-04 15:05:30 +000051/***********************************************************
wdenk7d393ae2002-10-25 21:08:05 +000052 * Clock
53 ***********************************************************/
54#define CONFIG_SYS_CLK_FREQ 33000000 /* external frequency to pll */
55
wdenk7d393ae2002-10-25 21:08:05 +000056
Jon Loeliger8353e132007-07-08 14:14:17 -050057/*
Jon Loeliger659e2f62007-07-10 09:10:49 -050058 * BOOTP options
59 */
60#define CONFIG_BOOTP_BOOTFILESIZE
61#define CONFIG_BOOTP_BOOTPATH
62#define CONFIG_BOOTP_GATEWAY
63#define CONFIG_BOOTP_HOSTNAME
64
65
66/*
Jon Loeliger8353e132007-07-08 14:14:17 -050067 * Command line configuration.
68 */
69#include <config_cmd_default.h>
wdenkf3e0de62003-06-04 15:05:30 +000070
Jon Loeliger8353e132007-07-08 14:14:17 -050071#define CONFIG_CMD_CACHE
72#define CONFIG_CMD_DATE
73#define CONFIG_CMD_DHCP
74#define CONFIG_CMD_EEPROM
75#define CONFIG_CMD_ELF
76#define CONFIG_CMD_FAT
77#define CONFIG_CMD_I2C
78#define CONFIG_CMD_IDE
79#define CONFIG_CMD_IRQ
80#define CONFIG_CMD_JFFS2
81#define CONFIG_CMD_MII
82#define CONFIG_CMD_PCI
83#define CONFIG_CMD_PING
84#define CONFIG_CMD_REGINFO
85#define CONFIG_CMD_SAVES
86#define CONFIG_CMD_BSP
87
88#if !defined(CONFIG_MIP405T)
89 #define CONFIG_CMD_USB
wdenkf3e0de62003-06-04 15:05:30 +000090#endif
91
wdenk7d393ae2002-10-25 21:08:05 +000092
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020093#define CONFIG_SYS_HUSH_PARSER
94#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
wdenk7d393ae2002-10-25 21:08:05 +000095/**************************************************************
96 * I2C Stuff:
97 * the MIP405 is equiped with an Atmel 24C128/256 EEPROM at address
98 * 0x53.
99 * The Atmel EEPROM uses 16Bit addressing.
100 ***************************************************************/
101
102#define CONFIG_HARD_I2C /* I2c with hardware support */
Stefan Roesed0b0dca2010-04-01 14:37:24 +0200103#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200104#define CONFIG_SYS_I2C_SPEED 50000 /* I2C speed and slave address */
105#define CONFIG_SYS_I2C_SLAVE 0x7F
wdenk7d393ae2002-10-25 21:08:05 +0000106
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200107#define CONFIG_SYS_I2C_EEPROM_ADDR 0x53 /* EEPROM 24C128/256 */
108#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* Bytes of address */
wdenk7d393ae2002-10-25 21:08:05 +0000109/* mask of address bits that overflow into the "EEPROM chip address" */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200110#undef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
111#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 /* The Atmel 24C128/256 has */
wdenk7d393ae2002-10-25 21:08:05 +0000112 /* 64 byte page write mode using*/
113 /* last 6 bits of the address */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200114#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
wdenk7d393ae2002-10-25 21:08:05 +0000115
116
Jean-Christophe PLAGNIOL-VILLARDbb1f8b42008-09-05 09:19:30 +0200117#define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200118#define CONFIG_ENV_OFFSET 0x00000 /* environment starts at the beginning of the EEPROM */
119#define CONFIG_ENV_SIZE 0x00800 /* 2k bytes may be used for env vars */
wdenk7d393ae2002-10-25 21:08:05 +0000120
121/***************************************************************
122 * Definitions for Serial Presence Detect EEPROM address
123 * (to get SDRAM settings)
124 ***************************************************************/
wdenkf3e0de62003-06-04 15:05:30 +0000125/*#define SDRAM_EEPROM_WRITE_ADDRESS 0xA0
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200126#define SDRAM_EEPROM_READ_ADDRESS 0xA1
wdenkf3e0de62003-06-04 15:05:30 +0000127*/
wdenk7d393ae2002-10-25 21:08:05 +0000128/**************************************************************
129 * Environment definitions
130 **************************************************************/
131#define CONFIG_BAUDRATE 9600 /* STD Baudrate */
132#define CONFIG_BOOTDELAY 5
133/* autoboot (do NOT change this set environment variable "bootdelay" to -1 instead) */
Wolfgang Denk2afbe4e2005-08-13 02:04:37 +0200134/* #define CONFIG_BOOT_RETRY_TIME -10 /XXX* feature is available but not enabled */
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200135#define CONFIG_ZERO_BOOTDELAY_CHECK /* check console even if bootdelay = 0 */
wdenk7d393ae2002-10-25 21:08:05 +0000136
wdenk3e386912003-04-05 00:53:31 +0000137#define CONFIG_BOOTCOMMAND "diskboot 400000 0:1; bootm" /* autoboot command */
wdenk7d393ae2002-10-25 21:08:05 +0000138#define CONFIG_BOOTARGS "console=ttyS0,9600 root=/dev/hda5" /* boot arguments */
139
140#define CONFIG_IPADDR 10.0.0.100
141#define CONFIG_SERVERIP 10.0.0.1
142#define CONFIG_PREBOOT
143/***************************************************************
144 * defines if the console is stored in the environment
145 ***************************************************************/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200146#define CONFIG_SYS_CONSOLE_IS_IN_ENV /* stdin, stdout and stderr are in evironment */
wdenk7d393ae2002-10-25 21:08:05 +0000147/***************************************************************
148 * defines if an overwrite_console function exists
149 *************************************************************/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200150#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
151#define CONFIG_SYS_CONSOLE_INFO_QUIET
wdenk7d393ae2002-10-25 21:08:05 +0000152/***************************************************************
153 * defines if the overwrite_console should be stored in the
154 * environment
155 **************************************************************/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200156#undef CONFIG_SYS_CONSOLE_ENV_OVERWRITE
wdenk7d393ae2002-10-25 21:08:05 +0000157
158/**************************************************************
159 * loads config
160 *************************************************************/
161#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200162#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
wdenk7d393ae2002-10-25 21:08:05 +0000163
164#define CONFIG_MISC_INIT_R
165/***********************************************************
166 * Miscellaneous configurable options
167 **********************************************************/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200168#define CONFIG_SYS_LONGHELP /* undef to save memory */
169#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
Jon Loeliger8353e132007-07-08 14:14:17 -0500170#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200171#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
wdenk7d393ae2002-10-25 21:08:05 +0000172#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200173#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
wdenk7d393ae2002-10-25 21:08:05 +0000174#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200175#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
176#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
177#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
wdenk7d393ae2002-10-25 21:08:05 +0000178
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200179#define CONFIG_SYS_MEMTEST_START 0x0100000 /* memtest works on */
180#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 1 ... 12 MB in DRAM */
wdenk7d393ae2002-10-25 21:08:05 +0000181
Stefan Roese550650d2010-09-20 16:05:31 +0200182#define CONFIG_CONS_INDEX 1 /* Use UART0 */
183#define CONFIG_SYS_NS16550
184#define CONFIG_SYS_NS16550_SERIAL
185#define CONFIG_SYS_NS16550_REG_SIZE 1
186#define CONFIG_SYS_NS16550_CLK get_serial_clock()
187
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200188#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */
189#define CONFIG_SYS_BASE_BAUD 916667
wdenk7d393ae2002-10-25 21:08:05 +0000190
191/* The following table includes the supported baudrates */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200192#define CONFIG_SYS_BAUDRATE_TABLE \
wdenk7d393ae2002-10-25 21:08:05 +0000193 { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \
194 57600, 115200, 230400, 460800, 921600 }
195
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200196#define CONFIG_SYS_LOAD_ADDR 0x400000 /* default load address */
197#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */
wdenk7d393ae2002-10-25 21:08:05 +0000198
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200199#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
wdenk7d393ae2002-10-25 21:08:05 +0000200
201/*-----------------------------------------------------------------------
202 * PCI stuff
203 *-----------------------------------------------------------------------
204 */
205#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */
206#define PCI_HOST_FORCE 1 /* configure as pci host */
207#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
208
209#define CONFIG_PCI /* include pci support */
210#define CONFIG_PCI_HOST PCI_HOST_FORCE /* configure as pci-host */
211#define CONFIG_PCI_PNP /* pci plug-and-play */
212 /* resource configuration */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200213#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x0000 /* PCI Vendor ID: to-do!!! */
214#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0000 /* PCI Device ID: to-do!!! */
215#define CONFIG_SYS_PCI_PTM1LA 0x00000000 /* point to sdram */
216#define CONFIG_SYS_PCI_PTM1MS 0x80000001 /* 2GB, enable hard-wired to 1 */
217#define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
218#define CONFIG_SYS_PCI_PTM2LA 0x00000000 /* disabled */
219#define CONFIG_SYS_PCI_PTM2MS 0x00000000 /* disabled */
220#define CONFIG_SYS_PCI_PTM2PCI 0x00000000 /* Host: use this pci address */
wdenk7d393ae2002-10-25 21:08:05 +0000221
222/*-----------------------------------------------------------------------
223 * Start addresses for the final memory configuration
224 * (Set up by the startup code)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200225 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
wdenk7d393ae2002-10-25 21:08:05 +0000226 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200227#define CONFIG_SYS_SDRAM_BASE 0x00000000
228#define CONFIG_SYS_FLASH_BASE 0xFFF80000
229#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
230#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Monitor */
231#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserve 1024 kB for malloc() */
wdenk7d393ae2002-10-25 21:08:05 +0000232
233/*
234 * For booting Linux, the board info and command line data
235 * have to be in the first 8 MB of memory, since this is
236 * the maximum mapped by the Linux kernel during initialization.
237 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200238#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
wdenk7d393ae2002-10-25 21:08:05 +0000239/*-----------------------------------------------------------------------
240 * FLASH organization
241 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200242#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
243#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
wdenk7d393ae2002-10-25 21:08:05 +0000244
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200245#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
246#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
wdenk7d393ae2002-10-25 21:08:05 +0000247
Wolfgang Denk700a0c62005-08-08 01:03:24 +0200248/*
249 * JFFS2 partitions
250 *
251 */
252/* No command line, one static partition, whole device */
Stefan Roese68d7d652009-03-19 13:30:36 +0100253#undef CONFIG_CMD_MTDPARTS
Wolfgang Denk700a0c62005-08-08 01:03:24 +0200254#define CONFIG_JFFS2_DEV "nor0"
255#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF
256#define CONFIG_JFFS2_PART_OFFSET 0x00000000
257
258/* mtdparts command line support */
259/* Note: fake mtd_id used, no linux mtd map file */
260/*
Stefan Roese68d7d652009-03-19 13:30:36 +0100261#define CONFIG_CMD_MTDPARTS
Wolfgang Denk700a0c62005-08-08 01:03:24 +0200262#define MTDIDS_DEFAULT "nor0=mip405-0"
263#define MTDPARTS_DEFAULT "mtdparts=mip405-0:-(jffs2)"
264*/
wdenk63e73c92004-02-23 22:22:28 +0000265
wdenk7d393ae2002-10-25 21:08:05 +0000266/*-----------------------------------------------------------------------
wdenk63e73c92004-02-23 22:22:28 +0000267 * Logbuffer Configuration
268 */
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200269#undef CONFIG_LOGBUFFER /* supported but not enabled */
wdenk63e73c92004-02-23 22:22:28 +0000270/*-----------------------------------------------------------------------
271 * Bootcountlimit Configuration
272 */
273#undef CONFIG_BOOTCOUNT_LIMIT /* supported but not enabled */
274
275/*-----------------------------------------------------------------------
276 * POST Configuration
277 */
278#if 0 /* enable this if POST is desired (is supported but not enabled) */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200279#define CONFIG_POST (CONFIG_SYS_POST_MEMORY | \
280 CONFIG_SYS_POST_CPU | \
281 CONFIG_SYS_POST_RTC | \
282 CONFIG_SYS_POST_I2C)
wdenk63e73c92004-02-23 22:22:28 +0000283
284#endif
wdenk7d393ae2002-10-25 21:08:05 +0000285/*
286 * Init Memory Controller:
287 */
wdenk7205e402003-09-10 22:30:53 +0000288#define FLASH_MAX_SIZE 0x00800000 /* 8MByte max */
289#define FLASH_BASE_PRELIM 0xFF800000 /* open the flash CS */
290/* Size: 0=1MB, 1=2MB, 2=4MB, 3=8MB, 4=16MB, 5=32MB, 6=64MB, 7=128MB */
291#define FLASH_SIZE_PRELIM 3 /* maximal flash FLASH size bank #0 */
wdenk7d393ae2002-10-25 21:08:05 +0000292
wdenkc837dcb2004-01-20 23:12:12 +0000293#define CONFIG_BOARD_EARLY_INIT_F 1
wdenk7d393ae2002-10-25 21:08:05 +0000294
295/* Peripheral Bus Mapping */
296#define PER_PLD_ADDR 0xF4000000 /* smallest window is 1MByte 0x10 0000*/
297#define PER_UART0_ADDR 0xF4100000 /* smallest window is 1MByte 0x10 0000*/
298#define PER_UART1_ADDR 0xF4200000 /* smallest window is 1MByte 0x10 0000*/
299
300#define MULTI_PURPOSE_SOCKET_ADDR 0xF8000000
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200301#define CONFIG_PORT_ADDR PER_PLD_ADDR + 5
wdenk7d393ae2002-10-25 21:08:05 +0000302
303
wdenk7d393ae2002-10-25 21:08:05 +0000304/*-----------------------------------------------------------------------
305 * Definitions for initial stack pointer and data area (in On Chip SRAM)
306 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200307#define CONFIG_SYS_TEMP_STACK_OCM 1
308#define CONFIG_SYS_OCM_DATA_ADDR 0xF0000000
309#define CONFIG_SYS_OCM_DATA_SIZE 0x1000
310#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of On Chip SRAM */
Wolfgang Denk553f0982010-10-26 13:32:32 +0200311#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE /* Size of On Chip SRAM */
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200312#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
wdenk63e73c92004-02-23 22:22:28 +0000313/* reserve some memory for POST and BOOT limit info */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200314#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_GBL_DATA_OFFSET - 32)
wdenk63e73c92004-02-23 22:22:28 +0000315
wdenk63e73c92004-02-23 22:22:28 +0000316#ifdef CONFIG_BOOTCOUNT_LIMIT /* reserve 2 word for bootcount limit */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200317#define CONFIG_SYS_BOOTCOUNT_ADDR (CONFIG_SYS_GBL_DATA_OFFSET - 12)
wdenk63e73c92004-02-23 22:22:28 +0000318#endif
wdenk7d393ae2002-10-25 21:08:05 +0000319
wdenk7d393ae2002-10-25 21:08:05 +0000320/***********************************************************************
321 * External peripheral base address
322 ***********************************************************************/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200323#define CONFIG_SYS_ISA_IO_BASE_ADDRESS 0xE8000000
wdenk7d393ae2002-10-25 21:08:05 +0000324
325/***********************************************************************
326 * Last Stage Init
327 ***********************************************************************/
328#define CONFIG_LAST_STAGE_INIT
329/************************************************************
330 * Ethernet Stuff
331 ***********************************************************/
Ben Warren96e21f82008-10-27 23:50:15 -0700332#define CONFIG_PPC4xx_EMAC
wdenk7d393ae2002-10-25 21:08:05 +0000333#define CONFIG_MII 1 /* MII PHY management */
334#define CONFIG_PHY_ADDR 1 /* PHY address */
wdenk63e73c92004-02-23 22:22:28 +0000335#define CONFIG_PHY_RESET_DELAY 300 /* Intel LXT971A needs this */
336#define CONFIG_PHY_CMD_DELAY 40 /* Intel LXT971A needs this */
wdenk7d393ae2002-10-25 21:08:05 +0000337/************************************************************
338 * RTC
339 ***********************************************************/
340#define CONFIG_RTC_MC146818
341#undef CONFIG_WATCHDOG /* watchdog disabled */
342
343/************************************************************
344 * IDE/ATA stuff
345 ************************************************************/
wdenkf3e0de62003-06-04 15:05:30 +0000346#if defined(CONFIG_MIP405T)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200347#define CONFIG_SYS_IDE_MAXBUS 1 /* MIP405T has only one IDE bus */
wdenkf3e0de62003-06-04 15:05:30 +0000348#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200349#define CONFIG_SYS_IDE_MAXBUS 2 /* max. 2 IDE busses */
wdenkf3e0de62003-06-04 15:05:30 +0000350#endif
351
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200352#define CONFIG_SYS_IDE_MAXDEVICE (CONFIG_SYS_IDE_MAXBUS*2) /* max. 2 drives per IDE bus */
wdenk7d393ae2002-10-25 21:08:05 +0000353
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200354#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_ISA_IO_BASE_ADDRESS /* base address */
355#define CONFIG_SYS_ATA_IDE0_OFFSET 0x01F0 /* ide0 offste */
356#define CONFIG_SYS_ATA_IDE1_OFFSET 0x0170 /* ide1 offset */
357#define CONFIG_SYS_ATA_DATA_OFFSET 0 /* data reg offset */
358#define CONFIG_SYS_ATA_REG_OFFSET 0 /* reg offset */
359#define CONFIG_SYS_ATA_ALT_OFFSET 0x200 /* alternate register offset */
wdenk7d393ae2002-10-25 21:08:05 +0000360
361#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */
362#undef CONFIG_IDE_LED /* no led for ide supported */
363#define CONFIG_IDE_RESET /* reset for ide supported... */
364#define CONFIG_IDE_RESET_ROUTINE /* with a special reset function */
wdenk7205e402003-09-10 22:30:53 +0000365#define CONFIG_SUPPORT_VFAT
wdenk7d393ae2002-10-25 21:08:05 +0000366/************************************************************
367 * ATAPI support (experimental)
368 ************************************************************/
369#define CONFIG_ATAPI /* enable ATAPI Support */
370
371/************************************************************
wdenk7d393ae2002-10-25 21:08:05 +0000372 * DISK Partition support
373 ************************************************************/
374#define CONFIG_DOS_PARTITION
375#define CONFIG_MAC_PARTITION
376#define CONFIG_ISO_PARTITION /* Experimental */
377
378/************************************************************
wdenk7d393ae2002-10-25 21:08:05 +0000379 * Keyboard support
380 ************************************************************/
381#undef CONFIG_ISA_KEYBOARD
382
383/************************************************************
384 * Video support
385 ************************************************************/
386#define CONFIG_VIDEO /*To enable video controller support */
387#define CONFIG_VIDEO_CT69000
388#define CONFIG_CFB_CONSOLE
389#define CONFIG_VIDEO_LOGO
390#define CONFIG_CONSOLE_EXTRA_INFO
391#define CONFIG_VGA_AS_SINGLE_DEVICE
392#define CONFIG_VIDEO_SW_CURSOR
393#undef CONFIG_VIDEO_ONBOARD
394/************************************************************
395 * USB support EXPERIMENTAL
396 ************************************************************/
wdenkf3e0de62003-06-04 15:05:30 +0000397#if !defined(CONFIG_MIP405T)
wdenk7d393ae2002-10-25 21:08:05 +0000398#define CONFIG_USB_UHCI
399#define CONFIG_USB_KEYBOARD
400#define CONFIG_USB_STORAGE
401
402/* Enable needed helper functions */
Jean-Christophe PLAGNIOL-VILLARD52cb4d42009-05-16 12:14:54 +0200403#define CONFIG_SYS_STDIO_DEREGISTER /* needs stdio_deregister */
wdenkf3e0de62003-06-04 15:05:30 +0000404#endif
wdenk7d393ae2002-10-25 21:08:05 +0000405/************************************************************
406 * Debug support
407 ************************************************************/
Jon Loeliger8353e132007-07-08 14:14:17 -0500408#if defined(CONFIG_CMD_KGDB)
wdenk7d393ae2002-10-25 21:08:05 +0000409#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
410#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
411#endif
412
413/************************************************************
wdenka2663ea2003-12-07 18:32:37 +0000414 * support BZIP2 compression
415 ************************************************************/
416#define CONFIG_BZIP2 1
417
418/************************************************************
wdenk7d393ae2002-10-25 21:08:05 +0000419 * Ident
420 ************************************************************/
wdenkf3e0de62003-06-04 15:05:30 +0000421
wdenk7d393ae2002-10-25 21:08:05 +0000422#define VERSION_TAG "released"
wdenkf3e0de62003-06-04 15:05:30 +0000423#if !defined(CONFIG_MIP405T)
424#define CONFIG_ISO_STRING "MEV-10072-001"
425#else
426#define CONFIG_ISO_STRING "MEV-10082-001"
427#endif
428
429#if !defined(CONFIG_BOOT_PCI)
430#define CONFIG_IDENT_STRING "\n(c) 2003 by MPL AG Switzerland, " CONFIG_ISO_STRING " " VERSION_TAG
431#else
432#define CONFIG_IDENT_STRING "\n(c) 2003 by MPL AG Switzerland, PCI_BOOT Version"
433#endif
wdenk7d393ae2002-10-25 21:08:05 +0000434
435
436#endif /* __CONFIG_H */