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gerrit.devboardsforandroid.linaro.org / platform / external / u-boot / 27d170af17bf17ccc3529bc460da0632a574b819 / . / board / ti / dra7xx / mux_data.h
blob: c9301a51c0ac64eb873aa2d24d59e4a3fdb10758 [file] [log] [blame]
Lokesh Vutla687054a2013-02-12 21:29:08 +0000[diff] [blame]1/*
2 * (C) Copyright 2013
3 * Texas Instruments Incorporated, <www.ti.com>
4 *
5 * Sricharan R <r.sricharan@ti.com>
6 * Nishant Kamat <nskamat@ti.com>
7 *
Wolfgang Denk1a459662013-07-08 09:37:19 +0200[diff] [blame]8 * SPDX-License-Identifier: GPL-2.0+
Lokesh Vutla687054a2013-02-12 21:29:08 +0000[diff] [blame]9 */
10#ifndef _MUX_DATA_DRA7XX_H_
11#define _MUX_DATA_DRA7XX_H_
12
13#include <asm/arch/mux_dra7xx.h>
14
15const struct pad_conf_entry core_padconf_array_essential[] = {
Lokesh Vutla7f36c882013-05-30 03:19:37 +0000[diff] [blame]16 {MMC1_CLK, (IEN | PTU | PDIS | M0)}, /* MMC1_CLK */
17 {MMC1_CMD, (IEN | PTU | PDIS | M0)}, /* MMC1_CMD */
18 {MMC1_DAT0, (IEN | PTU | PDIS | M0)}, /* MMC1_DAT0 */
19 {MMC1_DAT1, (IEN | PTU | PDIS | M0)}, /* MMC1_DAT1 */
20 {MMC1_DAT2, (IEN | PTU | PDIS | M0)}, /* MMC1_DAT2 */
21 {MMC1_DAT3, (IEN | PTU | PDIS | M0)}, /* MMC1_DAT3 */
22 {MMC1_SDCD, (FSC | IEN | PTU | PDIS | M0)}, /* MMC1_SDCD */
23 {MMC1_SDWP, (FSC | IEN | PTD | PEN | M14)}, /* MMC1_SDWP */
pekon gupta93526972014-07-22 16:03:24 +0530[diff] [blame]24#if defined(CONFIG_NOR)
25 /* NOR only pin-mux */
26 {GPMC_A0 , M0 | IDIS | PDIS}, /* nor.GPMC_A[0 ] */
27 {GPMC_A1 , M0 | IDIS | PDIS}, /* nor.GPMC_A[1 ] */
28 {GPMC_A2 , M0 | IDIS | PDIS}, /* nor.GPMC_A[2 ] */
29 {GPMC_A3 , M0 | IDIS | PDIS}, /* nor.GPMC_A[3 ] */
30 {GPMC_A4 , M0 | IDIS | PDIS}, /* nor.GPMC_A[4 ] */
31 {GPMC_A5 , M0 | IDIS | PDIS}, /* nor.GPMC_A[5 ] */
32 {GPMC_A6 , M0 | IDIS | PDIS}, /* nor.GPMC_A[6 ] */
33 {GPMC_A7 , M0 | IDIS | PDIS}, /* nor.GPMC_A[7 ] */
34 {GPMC_A8 , M0 | IDIS | PDIS}, /* nor.GPMC_A[8 ] */
35 {GPMC_A9 , M0 | IDIS | PDIS}, /* nor.GPMC_A[9 ] */
36 {GPMC_A10 , M0 | IDIS | PDIS}, /* nor.GPMC_A[10] */
37 {GPMC_A11 , M0 | IDIS | PDIS}, /* nor.GPMC_A[11] */
38 {GPMC_A12 , M0 | IDIS | PDIS}, /* nor.GPMC_A[12] */
39 {GPMC_A13 , M0 | IDIS | PDIS}, /* nor.GPMC_A[13] */
40 {GPMC_A14 , M0 | IDIS | PDIS}, /* nor.GPMC_A[14] */
41 {GPMC_A15 , M0 | IDIS | PDIS}, /* nor.GPMC_A[15] */
42 {GPMC_A16 , M0 | IDIS | PDIS}, /* nor.GPMC_A[16] */
43 {GPMC_A17 , M0 | IDIS | PDIS}, /* nor.GPMC_A[17] */
44 {GPMC_A18 , M0 | IDIS | PDIS}, /* nor.GPMC_A[18] */
45 {GPMC_A19 , M0 | IDIS | PDIS}, /* nor.GPMC_A[19] */
46 {GPMC_A20 , M0 | IDIS | PDIS}, /* nor.GPMC_A[20] */
47 {GPMC_A21 , M0 | IDIS | PDIS}, /* nor.GPMC_A[21] */
48 {GPMC_A22 , M0 | IDIS | PDIS}, /* nor.GPMC_A[22] */
49 {GPMC_A23 , M0 | IDIS | PDIS}, /* nor.GPMC_A[23] */
50 {GPMC_A24 , M0 | IDIS | PDIS}, /* nor.GPMC_A[24] */
51 {GPMC_A25 , M0 | IDIS | PDIS}, /* nor.GPMC_A[25] */
52 {GPMC_A26 , M0 | IDIS | PDIS}, /* nor.GPMC_A[26] */
53#else
54 /* eMMC pinmux */
Lokesh Vutla7f36c882013-05-30 03:19:37 +0000[diff] [blame]55 {GPMC_A19, (IEN | PTU | PDIS | M1)}, /* mmc2_dat4 */
56 {GPMC_A20, (IEN | PTU | PDIS | M1)}, /* mmc2_dat5 */
57 {GPMC_A21, (IEN | PTU | PDIS | M1)}, /* mmc2_dat6 */
58 {GPMC_A22, (IEN | PTU | PDIS | M1)}, /* mmc2_dat7 */
59 {GPMC_A23, (IEN | PTU | PDIS | M1)}, /* mmc2_clk */
60 {GPMC_A24, (IEN | PTU | PDIS | M1)}, /* mmc2_dat0 */
61 {GPMC_A25, (IEN | PTU | PDIS | M1)}, /* mmc2_dat1 */
62 {GPMC_A26, (IEN | PTU | PDIS | M1)}, /* mmc2_dat2 */
63 {GPMC_A27, (IEN | PTU | PDIS | M1)}, /* mmc2_dat3 */
64 {GPMC_CS1, (IEN | PTU | PDIS | M1)}, /* mmm2_cmd */
pekon gupta93526972014-07-22 16:03:24 +0530[diff] [blame]65#endif
Felipe Balbi49b633b2014-06-26 16:38:05 -0500[diff] [blame]66#if (CONFIG_CONS_INDEX == 1)
Lokesh Vutla7f36c882013-05-30 03:19:37 +0000[diff] [blame]67 {UART1_RXD, (FSC | IEN | PTU | PDIS | M0)}, /* UART1_RXD */
68 {UART1_TXD, (FSC | IEN | PTU | PDIS | M0)}, /* UART1_TXD */
69 {UART1_CTSN, (IEN | PTU | PDIS | M3)}, /* UART1_CTSN */
70 {UART1_RTSN, (IEN | PTU | PDIS | M3)}, /* UART1_RTSN */
Felipe Balbi49b633b2014-06-26 16:38:05 -0500[diff] [blame]71#elif (CONFIG_CONS_INDEX == 3)
72 {UART3_RXD, (FSC | IEN | PTU | PDIS | M0)}, /* UART3_RXD */
73 {UART3_TXD, (FSC | IEN | PTU | PDIS | M0)}, /* UART3_TXD */
74#endif
Lokesh Vutla7f36c882013-05-30 03:19:37 +0000[diff] [blame]75 {I2C1_SDA, (IEN | PTU | PDIS | M0)}, /* I2C1_SDA */
76 {I2C1_SCL, (IEN | PTU | PDIS | M0)}, /* I2C1_SCL */
Mugunthan V Ndec7f742013-07-08 16:04:42 +0530[diff] [blame]77 {MDIO_MCLK, (PTU | PEN | M0)}, /* MDIO_MCLK */
78 {MDIO_D, (IEN | PTU | PEN | M0)}, /* MDIO_D */
Nishanth Menon27d170a2015-06-04 16:42:39 +0530[diff] [blame^]79 {RGMII0_TXC, (PIN_OUTPUT | MANUAL_MODE | M0) },
80 {RGMII0_TXCTL, (PIN_OUTPUT | MANUAL_MODE | M0) },
81 {RGMII0_TXD3, (PIN_OUTPUT | MANUAL_MODE | M0) },
82 {RGMII0_TXD2, (PIN_OUTPUT | MANUAL_MODE | M0) },
83 {RGMII0_TXD1, (PIN_OUTPUT | MANUAL_MODE | M0) },
84 {RGMII0_TXD0, (PIN_OUTPUT | MANUAL_MODE | M0) },
85 {RGMII0_RXC, (PIN_INPUT | MANUAL_MODE | M0) },
86 {RGMII0_RXCTL, (PIN_INPUT | MANUAL_MODE | M0) },
87 {RGMII0_RXD3, (PIN_INPUT | MANUAL_MODE | M0) },
88 {RGMII0_RXD2, (PIN_INPUT | MANUAL_MODE | M0) },
89 {RGMII0_RXD1, (PIN_INPUT | MANUAL_MODE | M0) },
90 {RGMII0_RXD0, (PIN_INPUT | MANUAL_MODE | M0) },
91 {VIN2A_D12, (PIN_OUTPUT | MANUAL_MODE | M3) },
92 {VIN2A_D13, (PIN_OUTPUT | MANUAL_MODE | M3) },
93 {VIN2A_D14, (PIN_OUTPUT | MANUAL_MODE | M3) },
94 {VIN2A_D15, (PIN_OUTPUT | MANUAL_MODE | M3) },
95 {VIN2A_D16, (PIN_OUTPUT | MANUAL_MODE | M3) },
96 {VIN2A_D17, (PIN_OUTPUT | MANUAL_MODE | M3) },
97 {VIN2A_D18, (PIN_INPUT | MANUAL_MODE | M3)},
98 {VIN2A_D19, (PIN_INPUT | MANUAL_MODE | M3)},
99 {VIN2A_D20, (PIN_INPUT | MANUAL_MODE | M3)},
100 {VIN2A_D21, (PIN_INPUT | MANUAL_MODE | M3)},
101 {VIN2A_D22, (PIN_INPUT | MANUAL_MODE | M3)},
102 {VIN2A_D23, (PIN_INPUT | MANUAL_MODE | M3)},
pekon gupta93526972014-07-22 16:03:24 +0530[diff] [blame]103#if defined(CONFIG_NAND) || defined(CONFIG_NOR)
pekon gupta54a97d22014-07-22 16:03:23 +0530[diff] [blame]104 /* NAND / NOR pin-mux */
105 {GPMC_AD0 , M0 | IEN | PDIS}, /* GPMC_AD0 */
106 {GPMC_AD1 , M0 | IEN | PDIS}, /* GPMC_AD1 */
107 {GPMC_AD2 , M0 | IEN | PDIS}, /* GPMC_AD2 */
108 {GPMC_AD3 , M0 | IEN | PDIS}, /* GPMC_AD3 */
109 {GPMC_AD4 , M0 | IEN | PDIS}, /* GPMC_AD4 */
110 {GPMC_AD5 , M0 | IEN | PDIS}, /* GPMC_AD5 */
111 {GPMC_AD6 , M0 | IEN | PDIS}, /* GPMC_AD6 */
112 {GPMC_AD7 , M0 | IEN | PDIS}, /* GPMC_AD7 */
113 {GPMC_AD8 , M0 | IEN | PDIS}, /* GPMC_AD8 */
114 {GPMC_AD9 , M0 | IEN | PDIS}, /* GPMC_AD9 */
115 {GPMC_AD10, M0 | IEN | PDIS}, /* GPMC_AD10 */
116 {GPMC_AD11, M0 | IEN | PDIS}, /* GPMC_AD11 */
117 {GPMC_AD12, M0 | IEN | PDIS}, /* GPMC_AD12 */
118 {GPMC_AD13, M0 | IEN | PDIS}, /* GPMC_AD13 */
119 {GPMC_AD14, M0 | IEN | PDIS}, /* GPMC_AD14 */
120 {GPMC_AD15, M0 | IEN | PDIS}, /* GPMC_AD15 */
121 {GPMC_CS0, M0 | IDIS | PEN | PTU}, /* GPMC chip-select */
122 {GPMC_ADVN_ALE, M0 | IDIS | PEN | PTD}, /* GPMC Addr latch */
123 {GPMC_OEN_REN, M0 | IDIS | PEN | PTU}, /* GPMC Read enable */
124 {GPMC_WEN, M0 | IDIS | PEN | PTU}, /* GPMC Write enable_n */
125 {GPMC_BEN0, M0 | IDIS | PEN | PTD}, /* GPMC Byte/Column En */
126 {GPMC_WAIT0, M0 | IEN | PEN | PTU}, /* GPMC Wait/Ready */
127 /* GPMC_WPN (Write Protect) is controlled by DIP Switch SW10(12) */
128#else
129 /* QSPI pin-mux */
Matt Porter247cdf02013-10-07 15:53:03 +0530[diff] [blame]130 {GPMC_A13, (IEN | PDIS | M1)}, /* QSPI1_RTCLK */
131 {GPMC_A14, (IEN | PDIS | M1)}, /* QSPI1_D[3] */
132 {GPMC_A15, (IEN | PDIS | M1)}, /* QSPI1_D[2] */
Lubomir Popovae525182014-11-10 18:34:10 +0200[diff] [blame]133 {GPMC_A16, (IEN | PDIS | M1)}, /* QSPI1_D[0] */
134 {GPMC_A17, (IEN | PDIS | M1)}, /* QSPI1_D[1] */
Matt Porter247cdf02013-10-07 15:53:03 +0530[diff] [blame]135 {GPMC_A18, (M1)}, /* QSPI1_SCLK */
136 {GPMC_A3, (IEN | PDIS | M1)}, /* QSPI1_CS2 */
137 {GPMC_A4, (IEN | PDIS | M1)}, /* QSPI1_CS3 */
138 {GPMC_CS2, (IEN | PTU | PDIS | M1)}, /* QSPI1_CS0 */
139 {GPMC_CS3, (IEN | PTU | PDIS | M1)}, /* QSPI1_CS1*/
pekon gupta93526972014-07-22 16:03:24 +0530[diff] [blame]140#endif /* CONFIG_NAND || CONFIG_NOR */
Dan Murphy834e91a2013-10-11 12:28:17 -0500[diff] [blame]141 {USB2_DRVVBUS, (M0 | IEN | FSC) },
Lokesh Vutla7b922522014-08-04 19:42:24 +0530[diff] [blame]142 {SPI1_CS1, (PEN | IDIS | M14) },
Lokesh Vutla687054a2013-02-12 21:29:08 +0000[diff] [blame]143};
Nishanth Menon27d170a2015-06-04 16:42:39 +0530[diff] [blame^]144
145const struct pad_conf_entry early_padconf[] = {
146#if (CONFIG_CONS_INDEX == 1)
147 {UART1_RXD, (PIN_INPUT_SLEW | M0)}, /* UART1_RXD */
148 {UART1_TXD, (PIN_INPUT_SLEW | M0)}, /* UART1_TXD */
149#elif (CONFIG_CONS_INDEX == 3)
150 {UART3_RXD, (PIN_INPUT_SLEW | M0)}, /* UART3_RXD */
151 {UART3_TXD, (PIN_INPUT_SLEW | M0)}, /* UART3_TXD */
152#endif
153 {I2C1_SDA, (PIN_INPUT | M0)}, /* I2C1_SDA */
154 {I2C1_SCL, (PIN_INPUT | M0)}, /* I2C1_SCL */
155};
156
157#ifdef CONFIG_IODELAY_RECALIBRATION
158const struct iodelay_cfg_entry iodelay_cfg_array[] = {
159 {0x6F0, 480, 0}, /* RGMMI0_RXC_IN */
160 {0x6FC, 111, 1641}, /* RGMMI0_RXCTL_IN */
161 {0x708, 272, 1116}, /* RGMMI0_RXD0_IN */
162 {0x714, 243, 1260}, /* RGMMI0_RXD1_IN */
163 {0x720, 0, 1614}, /* RGMMI0_RXD2_IN */
164 {0x72C, 105, 1673}, /* RGMMI0_RXD3_IN */
165 {0x740, 531, 120}, /* RGMMI0_TXC_OUT */
166 {0x74C, 11, 60}, /* RGMMI0_TXCTL_OUT */
167 {0x758, 7, 120}, /* RGMMI0_TXD0_OUT */
168 {0x764, 0, 0}, /* RGMMI0_TXD1_OUT */
169 {0x770, 276, 120}, /* RGMMI0_TXD2_OUT */
170 {0x77C, 440, 120}, /* RGMMI0_TXD3_OUT */
171 {0xAB0, 702, 0}, /* CFG_VIN2A_D18_IN */
172 {0xABC, 136, 976}, /* CFG_VIN2A_D19_IN */
173 {0xAD4, 210, 1357}, /* CFG_VIN2A_D20_IN */
174 {0xAE0, 189, 1462}, /* CFG_VIN2A_D21_IN */
175 {0xAEC, 232, 1278}, /* CFG_VIN2A_D22_IN */
176 {0xAF8, 0, 1397}, /* CFG_VIN2A_D23_IN */
177 {0xA70, 1551, 115}, /* CFG_VIN2A_D12_OUT */
178 {0xA7C, 816, 0}, /* CFG_VIN2A_D13_OUT */
179 {0xA88, 876, 0}, /* CFG_VIN2A_D14_OUT */
180 {0xA94, 312, 0}, /* CFG_VIN2A_D15_OUT */
181 {0xAA0, 58, 0}, /* CFG_VIN2A_D16_OUT */
182 {0xAAC, 0, 0}, /* CFG_VIN2A_D17_OUT */
183};
184#endif
185
186const struct pad_conf_entry dra74x_core_padconf_array[] = {
187 {GPMC_AD0, (M3 | PIN_INPUT)}, /* gpmc_ad0.vout3_d0 */
188 {GPMC_AD1, (M3 | PIN_INPUT)}, /* gpmc_ad1.vout3_d1 */
189 {GPMC_AD2, (M3 | PIN_INPUT)}, /* gpmc_ad2.vout3_d2 */
190 {GPMC_AD3, (M3 | PIN_INPUT)}, /* gpmc_ad3.vout3_d3 */
191 {GPMC_AD4, (M3 | PIN_INPUT)}, /* gpmc_ad4.vout3_d4 */
192 {GPMC_AD5, (M3 | PIN_INPUT)}, /* gpmc_ad5.vout3_d5 */
193 {GPMC_AD6, (M3 | PIN_INPUT)}, /* gpmc_ad6.vout3_d6 */
194 {GPMC_AD7, (M3 | PIN_INPUT)}, /* gpmc_ad7.vout3_d7 */
195 {GPMC_AD8, (M3 | PIN_INPUT)}, /* gpmc_ad8.vout3_d8 */
196 {GPMC_AD9, (M3 | PIN_INPUT)}, /* gpmc_ad9.vout3_d9 */
197 {GPMC_AD10, (M3 | PIN_INPUT)}, /* gpmc_ad10.vout3_d10 */
198 {GPMC_AD11, (M3 | PIN_INPUT)}, /* gpmc_ad11.vout3_d11 */
199 {GPMC_AD12, (M3 | PIN_INPUT)}, /* gpmc_ad12.vout3_d12 */
200 {GPMC_AD13, (M3 | PIN_INPUT)}, /* gpmc_ad13.vout3_d13 */
201 {GPMC_AD14, (M3 | PIN_INPUT)}, /* gpmc_ad14.vout3_d14 */
202 {GPMC_AD15, (M3 | PIN_INPUT)}, /* gpmc_ad15.vout3_d15 */
203 {GPMC_A0, (M3 | PIN_INPUT_PULLDOWN)}, /* gpmc_a0.vout3_d16 */
204 {GPMC_A1, (M3 | PIN_INPUT_PULLDOWN)}, /* gpmc_a1.vout3_d17 */
205 {GPMC_A2, (M3 | PIN_INPUT_PULLDOWN)}, /* gpmc_a2.vout3_d18 */
206 {GPMC_A3, (M3 | PIN_INPUT_PULLDOWN)}, /* gpmc_a3.vout3_d19 */
207 {GPMC_A4, (M3 | PIN_INPUT_PULLDOWN)}, /* gpmc_a4.vout3_d20 */
208 {GPMC_A5, (M3 | PIN_INPUT_PULLDOWN)}, /* gpmc_a5.vout3_d21 */
209 {GPMC_A6, (M3 | PIN_INPUT_PULLDOWN)}, /* gpmc_a6.vout3_d22 */
210 {GPMC_A7, (M3 | PIN_INPUT_PULLDOWN)}, /* gpmc_a7.vout3_d23 */
211 {GPMC_A8, (M3 | PIN_INPUT_PULLDOWN)}, /* gpmc_a8.vout3_hsync */
212 {GPMC_A9, (M3 | PIN_INPUT_PULLDOWN)}, /* gpmc_a9.vout3_vsync */
213 {GPMC_A10, (M3 | PIN_INPUT_PULLDOWN)}, /* gpmc_a10.vout3_de */
214 {GPMC_A11, (M14 | PIN_INPUT_PULLDOWN)}, /* gpmc_a11.gpio2_1 */
215 {GPMC_A13, (M1 | PIN_INPUT_PULLDOWN)}, /* gpmc_a13.qspi1_rtclk */
216 {GPMC_A14, (M1 | PIN_INPUT_PULLDOWN)}, /* gpmc_a14.qspi1_d3 */
217 {GPMC_A15, (M1 | PIN_INPUT_PULLDOWN)}, /* gpmc_a15.qspi1_d2 */
218 {GPMC_A16, (M1 | PIN_INPUT_PULLDOWN)}, /* gpmc_a16.qspi1_d0 */
219 {GPMC_A17, (M1 | PIN_INPUT_PULLDOWN)}, /* gpmc_a17.qspi1_d1 */
220 {GPMC_A18, (M1 | PIN_INPUT_PULLDOWN)}, /* gpmc_a18.qspi1_sclk */
221 {GPMC_A19, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a19.mmc2_dat4 */
222 {GPMC_A20, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a20.mmc2_dat5 */
223 {GPMC_A21, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a21.mmc2_dat6 */
224 {GPMC_A22, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a22.mmc2_dat7 */
225 {GPMC_A23, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a23.mmc2_clk */
226 {GPMC_A24, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a24.mmc2_dat0 */
227 {GPMC_A25, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a25.mmc2_dat1 */
228 {GPMC_A26, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a26.mmc2_dat2 */
229 {GPMC_A27, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a27.mmc2_dat3 */
230 {GPMC_CS1, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_cs1.mmc2_cmd */
231 {GPMC_CS2, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_cs2.qspi1_cs0 */
232 {GPMC_CS3, (M3 | PIN_INPUT_PULLUP)}, /* gpmc_cs3.vout3_clk */
233 {VIN1A_CLK0, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin1a_clk0.vin1a_clk0 */
234 {VIN1A_DE0, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin1a_de0.vin1a_de0 */
235 {VIN1A_FLD0, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin1a_fld0.vin1a_fld0 */
236 {VIN1A_HSYNC0, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin1a_hsync0.vin1a_hsync0 */
237 {VIN1A_VSYNC0, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin1a_vsync0.vin1a_vsync0 */
238 {VIN1A_D0, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin1a_d0.vin1a_d0 */
239 {VIN1A_D1, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin1a_d1.vin1a_d1 */
240 {VIN1A_D2, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin1a_d2.vin1a_d2 */
241 {VIN1A_D3, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin1a_d3.vin1a_d3 */
242 {VIN1A_D4, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin1a_d4.vin1a_d4 */
243 {VIN1A_D5, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin1a_d5.vin1a_d5 */
244 {VIN1A_D6, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin1a_d6.vin1a_d6 */
245 {VIN1A_D7, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin1a_d7.vin1a_d7 */
246 {VIN1A_D8, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin1a_d8.vin1a_d8 */
247 {VIN1A_D9, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin1a_d9.vin1a_d9 */
248 {VIN1A_D10, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin1a_d10.vin1a_d10 */
249 {VIN1A_D11, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin1a_d11.vin1a_d11 */
250 {VIN1A_D12, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin1a_d12.vin1a_d12 */
251 {VIN1A_D13, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin1a_d13.vin1a_d13 */
252 {VIN1A_D14, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin1a_d14.vin1a_d14 */
253 {VIN1A_D15, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin1a_d15.vin1a_d15 */
254 {VIN1A_D16, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin1a_d16.vin1a_d16 */
255 {VIN1A_D17, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin1a_d17.vin1a_d17 */
256 {VIN1A_D18, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin1a_d18.vin1a_d18 */
257 {VIN1A_D19, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin1a_d19.vin1a_d19 */
258 {VIN1A_D20, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin1a_d20.vin1a_d20 */
259 {VIN1A_D21, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin1a_d21.vin1a_d21 */
260 {VIN1A_D22, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin1a_d22.vin1a_d22 */
261 {VIN1A_D23, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin1a_d23.vin1a_d23 */
262 {VIN2A_D12, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d12.rgmii1_txc */
263 {VIN2A_D13, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d13.rgmii1_txctl */
264 {VIN2A_D14, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d14.rgmii1_txd3 */
265 {VIN2A_D15, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d15.rgmii1_txd2 */
266 {VIN2A_D16, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d16.rgmii1_txd1 */
267 {VIN2A_D17, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d17.rgmii1_txd0 */
268 {VIN2A_D18, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d18.rgmii1_rxc */
269 {VIN2A_D19, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d19.rgmii1_rxctl */
270 {VIN2A_D20, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d20.rgmii1_rxd3 */
271 {VIN2A_D21, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d21.rgmii1_rxd2 */
272 {VIN2A_D22, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d22.rgmii1_rxd1 */
273 {VIN2A_D23, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d23.rgmii1_rxd0 */
274 {VOUT1_CLK, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_clk.vout1_clk */
275 {VOUT1_DE, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_de.vout1_de */
276 {VOUT1_HSYNC, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_hsync.vout1_hsync */
277 {VOUT1_VSYNC, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_vsync.vout1_vsync */
278 {VOUT1_D0, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d0.vout1_d0 */
279 {VOUT1_D1, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d1.vout1_d1 */
280 {VOUT1_D2, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d2.vout1_d2 */
281 {VOUT1_D3, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d3.vout1_d3 */
282 {VOUT1_D4, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d4.vout1_d4 */
283 {VOUT1_D5, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d5.vout1_d5 */
284 {VOUT1_D6, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d6.vout1_d6 */
285 {VOUT1_D7, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d7.vout1_d7 */
286 {VOUT1_D8, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d8.vout1_d8 */
287 {VOUT1_D9, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d9.vout1_d9 */
288 {VOUT1_D10, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d10.vout1_d10 */
289 {VOUT1_D11, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d11.vout1_d11 */
290 {VOUT1_D12, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d12.vout1_d12 */
291 {VOUT1_D13, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d13.vout1_d13 */
292 {VOUT1_D14, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d14.vout1_d14 */
293 {VOUT1_D15, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d15.vout1_d15 */
294 {VOUT1_D16, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d16.vout1_d16 */
295 {VOUT1_D17, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d17.vout1_d17 */
296 {VOUT1_D18, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d18.vout1_d18 */
297 {VOUT1_D19, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d19.vout1_d19 */
298 {VOUT1_D20, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d20.vout1_d20 */
299 {VOUT1_D21, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d21.vout1_d21 */
300 {VOUT1_D22, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d22.vout1_d22 */
301 {VOUT1_D23, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d23.vout1_d23 */
302 {MDIO_MCLK, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* mdio_mclk.mdio_mclk */
303 {MDIO_D, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* mdio_d.mdio_d */
304 {RGMII0_TXC, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_txc.rgmii0_txc */
305 {RGMII0_TXCTL, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_txctl.rgmii0_txctl */
306 {RGMII0_TXD3, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_txd3.rgmii0_txd3 */
307 {RGMII0_TXD2, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_txd2.rgmii0_txd2 */
308 {RGMII0_TXD1, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_txd1.rgmii0_txd1 */
309 {RGMII0_TXD0, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_txd0.rgmii0_txd0 */
310 {RGMII0_RXC, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_rxc.rgmii0_rxc */
311 {RGMII0_RXCTL, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_rxctl.rgmii0_rxctl */
312 {RGMII0_RXD3, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_rxd3.rgmii0_rxd3 */
313 {RGMII0_RXD2, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_rxd2.rgmii0_rxd2 */
314 {RGMII0_RXD1, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_rxd1.rgmii0_rxd1 */
315 {RGMII0_RXD0, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_rxd0.rgmii0_rxd0 */
316 {USB1_DRVVBUS, (M0 | PIN_INPUT_SLEW)}, /* usb1_drvvbus.usb1_drvvbus */
317 {USB2_DRVVBUS, (M0 | PIN_INPUT_SLEW)}, /* usb2_drvvbus.usb2_drvvbus */
318 {GPIO6_14, (M9 | PIN_INPUT_PULLUP)}, /* gpio6_14.i2c3_sda */
319 {GPIO6_15, (M9 | PIN_INPUT_PULLUP)}, /* gpio6_15.i2c3_scl */
320 {GPIO6_16, (M14 | PIN_INPUT_PULLUP)}, /* gpio6_16.gpio6_16 */
321 {XREF_CLK2, (M5 | PIN_INPUT_PULLDOWN)}, /* xref_clk2.atl_clk2 */
322 {MCASP1_ACLKX, (M0 | PIN_INPUT_PULLDOWN)}, /* mcasp1_aclkx.mcasp1_aclkx */
323 {MCASP1_FSX, (M0 | PIN_INPUT_SLEW)}, /* mcasp1_fsx.mcasp1_fsx */
324 {MCASP1_AXR0, (M0 | PIN_INPUT_SLEW | VIRTUAL_MODE15)}, /* mcasp1_axr0.mcasp1_axr0 */
325 {MCASP1_AXR1, (M0 | PIN_INPUT_SLEW)}, /* mcasp1_axr1.mcasp1_axr1 */
326 {MCASP1_AXR2, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr2.gpio5_4 */
327 {MCASP1_AXR3, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr3.gpio5_5 */
328 {MCASP1_AXR4, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr4.gpio5_6 */
329 {MCASP1_AXR5, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr5.gpio5_7 */
330 {MCASP1_AXR6, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr6.gpio5_8 */
331 {MCASP1_AXR7, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr7.gpio5_9 */
332 {MCASP1_AXR12, (M1 | PIN_INPUT_SLEW | VIRTUAL_MODE10)}, /* mcasp1_axr12.mcasp7_axr0 */
333 {MCASP1_AXR13, (M1 | PIN_INPUT_SLEW)}, /* mcasp1_axr13.mcasp7_axr1 */
334 {MCASP1_AXR14, (M1 | PIN_INPUT_SLEW | VIRTUAL_MODE10)}, /* mcasp1_axr14.mcasp7_aclkx */
335 {MCASP1_AXR15, (M1 | PIN_INPUT_SLEW | VIRTUAL_MODE10)}, /* mcasp1_axr15.mcasp7_fsx */
336 {MCASP2_ACLKR, (M0 | PIN_INPUT_PULLDOWN)}, /* mcasp2_aclkr.mcasp2_aclkr */
337 {MCASP3_ACLKX, (M0 | PIN_INPUT_PULLDOWN)}, /* mcasp3_aclkx.mcasp3_aclkx */
338 {MCASP3_FSX, (M0 | PIN_INPUT_SLEW)}, /* mcasp3_fsx.mcasp3_fsx */
339 {MCASP3_AXR0, (M0 | PIN_INPUT_SLEW)}, /* mcasp3_axr0.mcasp3_axr0 */
340 {MCASP3_AXR1, (M0 | PIN_INPUT_SLEW | VIRTUAL_MODE6)}, /* mcasp3_axr1.mcasp3_axr1 */
341 {MMC1_CLK, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_clk.mmc1_clk */
342 {MMC1_CMD, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_cmd.mmc1_cmd */
343 {MMC1_DAT0, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_dat0.mmc1_dat0 */
344 {MMC1_DAT1, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_dat1.mmc1_dat1 */
345 {MMC1_DAT2, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_dat2.mmc1_dat2 */
346 {MMC1_DAT3, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_dat3.mmc1_dat3 */
347 {MMC1_SDCD, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* mmc1_sdcd.mmc1_sdcd */
348 {MMC1_SDWP, (M14 | PIN_INPUT_SLEW)}, /* mmc1_sdwp.gpio6_28 */
349 {GPIO6_11, (M14 | PIN_INPUT_PULLUP)}, /* gpio6_11.gpio6_11 */
350 {SPI1_SCLK, (M0 | PIN_INPUT_PULLDOWN)}, /* spi1_sclk.spi1_sclk */
351 {SPI1_D1, (M0 | PIN_INPUT_PULLDOWN)}, /* spi1_d1.spi1_d1 */
352 {SPI1_D0, (M0 | PIN_INPUT_PULLDOWN)}, /* spi1_d0.spi1_d0 */
353 {SPI1_CS0, (M0 | PIN_INPUT_PULLUP)}, /* spi1_cs0.spi1_cs0 */
354 {SPI1_CS1, (M14 | PIN_OUTPUT)}, /* spi1_cs1.gpio7_11 */
355 {SPI1_CS2, (M14 | PIN_INPUT_PULLDOWN)}, /* spi1_cs2.gpio7_12 */
356 {SPI1_CS3, (M6 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* spi1_cs3.hdmi1_cec */
357 {SPI2_SCLK, (M1 | PIN_INPUT_PULLDOWN)}, /* spi2_sclk.uart3_rxd */
358 {SPI2_D1, (M1 | PIN_INPUT_SLEW)}, /* spi2_d1.uart3_txd */
359 {SPI2_D0, (M1 | PIN_INPUT_SLEW)}, /* spi2_d0.uart3_ctsn */
360 {SPI2_CS0, (M1 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* spi2_cs0.uart3_rtsn */
361 {DCAN1_TX, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* dcan1_tx.dcan1_tx */
362 {DCAN1_RX, (M14 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* dcan1_rx.gpio1_15 */
363 {UART1_RXD, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* uart1_rxd.uart1_rxd */
364 {UART1_TXD, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* uart1_txd.uart1_txd */
365 {UART1_CTSN, (M3 | PIN_INPUT_PULLUP)}, /* uart1_ctsn.mmc4_clk */
366 {UART1_RTSN, (M3 | PIN_INPUT_PULLUP)}, /* uart1_rtsn.mmc4_cmd */
367 {UART2_RXD, (M3 | PIN_INPUT_PULLUP)}, /* N/A.mmc4_dat0 */
368 {UART2_TXD, (M3 | PIN_INPUT_PULLUP)}, /* uart2_txd.mmc4_dat1 */
369 {UART2_CTSN, (M3 | PIN_INPUT_PULLUP)}, /* uart2_ctsn.mmc4_dat2 */
370 {UART2_RTSN, (M3 | PIN_INPUT_PULLUP)}, /* uart2_rtsn.mmc4_dat3 */
371 {I2C2_SDA, (M0 | PIN_INPUT_PULLUP)}, /* i2c2_sda.i2c2_sda */
372 {I2C2_SCL, (M0 | PIN_INPUT_PULLUP)}, /* i2c2_scl.i2c2_scl */
373 {WAKEUP0, (M1 | PIN_OUTPUT)}, /* Wakeup0.dcan1_rx */
374 {WAKEUP2, (M14 | PIN_OUTPUT)}, /* Wakeup2.gpio1_2 */
375};
376
377#ifdef CONFIG_IODELAY_RECALIBRATION
378const struct iodelay_cfg_entry dra742_iodelay_cfg_array[] = {
379 {0x06F0, 480, 0}, /* CFG_RGMII0_RXC_IN */
380 {0x06FC, 111, 1641}, /* CFG_RGMII0_RXCTL_IN */
381 {0x0708, 272, 1116}, /* CFG_RGMII0_RXD0_IN */
382 {0x0714, 243, 1260}, /* CFG_RGMII0_RXD1_IN */
383 {0x0720, 0, 1614}, /* CFG_RGMII0_RXD2_IN */
384 {0x072C, 105, 1673}, /* CFG_RGMII0_RXD3_IN */
385 {0x0740, 0, 0}, /* CFG_RGMII0_TXC_OUT */
386 {0x074C, 1560, 120}, /* CFG_RGMII0_TXCTL_OUT */
387 {0x0758, 1570, 120}, /* CFG_RGMII0_TXD0_OUT */
388 {0x0764, 1500, 120}, /* CFG_RGMII0_TXD1_OUT */
389 {0x0770, 1775, 120}, /* CFG_RGMII0_TXD2_OUT */
390 {0x077C, 1875, 120}, /* CFG_RGMII0_TXD3_OUT */
391 {0x08D0, 0, 0}, /* CFG_VIN1A_CLK0_IN */
392 {0x08DC, 2600, 0}, /* CFG_VIN1A_D0_IN */
393 {0x08E8, 2652, 46}, /* CFG_VIN1A_D10_IN */
394 {0x08F4, 2541, 0}, /* CFG_VIN1A_D11_IN */
395 {0x0900, 2603, 574}, /* CFG_VIN1A_D12_IN */
396 {0x090C, 2548, 443}, /* CFG_VIN1A_D13_IN */
397 {0x0918, 2624, 598}, /* CFG_VIN1A_D14_IN */
398 {0x0924, 2535, 1027}, /* CFG_VIN1A_D15_IN */
399 {0x0930, 2526, 818}, /* CFG_VIN1A_D16_IN */
400 {0x093C, 2623, 797}, /* CFG_VIN1A_D17_IN */
401 {0x0948, 2578, 888}, /* CFG_VIN1A_D18_IN */
402 {0x0954, 2574, 1008}, /* CFG_VIN1A_D19_IN */
403 {0x0960, 2527, 123}, /* CFG_VIN1A_D1_IN */
404 {0x096C, 2577, 737}, /* CFG_VIN1A_D20_IN */
405 {0x0978, 2627, 616}, /* CFG_VIN1A_D21_IN */
406 {0x0984, 2573, 777}, /* CFG_VIN1A_D22_IN */
407 {0x0990, 2730, 67}, /* CFG_VIN1A_D23_IN */
408 {0x099C, 2509, 303}, /* CFG_VIN1A_D2_IN */
409 {0x09A8, 2494, 267}, /* CFG_VIN1A_D3_IN */
410 {0x09B4, 2474, 0}, /* CFG_VIN1A_D4_IN */
411 {0x09C0, 2556, 181}, /* CFG_VIN1A_D5_IN */
412 {0x09CC, 2516, 195}, /* CFG_VIN1A_D6_IN */
413 {0x09D8, 2589, 210}, /* CFG_VIN1A_D7_IN */
414 {0x09E4, 2624, 75}, /* CFG_VIN1A_D8_IN */
415 {0x09F0, 2704, 14}, /* CFG_VIN1A_D9_IN */
416 {0x09FC, 2469, 55}, /* CFG_VIN1A_DE0_IN */
417 {0x0A08, 2557, 264}, /* CFG_VIN1A_FLD0_IN */
418 {0x0A14, 2465, 269}, /* CFG_VIN1A_HSYNC0_IN */
419 {0x0A20, 2411, 348}, /* CFG_VIN1A_VSYNC0_IN */
420 {0x0A70, 150, 0}, /* CFG_VIN2A_D12_OUT */
421 {0x0A7C, 1500, 0}, /* CFG_VIN2A_D13_OUT */
422 {0x0A88, 1600, 0}, /* CFG_VIN2A_D14_OUT */
423 {0x0A94, 900, 0}, /* CFG_VIN2A_D15_OUT */
424 {0x0AA0, 680, 0}, /* CFG_VIN2A_D16_OUT */
425 {0x0AAC, 500, 0}, /* CFG_VIN2A_D17_OUT */
426 {0x0AB0, 702, 0}, /* CFG_VIN2A_D18_IN */
427 {0x0ABC, 136, 976}, /* CFG_VIN2A_D19_IN */
428 {0x0AD4, 210, 1357}, /* CFG_VIN2A_D20_IN */
429 {0x0AE0, 189, 1462}, /* CFG_VIN2A_D21_IN */
430 {0x0AEC, 232, 1278}, /* CFG_VIN2A_D22_IN */
431 {0x0AF8, 0, 1397}, /* CFG_VIN2A_D23_IN */
432};
433#endif
434
Lokesh Vutla687054a2013-02-12 21:29:08 +0000[diff] [blame]435#endif /* _MUX_DATA_DRA7XX_H_ */