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Tom Rini83d290c2018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Marek Vasut0a333602017-10-09 21:51:10 +02002/*
3 * DHCOM DH-iMX6 PDK board configuration
4 *
5 * Copyright (C) 2017 Marek Vasut <marex@denx.de>
Marek Vasut0a333602017-10-09 21:51:10 +02006 */
7
8#ifndef __DH_IMX6_CONFIG_H
9#define __DH_IMX6_CONFIG_H
10
11#include <asm/arch/imx-regs.h>
12
Marek Vasut0a333602017-10-09 21:51:10 +020013#include "mx6_common.h"
14
15/*
16 * SPI NOR layout:
17 * 0x00_0000-0x00_ffff ... U-Boot SPL
18 * 0x01_0000-0x0f_ffff ... U-Boot
19 * 0x10_0000-0x10_ffff ... U-Boot env #1
20 * 0x11_0000-0x11_ffff ... U-Boot env #2
21 * 0x12_0000-0x1f_ffff ... UNUSED
22 */
23
24/* SPL */
25#include "imx6_spl.h" /* common IMX6 SPL configuration */
Marek Vasut0a333602017-10-09 21:51:10 +020026#define CONFIG_SPL_TARGET "u-boot-with-spl.imx"
27
28/* Miscellaneous configurable options */
Marek Vasut0a333602017-10-09 21:51:10 +020029
30#define CONFIG_CMDLINE_TAG
31#define CONFIG_SETUP_MEMORY_TAGS
32#define CONFIG_INITRD_TAG
33#define CONFIG_REVISION_TAG
34
Marek Vasut0a333602017-10-09 21:51:10 +020035#define CONFIG_BZIP2
36
37/* Size of malloc() pool */
38#define CONFIG_SYS_MALLOC_LEN (4 * SZ_1M)
39
40/* Bootcounter */
Marek Vasut0a333602017-10-09 21:51:10 +020041#define CONFIG_SYS_BOOTCOUNT_BE
42
43/* FEC ethernet */
Marek Vasut0a333602017-10-09 21:51:10 +020044#define IMX_FEC_BASE ENET_BASE_ADDR
45#define CONFIG_FEC_XCV_TYPE RMII
46#define CONFIG_ETHPRIME "FEC"
47#define CONFIG_FEC_MXC_PHYADDR 0
48#define CONFIG_ARP_TIMEOUT 200UL
49
Marek Vasut0a333602017-10-09 21:51:10 +020050/* MMC Configs */
Marek Vasut0a333602017-10-09 21:51:10 +020051#define CONFIG_SYS_FSL_ESDHC_ADDR 0
52#define CONFIG_SYS_FSL_USDHC_NUM 3
53#define CONFIG_SYS_MMC_ENV_DEV 2 /* 1 = SDHC3, 2 = SDHC4 (eMMC) */
54
55/* SATA Configs */
Marek Vasut0a333602017-10-09 21:51:10 +020056#define CONFIG_LBA48
Marek Vasut0a333602017-10-09 21:51:10 +020057
58/* SPI Flash Configs */
Marek Vasutcc48c2a2019-05-17 16:58:54 +020059#if defined(CONFIG_SPL_BUILD)
60#undef CONFIG_DM_SPI
61#undef CONFIG_DM_SPI_FLASH
Marek Vasutcc48c2a2019-05-17 16:58:54 +020062#endif
Marek Vasut0a333602017-10-09 21:51:10 +020063
64/* UART */
65#define CONFIG_MXC_UART
66#define CONFIG_MXC_UART_BASE UART1_BASE
Marek Vasut0a333602017-10-09 21:51:10 +020067#define CONFIG_BAUDRATE 115200
68
69/* USB Configs */
70#ifdef CONFIG_CMD_USB
71#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
72#define CONFIG_USB_HOST_ETHER
73#define CONFIG_USB_ETHER_ASIX
74#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
75#define CONFIG_MXC_USB_FLAGS 0
76#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 /* Enabled USB controller number */
Marek Vasut506abdb2017-10-22 10:22:40 +020077
78/* USB Gadget (DFU, UMS) */
79#if defined(CONFIG_CMD_DFU) || defined(CONFIG_CMD_USB_MASS_STORAGE)
Marek Vasut506abdb2017-10-22 10:22:40 +020080#define CONFIG_SYS_DFU_DATA_BUF_SIZE (16 * 1024 * 1024)
81#define DFU_DEFAULT_POLL_TIMEOUT 300
82
83/* USB IDs */
84#define CONFIG_G_DNL_UMS_VENDOR_NUM 0x0525
85#define CONFIG_G_DNL_UMS_PRODUCT_NUM 0xA4A5
86#endif
Marek Vasut0a333602017-10-09 21:51:10 +020087#endif
88
89/* Watchdog */
Marek Vasut0a333602017-10-09 21:51:10 +020090
91/* allow to overwrite serial and ethaddr */
92#define CONFIG_ENV_OVERWRITE
93
Marek Vasut0a333602017-10-09 21:51:10 +020094#define CONFIG_LOADADDR 0x12000000
95#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
96
97#ifndef CONFIG_SPL_BUILD
98#define CONFIG_EXTRA_ENV_SETTINGS \
99 "console=ttymxc0,115200\0" \
100 "fdt_addr=0x18000000\0" \
101 "fdt_high=0xffffffff\0" \
102 "initrd_high=0xffffffff\0" \
103 "kernel_addr_r=0x10008000\0" \
104 "fdt_addr_r=0x13000000\0" \
105 "ramdisk_addr_r=0x18000000\0" \
106 "scriptaddr=0x14000000\0" \
107 "fdtfile=imx6q-dhcom-pdk2.dtb\0"\
108 BOOTENV
109
110#define CONFIG_BOOTCOMMAND "run distro_bootcmd"
111
112#define BOOT_TARGET_DEVICES(func) \
113 func(MMC, mmc, 0) \
114 func(MMC, mmc, 2) \
115 func(USB, usb, 1) \
116 func(SATA, sata, 0) \
117 func(DHCP, dhcp, na)
118
119#include <config_distro_bootcmd.h>
120#endif
121
122/* Physical Memory Map */
Marek Vasut0a333602017-10-09 21:51:10 +0200123#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
124
125#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
126#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
127#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
128
129#define CONFIG_SYS_INIT_SP_OFFSET \
130 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
131
132#define CONFIG_SYS_INIT_SP_ADDR \
133 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
134
135#define CONFIG_SYS_MEMTEST_START 0x10000000
136#define CONFIG_SYS_MEMTEST_END 0x20000000
137#define CONFIG_SYS_MEMTEST_SCRATCH 0x10800000
138
139/* Environment */
Marek Vasut0a333602017-10-09 21:51:10 +0200140
141#endif /* __DH_IMX6_CONFIG_H */