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Masahiro Yamada509eb672014-11-26 18:33:59 +09001/*
2 * Device Tree Source for UniPhier PH1-LD4 SoC
3 *
Masahiro Yamadaedcfaeb2015-06-30 18:27:00 +09004 * Copyright (C) 2014-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
Masahiro Yamada509eb672014-11-26 18:33:59 +09005 *
Masahiro Yamada13b2ba12015-06-30 18:27:01 +09006 * SPDX-License-Identifier: GPL-2.0+ X11
Masahiro Yamada509eb672014-11-26 18:33:59 +09007 */
8
9/include/ "skeleton.dtsi"
10
11/ {
Masahiro Yamada6462cde2015-03-11 15:54:46 +090012 compatible = "socionext,ph1-ld4";
Masahiro Yamada509eb672014-11-26 18:33:59 +090013
14 cpus {
Masahiro Yamada509eb672014-11-26 18:33:59 +090015 #address-cells = <1>;
Masahiro Yamadaf5fd7af2014-12-06 00:03:23 +090016 #size-cells = <0>;
Masahiro Yamada509eb672014-11-26 18:33:59 +090017
18 cpu@0 {
19 device_type = "cpu";
20 compatible = "arm,cortex-a9";
21 reg = <0>;
22 };
23 };
24
Masahiro Yamadaedcfaeb2015-06-30 18:27:00 +090025 clocks {
26 arm_timer_clk: arm_timer_clk {
27 #clock-cells = <0>;
28 compatible = "fixed-clock";
29 clock-frequency = <50000000>;
30 };
Masahiro Yamadad243c182015-08-28 22:33:13 +090031
32 uart_clk: uart_clk {
33 #clock-cells = <0>;
34 compatible = "fixed-clock";
35 clock-frequency = <36864000>;
36 };
37
38 iobus_clk: iobus_clk {
39 #clock-cells = <0>;
40 compatible = "fixed-clock";
41 clock-frequency = <100000000>;
42 };
Masahiro Yamadaedcfaeb2015-06-30 18:27:00 +090043 };
44
Masahiro Yamada509eb672014-11-26 18:33:59 +090045 soc {
46 compatible = "simple-bus";
47 #address-cells = <1>;
48 #size-cells = <1>;
49 ranges;
Masahiro Yamadaedcfaeb2015-06-30 18:27:00 +090050 interrupt-parent = <&intc>;
51
52 extbus: extbus {
53 compatible = "simple-bus";
54 #address-cells = <2>;
55 #size-cells = <1>;
56 };
Masahiro Yamada625177d2014-11-26 18:34:00 +090057
Masahiro Yamadad243c182015-08-28 22:33:13 +090058 serial0: serial@54006800 {
Masahiro Yamada6462cde2015-03-11 15:54:46 +090059 compatible = "socionext,uniphier-uart";
Masahiro Yamada625177d2014-11-26 18:34:00 +090060 status = "disabled";
Masahiro Yamadad243c182015-08-28 22:33:13 +090061 reg = <0x54006800 0x40>;
62 pinctrl-names = "default";
63 pinctrl-0 = <&pinctrl_uart0>;
64 interrupts = <0 33 4>;
65 clocks = <&uart_clk>;
Masahiro Yamada625177d2014-11-26 18:34:00 +090066 clock-frequency = <36864000>;
67 };
68
Masahiro Yamadad243c182015-08-28 22:33:13 +090069 serial1: serial@54006900 {
Masahiro Yamada6462cde2015-03-11 15:54:46 +090070 compatible = "socionext,uniphier-uart";
Masahiro Yamada625177d2014-11-26 18:34:00 +090071 status = "disabled";
Masahiro Yamadad243c182015-08-28 22:33:13 +090072 reg = <0x54006900 0x40>;
73 pinctrl-names = "default";
74 pinctrl-0 = <&pinctrl_uart1>;
75 interrupts = <0 35 4>;
76 clocks = <&uart_clk>;
Masahiro Yamada625177d2014-11-26 18:34:00 +090077 clock-frequency = <36864000>;
78 };
79
Masahiro Yamadad243c182015-08-28 22:33:13 +090080 serial2: serial@54006a00 {
Masahiro Yamada6462cde2015-03-11 15:54:46 +090081 compatible = "socionext,uniphier-uart";
Masahiro Yamada625177d2014-11-26 18:34:00 +090082 status = "disabled";
Masahiro Yamadad243c182015-08-28 22:33:13 +090083 reg = <0x54006a00 0x40>;
84 pinctrl-names = "default";
85 pinctrl-0 = <&pinctrl_uart2>;
86 interrupts = <0 37 4>;
87 clocks = <&uart_clk>;
Masahiro Yamada625177d2014-11-26 18:34:00 +090088 clock-frequency = <36864000>;
89 };
90
Masahiro Yamadad243c182015-08-28 22:33:13 +090091 serial3: serial@54006b00 {
Masahiro Yamada6462cde2015-03-11 15:54:46 +090092 compatible = "socionext,uniphier-uart";
Masahiro Yamada625177d2014-11-26 18:34:00 +090093 status = "disabled";
Masahiro Yamadad243c182015-08-28 22:33:13 +090094 reg = <0x54006b00 0x40>;
95 pinctrl-names = "default";
96 pinctrl-0 = <&pinctrl_uart3>;
97 interrupts = <0 29 4>;
98 clocks = <&uart_clk>;
Masahiro Yamada625177d2014-11-26 18:34:00 +090099 clock-frequency = <36864000>;
100 };
Masahiro Yamada149c7512014-11-26 18:34:01 +0900101
Masahiro Yamadaf5fd7af2014-12-06 00:03:23 +0900102 i2c0: i2c@58400000 {
Masahiro Yamada6462cde2015-03-11 15:54:46 +0900103 compatible = "socionext,uniphier-i2c";
Masahiro Yamadad243c182015-08-28 22:33:13 +0900104 status = "disabled";
105 reg = <0x58400000 0x40>;
Masahiro Yamadaf5fd7af2014-12-06 00:03:23 +0900106 #address-cells = <1>;
107 #size-cells = <0>;
Masahiro Yamadad243c182015-08-28 22:33:13 +0900108 pinctrl-names = "default";
109 pinctrl-0 = <&pinctrl_i2c0>;
110 interrupts = <0 41 1>;
111 clocks = <&iobus_clk>;
Masahiro Yamadaf5fd7af2014-12-06 00:03:23 +0900112 clock-frequency = <100000>;
Masahiro Yamadaf5fd7af2014-12-06 00:03:23 +0900113 };
114
115 i2c1: i2c@58480000 {
Masahiro Yamada6462cde2015-03-11 15:54:46 +0900116 compatible = "socionext,uniphier-i2c";
Masahiro Yamadad243c182015-08-28 22:33:13 +0900117 status = "disabled";
118 reg = <0x58480000 0x40>;
Masahiro Yamadaf5fd7af2014-12-06 00:03:23 +0900119 #address-cells = <1>;
120 #size-cells = <0>;
Masahiro Yamadad243c182015-08-28 22:33:13 +0900121 pinctrl-names = "default";
122 pinctrl-0 = <&pinctrl_i2c1>;
123 interrupts = <0 42 1>;
124 clocks = <&iobus_clk>;
Masahiro Yamadaf5fd7af2014-12-06 00:03:23 +0900125 clock-frequency = <100000>;
Masahiro Yamadaf5fd7af2014-12-06 00:03:23 +0900126 };
127
Masahiro Yamadad243c182015-08-28 22:33:13 +0900128 /* chip-internal connection for DMD */
Masahiro Yamadaf5fd7af2014-12-06 00:03:23 +0900129 i2c2: i2c@58500000 {
Masahiro Yamada6462cde2015-03-11 15:54:46 +0900130 compatible = "socionext,uniphier-i2c";
Masahiro Yamadad243c182015-08-28 22:33:13 +0900131 reg = <0x58500000 0x40>;
Masahiro Yamadaf5fd7af2014-12-06 00:03:23 +0900132 #address-cells = <1>;
133 #size-cells = <0>;
Masahiro Yamadad243c182015-08-28 22:33:13 +0900134 pinctrl-names = "default";
135 pinctrl-0 = <&pinctrl_i2c2>;
136 interrupts = <0 43 1>;
137 clocks = <&iobus_clk>;
138 clock-frequency = <400000>;
Masahiro Yamadaf5fd7af2014-12-06 00:03:23 +0900139 };
140
141 i2c3: i2c@58580000 {
Masahiro Yamada6462cde2015-03-11 15:54:46 +0900142 compatible = "socionext,uniphier-i2c";
Masahiro Yamadad243c182015-08-28 22:33:13 +0900143 status = "disabled";
144 reg = <0x58580000 0x40>;
Masahiro Yamadaf5fd7af2014-12-06 00:03:23 +0900145 #address-cells = <1>;
146 #size-cells = <0>;
Masahiro Yamadad243c182015-08-28 22:33:13 +0900147 pinctrl-names = "default";
148 pinctrl-0 = <&pinctrl_i2c3>;
149 interrupts = <0 44 1>;
150 clocks = <&iobus_clk>;
Masahiro Yamadaf5fd7af2014-12-06 00:03:23 +0900151 clock-frequency = <100000>;
Masahiro Yamadaf5fd7af2014-12-06 00:03:23 +0900152 };
153
Masahiro Yamadaedcfaeb2015-06-30 18:27:00 +0900154 system-bus-controller-misc@59800000 {
155 compatible = "socionext,uniphier-system-bus-controller-misc",
156 "syscon";
157 reg = <0x59800000 0x2000>;
158 };
159
Masahiro Yamada149c7512014-11-26 18:34:01 +0900160 usb0: usb@5a800100 {
Masahiro Yamada6462cde2015-03-11 15:54:46 +0900161 compatible = "socionext,uniphier-ehci", "generic-ehci";
Masahiro Yamada149c7512014-11-26 18:34:01 +0900162 status = "disabled";
163 reg = <0x5a800100 0x100>;
Masahiro Yamadad243c182015-08-28 22:33:13 +0900164 pinctrl-names = "default";
165 pinctrl-0 = <&pinctrl_usb0>;
166 interrupts = <0 80 4>;
Masahiro Yamada149c7512014-11-26 18:34:01 +0900167 };
168
169 usb1: usb@5a810100 {
Masahiro Yamada6462cde2015-03-11 15:54:46 +0900170 compatible = "socionext,uniphier-ehci", "generic-ehci";
Masahiro Yamada149c7512014-11-26 18:34:01 +0900171 status = "disabled";
172 reg = <0x5a810100 0x100>;
Masahiro Yamadad243c182015-08-28 22:33:13 +0900173 pinctrl-names = "default";
174 pinctrl-0 = <&pinctrl_usb1>;
175 interrupts = <0 81 4>;
Masahiro Yamada149c7512014-11-26 18:34:01 +0900176 };
177
178 usb2: usb@5a820100 {
Masahiro Yamada6462cde2015-03-11 15:54:46 +0900179 compatible = "socionext,uniphier-ehci", "generic-ehci";
Masahiro Yamada149c7512014-11-26 18:34:01 +0900180 status = "disabled";
181 reg = <0x5a820100 0x100>;
Masahiro Yamadad243c182015-08-28 22:33:13 +0900182 pinctrl-names = "default";
183 pinctrl-0 = <&pinctrl_usb2>;
184 interrupts = <0 82 4>;
185 };
186
187 pinctrl: pinctrl@5f801000 {
188 compatible = "socionext,ph1-ld4-pinctrl",
189 "syscon";
190 reg = <0x5f801000 0xe00>;
Masahiro Yamada149c7512014-11-26 18:34:01 +0900191 };
Masahiro Yamadaf5fd7af2014-12-06 00:03:23 +0900192
Masahiro Yamadaedcfaeb2015-06-30 18:27:00 +0900193 timer@60000200 {
194 compatible = "arm,cortex-a9-global-timer";
195 reg = <0x60000200 0x20>;
196 interrupts = <1 11 0x104>;
197 clocks = <&arm_timer_clk>;
198 };
199
200 timer@60000600 {
201 compatible = "arm,cortex-a9-twd-timer";
202 reg = <0x60000600 0x20>;
203 interrupts = <1 13 0x104>;
204 clocks = <&arm_timer_clk>;
205 };
206
207 intc: interrupt-controller@60001000 {
208 compatible = "arm,cortex-a9-gic";
209 #interrupt-cells = <3>;
210 interrupt-controller;
211 reg = <0x60001000 0x1000>,
212 <0x60000100 0x100>;
213 };
214
Masahiro Yamadaf5fd7af2014-12-06 00:03:23 +0900215 nand: nand@68000000 {
216 compatible = "denali,denali-nand-dt";
217 reg = <0x68000000 0x20>, <0x68100000 0x1000>;
218 reg-names = "nand_data", "denali_reg";
219 };
Masahiro Yamada509eb672014-11-26 18:33:59 +0900220 };
221};
Masahiro Yamadad243c182015-08-28 22:33:13 +0900222
223/include/ "uniphier-pinctrl.dtsi"