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Nobuhiro Iwamatsu3dab3e02011-11-14 18:27:04 +00001/*
2 * Copyright (C) 2011 Renesas Solutions Corp.
3 * Copyright (C) 2011 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License as
7 * published by the Free Software Foundation; either version 2 of
8 * the License, or (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
18 * MA 02111-1307 USA
19 */
20
21#include <common.h>
22#include <asm/io.h>
23
24/* Every register is 32bit aligned, but only 8bits in size */
25#define ureg(name) u8 name; u8 __pad_##name##0; u16 __pad_##name##1;
26struct sh_i2c {
27 ureg(icdr);
28 ureg(iccr);
29 ureg(icsr);
30 ureg(icic);
31 ureg(iccl);
32 ureg(icch);
33};
34#undef ureg
35
36static struct sh_i2c *base;
37
38/* ICCR */
39#define SH_I2C_ICCR_ICE (1 << 7)
40#define SH_I2C_ICCR_RACK (1 << 6)
41#define SH_I2C_ICCR_RTS (1 << 4)
42#define SH_I2C_ICCR_BUSY (1 << 2)
43#define SH_I2C_ICCR_SCP (1 << 0)
44
45/* ICSR / ICIC */
Tetsuyuki Kobayashi57d7c802012-09-13 19:07:57 +000046#define SH_IC_BUSY (1 << 4)
Nobuhiro Iwamatsu3dab3e02011-11-14 18:27:04 +000047#define SH_IC_TACK (1 << 2)
48#define SH_IC_WAIT (1 << 1)
49#define SH_IC_DTE (1 << 0)
50
Tetsuyuki Kobayashib1af67f2012-09-13 19:07:56 +000051#ifdef CONFIG_SH_I2C_8BIT
52/* store 8th bit of iccl and icch in ICIC register */
53#define SH_I2C_ICIC_ICCLB8 (1 << 7)
54#define SH_I2C_ICIC_ICCHB8 (1 << 6)
55#endif
56
57static u16 iccl, icch;
Nobuhiro Iwamatsu3dab3e02011-11-14 18:27:04 +000058
59#define IRQ_WAIT 1000
60
Nobuhiro Iwamatsu3dab3e02011-11-14 18:27:04 +000061static void irq_dte(struct sh_i2c *base)
62{
63 int i;
64
65 for (i = 0 ; i < IRQ_WAIT ; i++) {
66 if (SH_IC_DTE & readb(&base->icsr))
67 break;
68 udelay(10);
69 }
70}
71
Tetsuyuki Kobayashid042d712012-09-13 19:08:00 +000072static int irq_dte_with_tack(struct sh_i2c *base)
73{
74 int i;
75
76 for (i = 0 ; i < IRQ_WAIT ; i++) {
77 if (SH_IC_DTE & readb(&base->icsr))
78 break;
79 if (SH_IC_TACK & readb(&base->icsr))
80 return -1;
81 udelay(10);
82 }
83 return 0;
84}
85
Nobuhiro Iwamatsu3dab3e02011-11-14 18:27:04 +000086static void irq_busy(struct sh_i2c *base)
87{
88 int i;
89
90 for (i = 0 ; i < IRQ_WAIT ; i++) {
91 if (!(SH_IC_BUSY & readb(&base->icsr)))
92 break;
93 udelay(10);
94 }
95}
96
Tetsuyuki Kobayashid042d712012-09-13 19:08:00 +000097static int i2c_set_addr(struct sh_i2c *base, u8 id, u8 reg, int stop)
Nobuhiro Iwamatsu3dab3e02011-11-14 18:27:04 +000098{
Tetsuyuki Kobayashid042d712012-09-13 19:08:00 +000099 u8 icic = SH_IC_TACK;
Tetsuyuki Kobayashib1af67f2012-09-13 19:07:56 +0000100
Tetsuyuki Kobayashif5390942012-09-13 19:08:05 +0000101 clrbits_8(&base->iccr, SH_I2C_ICCR_ICE);
102 setbits_8(&base->iccr, SH_I2C_ICCR_ICE);
Nobuhiro Iwamatsu3dab3e02011-11-14 18:27:04 +0000103
Tetsuyuki Kobayashib1af67f2012-09-13 19:07:56 +0000104 writeb(iccl & 0xff, &base->iccl);
105 writeb(icch & 0xff, &base->icch);
106#ifdef CONFIG_SH_I2C_8BIT
107 if (iccl > 0xff)
108 icic |= SH_I2C_ICIC_ICCLB8;
109 if (icch > 0xff)
110 icic |= SH_I2C_ICIC_ICCHB8;
111#endif
112 writeb(icic, &base->icic);
Nobuhiro Iwamatsu3dab3e02011-11-14 18:27:04 +0000113
114 writeb((SH_I2C_ICCR_ICE|SH_I2C_ICCR_RTS|SH_I2C_ICCR_BUSY), &base->iccr);
115 irq_dte(base);
116
Tetsuyuki Kobayashif5390942012-09-13 19:08:05 +0000117 clrbits_8(&base->icsr, SH_IC_TACK);
Nobuhiro Iwamatsu3dab3e02011-11-14 18:27:04 +0000118 writeb(id << 1, &base->icdr);
Tetsuyuki Kobayashid042d712012-09-13 19:08:00 +0000119 if (irq_dte_with_tack(base) != 0)
120 return -1;
Nobuhiro Iwamatsu3dab3e02011-11-14 18:27:04 +0000121
122 writeb(reg, &base->icdr);
123 if (stop)
124 writeb((SH_I2C_ICCR_ICE|SH_I2C_ICCR_RTS), &base->iccr);
125
Tetsuyuki Kobayashid042d712012-09-13 19:08:00 +0000126 if (irq_dte_with_tack(base) != 0)
127 return -1;
128 return 0;
Nobuhiro Iwamatsu3dab3e02011-11-14 18:27:04 +0000129}
130
131static void i2c_finish(struct sh_i2c *base)
132{
133 writeb(0, &base->icsr);
Tetsuyuki Kobayashif5390942012-09-13 19:08:05 +0000134 clrbits_8(&base->iccr, SH_I2C_ICCR_ICE);
Nobuhiro Iwamatsu3dab3e02011-11-14 18:27:04 +0000135}
136
Tetsuyuki Kobayashi0e5fb332012-09-13 19:08:01 +0000137static int i2c_raw_write(struct sh_i2c *base, u8 id, u8 reg, u8 val)
Nobuhiro Iwamatsu3dab3e02011-11-14 18:27:04 +0000138{
Tetsuyuki Kobayashi0e5fb332012-09-13 19:08:01 +0000139 int ret = -1;
140 if (i2c_set_addr(base, id, reg, 0) != 0)
141 goto exit0;
Nobuhiro Iwamatsu3dab3e02011-11-14 18:27:04 +0000142 udelay(10);
143
144 writeb(val, &base->icdr);
Tetsuyuki Kobayashi0e5fb332012-09-13 19:08:01 +0000145 if (irq_dte_with_tack(base) != 0)
146 goto exit0;
Nobuhiro Iwamatsu3dab3e02011-11-14 18:27:04 +0000147
148 writeb((SH_I2C_ICCR_ICE | SH_I2C_ICCR_RTS), &base->iccr);
Tetsuyuki Kobayashi0e5fb332012-09-13 19:08:01 +0000149 if (irq_dte_with_tack(base) != 0)
150 goto exit0;
Nobuhiro Iwamatsu3dab3e02011-11-14 18:27:04 +0000151 irq_busy(base);
Tetsuyuki Kobayashi0e5fb332012-09-13 19:08:01 +0000152 ret = 0;
153exit0:
Nobuhiro Iwamatsu3dab3e02011-11-14 18:27:04 +0000154 i2c_finish(base);
Tetsuyuki Kobayashi0e5fb332012-09-13 19:08:01 +0000155 return ret;
Nobuhiro Iwamatsu3dab3e02011-11-14 18:27:04 +0000156}
157
Tetsuyuki Kobayashi0e5fb332012-09-13 19:08:01 +0000158static int i2c_raw_read(struct sh_i2c *base, u8 id, u8 reg)
Nobuhiro Iwamatsu3dab3e02011-11-14 18:27:04 +0000159{
Tetsuyuki Kobayashi0e5fb332012-09-13 19:08:01 +0000160 int ret = -1;
Nobuhiro Iwamatsu3dab3e02011-11-14 18:27:04 +0000161
Tetsuyuki Kobayashi3ce27032012-09-13 19:07:58 +0000162#if defined(CONFIG_SH73A0)
Tetsuyuki Kobayashi0e5fb332012-09-13 19:08:01 +0000163 if (i2c_set_addr(base, id, reg, 0) != 0)
164 goto exit0;
Tetsuyuki Kobayashi3ce27032012-09-13 19:07:58 +0000165#else
Tetsuyuki Kobayashi0e5fb332012-09-13 19:08:01 +0000166 if (i2c_set_addr(base, id, reg, 1) != 0)
167 goto exit0;
Nobuhiro Iwamatsu3dab3e02011-11-14 18:27:04 +0000168 udelay(100);
Tetsuyuki Kobayashi3ce27032012-09-13 19:07:58 +0000169#endif
Nobuhiro Iwamatsu3dab3e02011-11-14 18:27:04 +0000170
171 writeb((SH_I2C_ICCR_ICE|SH_I2C_ICCR_RTS|SH_I2C_ICCR_BUSY), &base->iccr);
172 irq_dte(base);
173
174 writeb(id << 1 | 0x01, &base->icdr);
Tetsuyuki Kobayashi0e5fb332012-09-13 19:08:01 +0000175 if (irq_dte_with_tack(base) != 0)
176 goto exit0;
Nobuhiro Iwamatsu3dab3e02011-11-14 18:27:04 +0000177
178 writeb((SH_I2C_ICCR_ICE|SH_I2C_ICCR_SCP), &base->iccr);
Tetsuyuki Kobayashi0e5fb332012-09-13 19:08:01 +0000179 if (irq_dte_with_tack(base) != 0)
180 goto exit0;
Nobuhiro Iwamatsu3dab3e02011-11-14 18:27:04 +0000181
Tetsuyuki Kobayashi0e5fb332012-09-13 19:08:01 +0000182 ret = readb(&base->icdr) & 0xff;
Nobuhiro Iwamatsu3dab3e02011-11-14 18:27:04 +0000183
184 writeb((SH_I2C_ICCR_ICE|SH_I2C_ICCR_RACK), &base->iccr);
185 readb(&base->icdr); /* Dummy read */
186 irq_busy(base);
Tetsuyuki Kobayashi0e5fb332012-09-13 19:08:01 +0000187exit0:
Nobuhiro Iwamatsu3dab3e02011-11-14 18:27:04 +0000188 i2c_finish(base);
189
190 return ret;
191}
192
193#ifdef CONFIG_I2C_MULTI_BUS
194static unsigned int current_bus;
195
196/**
197 * i2c_set_bus_num - change active I2C bus
198 * @bus: bus index, zero based
199 * @returns: 0 on success, non-0 on failure
200 */
201int i2c_set_bus_num(unsigned int bus)
202{
203 if ((bus < 0) || (bus >= CONFIG_SYS_MAX_I2C_BUS)) {
204 printf("Bad bus: %d\n", bus);
205 return -1;
206 }
207
208 switch (bus) {
209 case 0:
210 base = (void *)CONFIG_SH_I2C_BASE0;
211 break;
212 case 1:
213 base = (void *)CONFIG_SH_I2C_BASE1;
214 break;
Tetsuyuki Kobayashi020ec722012-09-13 19:07:59 +0000215#ifdef CONFIG_SH_I2C_BASE2
216 case 2:
217 base = (void *)CONFIG_SH_I2C_BASE2;
218 break;
219#endif
220#ifdef CONFIG_SH_I2C_BASE3
221 case 3:
222 base = (void *)CONFIG_SH_I2C_BASE3;
223 break;
224#endif
225#ifdef CONFIG_SH_I2C_BASE4
226 case 4:
227 base = (void *)CONFIG_SH_I2C_BASE4;
228 break;
229#endif
Nobuhiro Iwamatsu3dab3e02011-11-14 18:27:04 +0000230 default:
231 return -1;
232 }
233 current_bus = bus;
234
235 return 0;
236}
237
238/**
239 * i2c_get_bus_num - returns index of active I2C bus
240 */
241unsigned int i2c_get_bus_num(void)
242{
243 return current_bus;
244}
245#endif
246
247#define SH_I2C_ICCL_CALC(clk, date, t_low, t_high) \
248 ((clk / rate) * (t_low / t_low + t_high))
249#define SH_I2C_ICCH_CALC(clk, date, t_low, t_high) \
250 ((clk / rate) * (t_high / t_low + t_high))
251
252void i2c_init(int speed, int slaveaddr)
253{
254 int num, denom, tmp;
255
256#ifdef CONFIG_I2C_MULTI_BUS
257 current_bus = 0;
258#endif
259 base = (struct sh_i2c *)CONFIG_SH_I2C_BASE0;
260
261 /*
262 * Calculate the value for iccl. From the data sheet:
263 * iccl = (p-clock / transfer-rate) * (L / (L + H))
264 * where L and H are the SCL low and high ratio.
265 */
266 num = CONFIG_SH_I2C_CLOCK * CONFIG_SH_I2C_DATA_LOW;
267 denom = speed * (CONFIG_SH_I2C_DATA_HIGH + CONFIG_SH_I2C_DATA_LOW);
268 tmp = num * 10 / denom;
269 if (tmp % 10 >= 5)
Tetsuyuki Kobayashib1af67f2012-09-13 19:07:56 +0000270 iccl = (u16)((num/denom) + 1);
Nobuhiro Iwamatsu3dab3e02011-11-14 18:27:04 +0000271 else
Tetsuyuki Kobayashib1af67f2012-09-13 19:07:56 +0000272 iccl = (u16)(num/denom);
Nobuhiro Iwamatsu3dab3e02011-11-14 18:27:04 +0000273
274 /* Calculate the value for icch. From the data sheet:
275 icch = (p clock / transfer rate) * (H / (L + H)) */
276 num = CONFIG_SH_I2C_CLOCK * CONFIG_SH_I2C_DATA_HIGH;
277 tmp = num * 10 / denom;
278 if (tmp % 10 >= 5)
Tetsuyuki Kobayashib1af67f2012-09-13 19:07:56 +0000279 icch = (u16)((num/denom) + 1);
Nobuhiro Iwamatsu3dab3e02011-11-14 18:27:04 +0000280 else
Tetsuyuki Kobayashib1af67f2012-09-13 19:07:56 +0000281 icch = (u16)(num/denom);
Nobuhiro Iwamatsu3dab3e02011-11-14 18:27:04 +0000282}
283
284/*
285 * i2c_read: - Read multiple bytes from an i2c device
286 *
287 * The higher level routines take into account that this function is only
288 * called with len < page length of the device (see configuration file)
289 *
290 * @chip: address of the chip which is to be read
291 * @addr: i2c data address within the chip
292 * @alen: length of the i2c data address (1..2 bytes)
293 * @buffer: where to write the data
294 * @len: how much byte do we want to read
295 * @return: 0 in case of success
296 */
297int i2c_read(u8 chip, u32 addr, int alen, u8 *buffer, int len)
298{
Tetsuyuki Kobayashi0e5fb332012-09-13 19:08:01 +0000299 int ret;
Nobuhiro Iwamatsu3dab3e02011-11-14 18:27:04 +0000300 int i = 0;
Tetsuyuki Kobayashi0e5fb332012-09-13 19:08:01 +0000301 for (i = 0 ; i < len ; i++) {
302 ret = i2c_raw_read(base, chip, addr + i);
303 if (ret < 0)
304 return -1;
305 buffer[i] = ret & 0xff;
306 }
Nobuhiro Iwamatsu3dab3e02011-11-14 18:27:04 +0000307 return 0;
308}
309
310/*
311 * i2c_write: - Write multiple bytes to an i2c device
312 *
313 * The higher level routines take into account that this function is only
314 * called with len < page length of the device (see configuration file)
315 *
316 * @chip: address of the chip which is to be written
317 * @addr: i2c data address within the chip
318 * @alen: length of the i2c data address (1..2 bytes)
319 * @buffer: where to find the data to be written
320 * @len: how much byte do we want to read
321 * @return: 0 in case of success
322 */
323int i2c_write(u8 chip, u32 addr, int alen, u8 *buffer, int len)
324{
325 int i = 0;
326 for (i = 0; i < len ; i++)
Tetsuyuki Kobayashi0e5fb332012-09-13 19:08:01 +0000327 if (i2c_raw_write(base, chip, addr + i, buffer[i]) != 0)
328 return -1;
Nobuhiro Iwamatsu3dab3e02011-11-14 18:27:04 +0000329 return 0;
330}
331
332/*
333 * i2c_probe: - Test if a chip answers for a given i2c address
334 *
335 * @chip: address of the chip which is searched for
336 * @return: 0 if a chip was found, -1 otherwhise
337 */
338int i2c_probe(u8 chip)
339{
Tetsuyuki Kobayashid042d712012-09-13 19:08:00 +0000340 int ret;
341
342 ret = i2c_set_addr(base, chip, 0, 1);
343 i2c_finish(base);
344 return ret;
Nobuhiro Iwamatsu3dab3e02011-11-14 18:27:04 +0000345}