Tom Rini | 83d290c | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
Marek Vasut | 0d4e850 | 2011-11-08 23:18:16 +0000 | [diff] [blame] | 2 | /* |
| 3 | * Freescale i.MX28 NAND flash driver |
| 4 | * |
| 5 | * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com> |
| 6 | * on behalf of DENX Software Engineering GmbH |
| 7 | * |
| 8 | * Based on code from LTIB: |
| 9 | * Freescale GPMI NFC NAND Flash Driver |
| 10 | * |
| 11 | * Copyright (C) 2010 Freescale Semiconductor, Inc. |
| 12 | * Copyright (C) 2008 Embedded Alley Solutions, Inc. |
Marek Vasut | 0d4e850 | 2011-11-08 23:18:16 +0000 | [diff] [blame] | 13 | */ |
| 14 | |
Tom Warren | 651eb73 | 2012-09-10 08:47:51 -0700 | [diff] [blame] | 15 | #include <common.h> |
Marek Vasut | 0d4e850 | 2011-11-08 23:18:16 +0000 | [diff] [blame] | 16 | #include <linux/mtd/mtd.h> |
Masahiro Yamada | 6ae3900 | 2017-11-30 13:45:24 +0900 | [diff] [blame] | 17 | #include <linux/mtd/rawnand.h> |
Marek Vasut | 0d4e850 | 2011-11-08 23:18:16 +0000 | [diff] [blame] | 18 | #include <linux/types.h> |
Marek Vasut | 0d4e850 | 2011-11-08 23:18:16 +0000 | [diff] [blame] | 19 | #include <malloc.h> |
Stefan Agner | 5346c31 | 2018-06-22 17:19:47 +0200 | [diff] [blame] | 20 | #include <nand.h> |
Masahiro Yamada | 1221ce4 | 2016-09-21 11:28:55 +0900 | [diff] [blame] | 21 | #include <linux/errno.h> |
Marek Vasut | 0d4e850 | 2011-11-08 23:18:16 +0000 | [diff] [blame] | 22 | #include <asm/io.h> |
| 23 | #include <asm/arch/clock.h> |
| 24 | #include <asm/arch/imx-regs.h> |
Stefano Babic | 552a848 | 2017-06-29 10:16:06 +0200 | [diff] [blame] | 25 | #include <asm/mach-imx/regs-bch.h> |
| 26 | #include <asm/mach-imx/regs-gpmi.h> |
Marek Vasut | 0d4e850 | 2011-11-08 23:18:16 +0000 | [diff] [blame] | 27 | #include <asm/arch/sys_proto.h> |
Stefano Babic | 552a848 | 2017-06-29 10:16:06 +0200 | [diff] [blame] | 28 | #include <asm/mach-imx/dma.h> |
Stefan Agner | 9345943 | 2018-06-22 17:19:46 +0200 | [diff] [blame] | 29 | #include "mxs_nand.h" |
Marek Vasut | 0d4e850 | 2011-11-08 23:18:16 +0000 | [diff] [blame] | 30 | |
| 31 | #define MXS_NAND_DMA_DESCRIPTOR_COUNT 4 |
| 32 | |
Peng Fan | bedaa84 | 2015-12-22 17:04:23 +0800 | [diff] [blame] | 33 | #if (defined(CONFIG_MX6) || defined(CONFIG_MX7)) |
Stefan Roese | ae695b1 | 2013-04-15 21:14:12 +0000 | [diff] [blame] | 34 | #define MXS_NAND_CHUNK_DATA_CHUNK_SIZE_SHIFT 2 |
| 35 | #else |
| 36 | #define MXS_NAND_CHUNK_DATA_CHUNK_SIZE_SHIFT 0 |
| 37 | #endif |
Marek Vasut | 0d4e850 | 2011-11-08 23:18:16 +0000 | [diff] [blame] | 38 | #define MXS_NAND_METADATA_SIZE 10 |
Jörg Krause | 1fbdb70 | 2015-04-15 09:27:22 +0200 | [diff] [blame] | 39 | #define MXS_NAND_BITS_PER_ECC_LEVEL 13 |
Stefan Agner | 2a83c95 | 2016-08-01 23:55:18 -0700 | [diff] [blame] | 40 | |
| 41 | #if !defined(CONFIG_SYS_CACHELINE_SIZE) || CONFIG_SYS_CACHELINE_SIZE < 32 |
Marek Vasut | 0d4e850 | 2011-11-08 23:18:16 +0000 | [diff] [blame] | 42 | #define MXS_NAND_COMMAND_BUFFER_SIZE 32 |
Stefan Agner | 2a83c95 | 2016-08-01 23:55:18 -0700 | [diff] [blame] | 43 | #else |
| 44 | #define MXS_NAND_COMMAND_BUFFER_SIZE CONFIG_SYS_CACHELINE_SIZE |
| 45 | #endif |
Marek Vasut | 0d4e850 | 2011-11-08 23:18:16 +0000 | [diff] [blame] | 46 | |
| 47 | #define MXS_NAND_BCH_TIMEOUT 10000 |
| 48 | |
Stefan Agner | 28897e8 | 2018-06-22 17:19:49 +0200 | [diff] [blame^] | 49 | /** |
| 50 | * @gf_len: The length of Galois Field. (e.g., 13 or 14) |
| 51 | * @ecc_strength: A number that describes the strength of the ECC |
| 52 | * algorithm. |
| 53 | * @ecc_chunk_size: The size, in bytes, of a single ECC chunk. Note |
| 54 | * the first chunk in the page includes both data and |
| 55 | * metadata, so it's a bit larger than this value. |
| 56 | * @ecc_chunk_count: The number of ECC chunks in the page, |
| 57 | * @block_mark_byte_offset: The byte offset in the ECC-based page view at |
| 58 | * which the underlying physical block mark appears. |
| 59 | * @block_mark_bit_offset: The bit offset into the ECC-based page view at |
| 60 | * which the underlying physical block mark appears. |
| 61 | */ |
| 62 | struct bch_geometry { |
| 63 | unsigned int gf_len; |
| 64 | unsigned int ecc_strength; |
| 65 | unsigned int ecc_chunk_size; |
| 66 | unsigned int ecc_chunk_count; |
| 67 | unsigned int block_mark_byte_offset; |
| 68 | unsigned int block_mark_bit_offset; |
| 69 | }; |
| 70 | |
Marek Vasut | 0d4e850 | 2011-11-08 23:18:16 +0000 | [diff] [blame] | 71 | struct mxs_nand_info { |
Stefan Agner | 5346c31 | 2018-06-22 17:19:47 +0200 | [diff] [blame] | 72 | struct nand_chip chip; |
Marek Vasut | 0d4e850 | 2011-11-08 23:18:16 +0000 | [diff] [blame] | 73 | int cur_chip; |
| 74 | |
| 75 | uint32_t cmd_queue_len; |
Marek Vasut | 6b9408e | 2012-03-15 18:33:19 +0000 | [diff] [blame] | 76 | uint32_t data_buf_size; |
Stefan Agner | 28897e8 | 2018-06-22 17:19:49 +0200 | [diff] [blame^] | 77 | struct bch_geometry bch_geometry; |
Marek Vasut | 0d4e850 | 2011-11-08 23:18:16 +0000 | [diff] [blame] | 78 | |
| 79 | uint8_t *cmd_buf; |
| 80 | uint8_t *data_buf; |
| 81 | uint8_t *oob_buf; |
| 82 | |
| 83 | uint8_t marking_block_bad; |
| 84 | uint8_t raw_oob_mode; |
| 85 | |
| 86 | /* Functions with altered behaviour */ |
| 87 | int (*hooked_read_oob)(struct mtd_info *mtd, |
| 88 | loff_t from, struct mtd_oob_ops *ops); |
| 89 | int (*hooked_write_oob)(struct mtd_info *mtd, |
| 90 | loff_t to, struct mtd_oob_ops *ops); |
| 91 | int (*hooked_block_markbad)(struct mtd_info *mtd, |
| 92 | loff_t ofs); |
| 93 | |
| 94 | /* DMA descriptors */ |
| 95 | struct mxs_dma_desc **desc; |
| 96 | uint32_t desc_index; |
| 97 | }; |
| 98 | |
| 99 | struct nand_ecclayout fake_ecc_layout; |
| 100 | |
Marek Vasut | 6b9408e | 2012-03-15 18:33:19 +0000 | [diff] [blame] | 101 | /* |
| 102 | * Cache management functions |
| 103 | */ |
| 104 | #ifndef CONFIG_SYS_DCACHE_OFF |
| 105 | static void mxs_nand_flush_data_buf(struct mxs_nand_info *info) |
| 106 | { |
| 107 | uint32_t addr = (uint32_t)info->data_buf; |
| 108 | |
| 109 | flush_dcache_range(addr, addr + info->data_buf_size); |
| 110 | } |
| 111 | |
| 112 | static void mxs_nand_inval_data_buf(struct mxs_nand_info *info) |
| 113 | { |
| 114 | uint32_t addr = (uint32_t)info->data_buf; |
| 115 | |
| 116 | invalidate_dcache_range(addr, addr + info->data_buf_size); |
| 117 | } |
| 118 | |
| 119 | static void mxs_nand_flush_cmd_buf(struct mxs_nand_info *info) |
| 120 | { |
| 121 | uint32_t addr = (uint32_t)info->cmd_buf; |
| 122 | |
| 123 | flush_dcache_range(addr, addr + MXS_NAND_COMMAND_BUFFER_SIZE); |
| 124 | } |
| 125 | #else |
| 126 | static inline void mxs_nand_flush_data_buf(struct mxs_nand_info *info) {} |
| 127 | static inline void mxs_nand_inval_data_buf(struct mxs_nand_info *info) {} |
| 128 | static inline void mxs_nand_flush_cmd_buf(struct mxs_nand_info *info) {} |
| 129 | #endif |
| 130 | |
Marek Vasut | 0d4e850 | 2011-11-08 23:18:16 +0000 | [diff] [blame] | 131 | static struct mxs_dma_desc *mxs_nand_get_dma_desc(struct mxs_nand_info *info) |
| 132 | { |
| 133 | struct mxs_dma_desc *desc; |
| 134 | |
| 135 | if (info->desc_index >= MXS_NAND_DMA_DESCRIPTOR_COUNT) { |
| 136 | printf("MXS NAND: Too many DMA descriptors requested\n"); |
| 137 | return NULL; |
| 138 | } |
| 139 | |
| 140 | desc = info->desc[info->desc_index]; |
| 141 | info->desc_index++; |
| 142 | |
| 143 | return desc; |
| 144 | } |
| 145 | |
| 146 | static void mxs_nand_return_dma_descs(struct mxs_nand_info *info) |
| 147 | { |
| 148 | int i; |
| 149 | struct mxs_dma_desc *desc; |
| 150 | |
| 151 | for (i = 0; i < info->desc_index; i++) { |
| 152 | desc = info->desc[i]; |
| 153 | memset(desc, 0, sizeof(struct mxs_dma_desc)); |
| 154 | desc->address = (dma_addr_t)desc; |
| 155 | } |
| 156 | |
| 157 | info->desc_index = 0; |
| 158 | } |
| 159 | |
Marek Vasut | 0d4e850 | 2011-11-08 23:18:16 +0000 | [diff] [blame] | 160 | static uint32_t mxs_nand_aux_status_offset(void) |
| 161 | { |
| 162 | return (MXS_NAND_METADATA_SIZE + 0x3) & ~0x3; |
| 163 | } |
| 164 | |
Stefan Agner | 28897e8 | 2018-06-22 17:19:49 +0200 | [diff] [blame^] | 165 | static inline int mxs_nand_calc_mark_offset(struct bch_geometry *geo, |
| 166 | uint32_t page_data_size) |
Marek Vasut | 0d4e850 | 2011-11-08 23:18:16 +0000 | [diff] [blame] | 167 | { |
Stefan Agner | 28897e8 | 2018-06-22 17:19:49 +0200 | [diff] [blame^] | 168 | uint32_t chunk_data_size_in_bits = geo->ecc_chunk_size * 8; |
| 169 | uint32_t chunk_ecc_size_in_bits = geo->ecc_strength * geo->gf_len; |
Marek Vasut | 0d4e850 | 2011-11-08 23:18:16 +0000 | [diff] [blame] | 170 | uint32_t chunk_total_size_in_bits; |
| 171 | uint32_t block_mark_chunk_number; |
| 172 | uint32_t block_mark_chunk_bit_offset; |
| 173 | uint32_t block_mark_bit_offset; |
| 174 | |
Marek Vasut | 0d4e850 | 2011-11-08 23:18:16 +0000 | [diff] [blame] | 175 | chunk_total_size_in_bits = |
| 176 | chunk_data_size_in_bits + chunk_ecc_size_in_bits; |
| 177 | |
| 178 | /* Compute the bit offset of the block mark within the physical page. */ |
| 179 | block_mark_bit_offset = page_data_size * 8; |
| 180 | |
| 181 | /* Subtract the metadata bits. */ |
| 182 | block_mark_bit_offset -= MXS_NAND_METADATA_SIZE * 8; |
| 183 | |
| 184 | /* |
| 185 | * Compute the chunk number (starting at zero) in which the block mark |
| 186 | * appears. |
| 187 | */ |
| 188 | block_mark_chunk_number = |
| 189 | block_mark_bit_offset / chunk_total_size_in_bits; |
| 190 | |
| 191 | /* |
| 192 | * Compute the bit offset of the block mark within its chunk, and |
| 193 | * validate it. |
| 194 | */ |
| 195 | block_mark_chunk_bit_offset = block_mark_bit_offset - |
| 196 | (block_mark_chunk_number * chunk_total_size_in_bits); |
| 197 | |
| 198 | if (block_mark_chunk_bit_offset > chunk_data_size_in_bits) |
Stefan Agner | 28897e8 | 2018-06-22 17:19:49 +0200 | [diff] [blame^] | 199 | return -EINVAL; |
Marek Vasut | 0d4e850 | 2011-11-08 23:18:16 +0000 | [diff] [blame] | 200 | |
| 201 | /* |
| 202 | * Now that we know the chunk number in which the block mark appears, |
| 203 | * we can subtract all the ECC bits that appear before it. |
| 204 | */ |
| 205 | block_mark_bit_offset -= |
| 206 | block_mark_chunk_number * chunk_ecc_size_in_bits; |
| 207 | |
Stefan Agner | 28897e8 | 2018-06-22 17:19:49 +0200 | [diff] [blame^] | 208 | geo->block_mark_byte_offset = block_mark_bit_offset >> 3; |
| 209 | geo->block_mark_bit_offset = block_mark_bit_offset & 0x7; |
| 210 | |
| 211 | return 0; |
Marek Vasut | 0d4e850 | 2011-11-08 23:18:16 +0000 | [diff] [blame] | 212 | } |
| 213 | |
Stefan Agner | 28897e8 | 2018-06-22 17:19:49 +0200 | [diff] [blame^] | 214 | static inline int mxs_nand_calc_ecc_layout(struct bch_geometry *geo, |
| 215 | struct mtd_info *mtd) |
Marek Vasut | 0d4e850 | 2011-11-08 23:18:16 +0000 | [diff] [blame] | 216 | { |
Stefan Agner | 28897e8 | 2018-06-22 17:19:49 +0200 | [diff] [blame^] | 217 | unsigned int max_ecc_strength_supported; |
Marek Vasut | 0d4e850 | 2011-11-08 23:18:16 +0000 | [diff] [blame] | 218 | |
Stefan Agner | 28897e8 | 2018-06-22 17:19:49 +0200 | [diff] [blame^] | 219 | /* The default for the length of Galois Field. */ |
| 220 | geo->gf_len = 13; |
| 221 | |
| 222 | /* The default for chunk size. */ |
| 223 | geo->ecc_chunk_size = 512; |
| 224 | |
| 225 | if (geo->ecc_chunk_size < mtd->oobsize) { |
| 226 | geo->gf_len = 14; |
| 227 | geo->ecc_chunk_size *= 2; |
| 228 | } |
| 229 | |
| 230 | if (mtd->oobsize > geo->ecc_chunk_size) { |
| 231 | printf("Not support the NAND chips whose oob size is larger then %d bytes!\n", |
| 232 | geo->ecc_chunk_size); |
| 233 | return -EINVAL; |
| 234 | } |
| 235 | |
| 236 | geo->ecc_chunk_count = mtd->writesize / geo->ecc_chunk_size; |
| 237 | |
| 238 | /* Refer to Chapter 17 for i.MX6DQ, Chapter 18 for i.MX6SX */ |
| 239 | if (is_mx6sx() || is_mx7()) |
| 240 | max_ecc_strength_supported = 62; |
| 241 | else |
| 242 | max_ecc_strength_supported = 40; |
| 243 | |
| 244 | /* |
| 245 | * Determine the ECC layout with the formula: |
| 246 | * ECC bits per chunk = (total page spare data bits) / |
| 247 | * (bits per ECC level) / (chunks per page) |
| 248 | * where: |
| 249 | * total page spare data bits = |
| 250 | * (page oob size - meta data size) * (bits per byte) |
| 251 | */ |
| 252 | geo->ecc_strength = ((mtd->oobsize - MXS_NAND_METADATA_SIZE) * 8) |
| 253 | / (geo->gf_len * geo->ecc_chunk_count); |
| 254 | |
| 255 | geo->ecc_strength = min(round_down(geo->ecc_strength, 2), max_ecc_strength_supported); |
| 256 | |
| 257 | if (mxs_nand_calc_mark_offset(geo, mtd->writesize) < 0) |
| 258 | return -EINVAL; |
| 259 | |
| 260 | return 0; |
Marek Vasut | 0d4e850 | 2011-11-08 23:18:16 +0000 | [diff] [blame] | 261 | } |
| 262 | |
| 263 | /* |
| 264 | * Wait for BCH complete IRQ and clear the IRQ |
| 265 | */ |
| 266 | static int mxs_nand_wait_for_bch_complete(void) |
| 267 | { |
Otavio Salvador | 9c47114 | 2012-08-05 09:05:31 +0000 | [diff] [blame] | 268 | struct mxs_bch_regs *bch_regs = (struct mxs_bch_regs *)MXS_BCH_BASE; |
Marek Vasut | 0d4e850 | 2011-11-08 23:18:16 +0000 | [diff] [blame] | 269 | int timeout = MXS_NAND_BCH_TIMEOUT; |
| 270 | int ret; |
| 271 | |
Otavio Salvador | fa7a51c | 2012-08-13 09:53:12 +0000 | [diff] [blame] | 272 | ret = mxs_wait_mask_set(&bch_regs->hw_bch_ctrl_reg, |
Marek Vasut | 0d4e850 | 2011-11-08 23:18:16 +0000 | [diff] [blame] | 273 | BCH_CTRL_COMPLETE_IRQ, timeout); |
| 274 | |
| 275 | writel(BCH_CTRL_COMPLETE_IRQ, &bch_regs->hw_bch_ctrl_clr); |
| 276 | |
| 277 | return ret; |
| 278 | } |
| 279 | |
| 280 | /* |
| 281 | * This is the function that we install in the cmd_ctrl function pointer of the |
| 282 | * owning struct nand_chip. The only functions in the reference implementation |
| 283 | * that use these functions pointers are cmdfunc and select_chip. |
| 284 | * |
| 285 | * In this driver, we implement our own select_chip, so this function will only |
| 286 | * be called by the reference implementation's cmdfunc. For this reason, we can |
| 287 | * ignore the chip enable bit and concentrate only on sending bytes to the NAND |
| 288 | * Flash. |
| 289 | */ |
| 290 | static void mxs_nand_cmd_ctrl(struct mtd_info *mtd, int data, unsigned int ctrl) |
| 291 | { |
Scott Wood | 17cb4b8 | 2016-05-30 13:57:56 -0500 | [diff] [blame] | 292 | struct nand_chip *nand = mtd_to_nand(mtd); |
| 293 | struct mxs_nand_info *nand_info = nand_get_controller_data(nand); |
Marek Vasut | 0d4e850 | 2011-11-08 23:18:16 +0000 | [diff] [blame] | 294 | struct mxs_dma_desc *d; |
| 295 | uint32_t channel = MXS_DMA_CHANNEL_AHB_APBH_GPMI0 + nand_info->cur_chip; |
| 296 | int ret; |
| 297 | |
| 298 | /* |
| 299 | * If this condition is true, something is _VERY_ wrong in MTD |
| 300 | * subsystem! |
| 301 | */ |
| 302 | if (nand_info->cmd_queue_len == MXS_NAND_COMMAND_BUFFER_SIZE) { |
| 303 | printf("MXS NAND: Command queue too long\n"); |
| 304 | return; |
| 305 | } |
| 306 | |
| 307 | /* |
| 308 | * Every operation begins with a command byte and a series of zero or |
| 309 | * more address bytes. These are distinguished by either the Address |
| 310 | * Latch Enable (ALE) or Command Latch Enable (CLE) signals being |
| 311 | * asserted. When MTD is ready to execute the command, it will |
| 312 | * deasert both latch enables. |
| 313 | * |
| 314 | * Rather than run a separate DMA operation for every single byte, we |
| 315 | * queue them up and run a single DMA operation for the entire series |
| 316 | * of command and data bytes. |
| 317 | */ |
| 318 | if (ctrl & (NAND_ALE | NAND_CLE)) { |
| 319 | if (data != NAND_CMD_NONE) |
| 320 | nand_info->cmd_buf[nand_info->cmd_queue_len++] = data; |
| 321 | return; |
| 322 | } |
| 323 | |
| 324 | /* |
| 325 | * If control arrives here, MTD has deasserted both the ALE and CLE, |
| 326 | * which means it's ready to run an operation. Check if we have any |
| 327 | * bytes to send. |
| 328 | */ |
| 329 | if (nand_info->cmd_queue_len == 0) |
| 330 | return; |
| 331 | |
| 332 | /* Compile the DMA descriptor -- a descriptor that sends command. */ |
| 333 | d = mxs_nand_get_dma_desc(nand_info); |
| 334 | d->cmd.data = |
| 335 | MXS_DMA_DESC_COMMAND_DMA_READ | MXS_DMA_DESC_IRQ | |
| 336 | MXS_DMA_DESC_CHAIN | MXS_DMA_DESC_DEC_SEM | |
| 337 | MXS_DMA_DESC_WAIT4END | (3 << MXS_DMA_DESC_PIO_WORDS_OFFSET) | |
| 338 | (nand_info->cmd_queue_len << MXS_DMA_DESC_BYTES_OFFSET); |
| 339 | |
| 340 | d->cmd.address = (dma_addr_t)nand_info->cmd_buf; |
| 341 | |
| 342 | d->cmd.pio_words[0] = |
| 343 | GPMI_CTRL0_COMMAND_MODE_WRITE | |
| 344 | GPMI_CTRL0_WORD_LENGTH | |
| 345 | (nand_info->cur_chip << GPMI_CTRL0_CS_OFFSET) | |
| 346 | GPMI_CTRL0_ADDRESS_NAND_CLE | |
| 347 | GPMI_CTRL0_ADDRESS_INCREMENT | |
| 348 | nand_info->cmd_queue_len; |
| 349 | |
| 350 | mxs_dma_desc_append(channel, d); |
| 351 | |
Marek Vasut | 6b9408e | 2012-03-15 18:33:19 +0000 | [diff] [blame] | 352 | /* Flush caches */ |
| 353 | mxs_nand_flush_cmd_buf(nand_info); |
| 354 | |
Marek Vasut | 0d4e850 | 2011-11-08 23:18:16 +0000 | [diff] [blame] | 355 | /* Execute the DMA chain. */ |
| 356 | ret = mxs_dma_go(channel); |
| 357 | if (ret) |
| 358 | printf("MXS NAND: Error sending command\n"); |
| 359 | |
| 360 | mxs_nand_return_dma_descs(nand_info); |
| 361 | |
| 362 | /* Reset the command queue. */ |
| 363 | nand_info->cmd_queue_len = 0; |
| 364 | } |
| 365 | |
| 366 | /* |
| 367 | * Test if the NAND flash is ready. |
| 368 | */ |
| 369 | static int mxs_nand_device_ready(struct mtd_info *mtd) |
| 370 | { |
Scott Wood | 17cb4b8 | 2016-05-30 13:57:56 -0500 | [diff] [blame] | 371 | struct nand_chip *chip = mtd_to_nand(mtd); |
| 372 | struct mxs_nand_info *nand_info = nand_get_controller_data(chip); |
Otavio Salvador | 9c47114 | 2012-08-05 09:05:31 +0000 | [diff] [blame] | 373 | struct mxs_gpmi_regs *gpmi_regs = |
| 374 | (struct mxs_gpmi_regs *)MXS_GPMI_BASE; |
Marek Vasut | 0d4e850 | 2011-11-08 23:18:16 +0000 | [diff] [blame] | 375 | uint32_t tmp; |
| 376 | |
| 377 | tmp = readl(&gpmi_regs->hw_gpmi_stat); |
| 378 | tmp >>= (GPMI_STAT_READY_BUSY_OFFSET + nand_info->cur_chip); |
| 379 | |
| 380 | return tmp & 1; |
| 381 | } |
| 382 | |
| 383 | /* |
| 384 | * Select the NAND chip. |
| 385 | */ |
| 386 | static void mxs_nand_select_chip(struct mtd_info *mtd, int chip) |
| 387 | { |
Scott Wood | 17cb4b8 | 2016-05-30 13:57:56 -0500 | [diff] [blame] | 388 | struct nand_chip *nand = mtd_to_nand(mtd); |
| 389 | struct mxs_nand_info *nand_info = nand_get_controller_data(nand); |
Marek Vasut | 0d4e850 | 2011-11-08 23:18:16 +0000 | [diff] [blame] | 390 | |
| 391 | nand_info->cur_chip = chip; |
| 392 | } |
| 393 | |
| 394 | /* |
| 395 | * Handle block mark swapping. |
| 396 | * |
| 397 | * Note that, when this function is called, it doesn't know whether it's |
| 398 | * swapping the block mark, or swapping it *back* -- but it doesn't matter |
| 399 | * because the the operation is the same. |
| 400 | */ |
Stefan Agner | 28897e8 | 2018-06-22 17:19:49 +0200 | [diff] [blame^] | 401 | static void mxs_nand_swap_block_mark(struct bch_geometry *geo, |
| 402 | uint8_t *data_buf, uint8_t *oob_buf) |
Marek Vasut | 0d4e850 | 2011-11-08 23:18:16 +0000 | [diff] [blame] | 403 | { |
Stefan Agner | 28897e8 | 2018-06-22 17:19:49 +0200 | [diff] [blame^] | 404 | uint32_t bit_offset = geo->block_mark_bit_offset; |
| 405 | uint32_t buf_offset = geo->block_mark_byte_offset; |
Marek Vasut | 0d4e850 | 2011-11-08 23:18:16 +0000 | [diff] [blame] | 406 | |
| 407 | uint32_t src; |
| 408 | uint32_t dst; |
| 409 | |
Marek Vasut | 0d4e850 | 2011-11-08 23:18:16 +0000 | [diff] [blame] | 410 | /* |
| 411 | * Get the byte from the data area that overlays the block mark. Since |
| 412 | * the ECC engine applies its own view to the bits in the page, the |
| 413 | * physical block mark won't (in general) appear on a byte boundary in |
| 414 | * the data. |
| 415 | */ |
| 416 | src = data_buf[buf_offset] >> bit_offset; |
| 417 | src |= data_buf[buf_offset + 1] << (8 - bit_offset); |
| 418 | |
| 419 | dst = oob_buf[0]; |
| 420 | |
| 421 | oob_buf[0] = src; |
| 422 | |
| 423 | data_buf[buf_offset] &= ~(0xff << bit_offset); |
| 424 | data_buf[buf_offset + 1] &= 0xff << bit_offset; |
| 425 | |
| 426 | data_buf[buf_offset] |= dst << bit_offset; |
| 427 | data_buf[buf_offset + 1] |= dst >> (8 - bit_offset); |
| 428 | } |
| 429 | |
| 430 | /* |
| 431 | * Read data from NAND. |
| 432 | */ |
| 433 | static void mxs_nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int length) |
| 434 | { |
Scott Wood | 17cb4b8 | 2016-05-30 13:57:56 -0500 | [diff] [blame] | 435 | struct nand_chip *nand = mtd_to_nand(mtd); |
| 436 | struct mxs_nand_info *nand_info = nand_get_controller_data(nand); |
Marek Vasut | 0d4e850 | 2011-11-08 23:18:16 +0000 | [diff] [blame] | 437 | struct mxs_dma_desc *d; |
| 438 | uint32_t channel = MXS_DMA_CHANNEL_AHB_APBH_GPMI0 + nand_info->cur_chip; |
| 439 | int ret; |
| 440 | |
| 441 | if (length > NAND_MAX_PAGESIZE) { |
| 442 | printf("MXS NAND: DMA buffer too big\n"); |
| 443 | return; |
| 444 | } |
| 445 | |
| 446 | if (!buf) { |
| 447 | printf("MXS NAND: DMA buffer is NULL\n"); |
| 448 | return; |
| 449 | } |
| 450 | |
| 451 | /* Compile the DMA descriptor - a descriptor that reads data. */ |
| 452 | d = mxs_nand_get_dma_desc(nand_info); |
| 453 | d->cmd.data = |
| 454 | MXS_DMA_DESC_COMMAND_DMA_WRITE | MXS_DMA_DESC_IRQ | |
| 455 | MXS_DMA_DESC_DEC_SEM | MXS_DMA_DESC_WAIT4END | |
| 456 | (1 << MXS_DMA_DESC_PIO_WORDS_OFFSET) | |
| 457 | (length << MXS_DMA_DESC_BYTES_OFFSET); |
| 458 | |
| 459 | d->cmd.address = (dma_addr_t)nand_info->data_buf; |
| 460 | |
| 461 | d->cmd.pio_words[0] = |
| 462 | GPMI_CTRL0_COMMAND_MODE_READ | |
| 463 | GPMI_CTRL0_WORD_LENGTH | |
| 464 | (nand_info->cur_chip << GPMI_CTRL0_CS_OFFSET) | |
| 465 | GPMI_CTRL0_ADDRESS_NAND_DATA | |
| 466 | length; |
| 467 | |
| 468 | mxs_dma_desc_append(channel, d); |
| 469 | |
| 470 | /* |
| 471 | * A DMA descriptor that waits for the command to end and the chip to |
| 472 | * become ready. |
| 473 | * |
| 474 | * I think we actually should *not* be waiting for the chip to become |
| 475 | * ready because, after all, we don't care. I think the original code |
| 476 | * did that and no one has re-thought it yet. |
| 477 | */ |
| 478 | d = mxs_nand_get_dma_desc(nand_info); |
| 479 | d->cmd.data = |
| 480 | MXS_DMA_DESC_COMMAND_NO_DMAXFER | MXS_DMA_DESC_IRQ | |
| 481 | MXS_DMA_DESC_NAND_WAIT_4_READY | MXS_DMA_DESC_DEC_SEM | |
Luca Ellero | 5263a02 | 2014-12-16 15:36:14 +0100 | [diff] [blame] | 482 | MXS_DMA_DESC_WAIT4END | (1 << MXS_DMA_DESC_PIO_WORDS_OFFSET); |
Marek Vasut | 0d4e850 | 2011-11-08 23:18:16 +0000 | [diff] [blame] | 483 | |
| 484 | d->cmd.address = 0; |
| 485 | |
| 486 | d->cmd.pio_words[0] = |
| 487 | GPMI_CTRL0_COMMAND_MODE_WAIT_FOR_READY | |
| 488 | GPMI_CTRL0_WORD_LENGTH | |
| 489 | (nand_info->cur_chip << GPMI_CTRL0_CS_OFFSET) | |
| 490 | GPMI_CTRL0_ADDRESS_NAND_DATA; |
| 491 | |
| 492 | mxs_dma_desc_append(channel, d); |
| 493 | |
Peng Fan | ecfb876 | 2015-07-21 16:15:21 +0800 | [diff] [blame] | 494 | /* Invalidate caches */ |
| 495 | mxs_nand_inval_data_buf(nand_info); |
| 496 | |
Marek Vasut | 0d4e850 | 2011-11-08 23:18:16 +0000 | [diff] [blame] | 497 | /* Execute the DMA chain. */ |
| 498 | ret = mxs_dma_go(channel); |
| 499 | if (ret) { |
| 500 | printf("MXS NAND: DMA read error\n"); |
| 501 | goto rtn; |
| 502 | } |
| 503 | |
Marek Vasut | 6b9408e | 2012-03-15 18:33:19 +0000 | [diff] [blame] | 504 | /* Invalidate caches */ |
| 505 | mxs_nand_inval_data_buf(nand_info); |
| 506 | |
Marek Vasut | 0d4e850 | 2011-11-08 23:18:16 +0000 | [diff] [blame] | 507 | memcpy(buf, nand_info->data_buf, length); |
| 508 | |
| 509 | rtn: |
| 510 | mxs_nand_return_dma_descs(nand_info); |
| 511 | } |
| 512 | |
| 513 | /* |
| 514 | * Write data to NAND. |
| 515 | */ |
| 516 | static void mxs_nand_write_buf(struct mtd_info *mtd, const uint8_t *buf, |
| 517 | int length) |
| 518 | { |
Scott Wood | 17cb4b8 | 2016-05-30 13:57:56 -0500 | [diff] [blame] | 519 | struct nand_chip *nand = mtd_to_nand(mtd); |
| 520 | struct mxs_nand_info *nand_info = nand_get_controller_data(nand); |
Marek Vasut | 0d4e850 | 2011-11-08 23:18:16 +0000 | [diff] [blame] | 521 | struct mxs_dma_desc *d; |
| 522 | uint32_t channel = MXS_DMA_CHANNEL_AHB_APBH_GPMI0 + nand_info->cur_chip; |
| 523 | int ret; |
| 524 | |
| 525 | if (length > NAND_MAX_PAGESIZE) { |
| 526 | printf("MXS NAND: DMA buffer too big\n"); |
| 527 | return; |
| 528 | } |
| 529 | |
| 530 | if (!buf) { |
| 531 | printf("MXS NAND: DMA buffer is NULL\n"); |
| 532 | return; |
| 533 | } |
| 534 | |
| 535 | memcpy(nand_info->data_buf, buf, length); |
| 536 | |
| 537 | /* Compile the DMA descriptor - a descriptor that writes data. */ |
| 538 | d = mxs_nand_get_dma_desc(nand_info); |
| 539 | d->cmd.data = |
| 540 | MXS_DMA_DESC_COMMAND_DMA_READ | MXS_DMA_DESC_IRQ | |
| 541 | MXS_DMA_DESC_DEC_SEM | MXS_DMA_DESC_WAIT4END | |
Luca Ellero | 88a2cbb | 2014-12-16 15:36:15 +0100 | [diff] [blame] | 542 | (1 << MXS_DMA_DESC_PIO_WORDS_OFFSET) | |
Marek Vasut | 0d4e850 | 2011-11-08 23:18:16 +0000 | [diff] [blame] | 543 | (length << MXS_DMA_DESC_BYTES_OFFSET); |
| 544 | |
| 545 | d->cmd.address = (dma_addr_t)nand_info->data_buf; |
| 546 | |
| 547 | d->cmd.pio_words[0] = |
| 548 | GPMI_CTRL0_COMMAND_MODE_WRITE | |
| 549 | GPMI_CTRL0_WORD_LENGTH | |
| 550 | (nand_info->cur_chip << GPMI_CTRL0_CS_OFFSET) | |
| 551 | GPMI_CTRL0_ADDRESS_NAND_DATA | |
| 552 | length; |
| 553 | |
| 554 | mxs_dma_desc_append(channel, d); |
| 555 | |
Marek Vasut | 6b9408e | 2012-03-15 18:33:19 +0000 | [diff] [blame] | 556 | /* Flush caches */ |
| 557 | mxs_nand_flush_data_buf(nand_info); |
| 558 | |
Marek Vasut | 0d4e850 | 2011-11-08 23:18:16 +0000 | [diff] [blame] | 559 | /* Execute the DMA chain. */ |
| 560 | ret = mxs_dma_go(channel); |
| 561 | if (ret) |
| 562 | printf("MXS NAND: DMA write error\n"); |
| 563 | |
| 564 | mxs_nand_return_dma_descs(nand_info); |
| 565 | } |
| 566 | |
| 567 | /* |
| 568 | * Read a single byte from NAND. |
| 569 | */ |
| 570 | static uint8_t mxs_nand_read_byte(struct mtd_info *mtd) |
| 571 | { |
| 572 | uint8_t buf; |
| 573 | mxs_nand_read_buf(mtd, &buf, 1); |
| 574 | return buf; |
| 575 | } |
| 576 | |
| 577 | /* |
| 578 | * Read a page from NAND. |
| 579 | */ |
| 580 | static int mxs_nand_ecc_read_page(struct mtd_info *mtd, struct nand_chip *nand, |
Sergey Lapin | dfe64e2 | 2013-01-14 03:46:50 +0000 | [diff] [blame] | 581 | uint8_t *buf, int oob_required, |
| 582 | int page) |
Marek Vasut | 0d4e850 | 2011-11-08 23:18:16 +0000 | [diff] [blame] | 583 | { |
Scott Wood | 17cb4b8 | 2016-05-30 13:57:56 -0500 | [diff] [blame] | 584 | struct mxs_nand_info *nand_info = nand_get_controller_data(nand); |
Stefan Agner | 28897e8 | 2018-06-22 17:19:49 +0200 | [diff] [blame^] | 585 | struct bch_geometry *geo = &nand_info->bch_geometry; |
Marek Vasut | 0d4e850 | 2011-11-08 23:18:16 +0000 | [diff] [blame] | 586 | struct mxs_dma_desc *d; |
| 587 | uint32_t channel = MXS_DMA_CHANNEL_AHB_APBH_GPMI0 + nand_info->cur_chip; |
| 588 | uint32_t corrected = 0, failed = 0; |
| 589 | uint8_t *status; |
| 590 | int i, ret; |
| 591 | |
| 592 | /* Compile the DMA descriptor - wait for ready. */ |
| 593 | d = mxs_nand_get_dma_desc(nand_info); |
| 594 | d->cmd.data = |
| 595 | MXS_DMA_DESC_COMMAND_NO_DMAXFER | MXS_DMA_DESC_CHAIN | |
| 596 | MXS_DMA_DESC_NAND_WAIT_4_READY | MXS_DMA_DESC_WAIT4END | |
| 597 | (1 << MXS_DMA_DESC_PIO_WORDS_OFFSET); |
| 598 | |
| 599 | d->cmd.address = 0; |
| 600 | |
| 601 | d->cmd.pio_words[0] = |
| 602 | GPMI_CTRL0_COMMAND_MODE_WAIT_FOR_READY | |
| 603 | GPMI_CTRL0_WORD_LENGTH | |
| 604 | (nand_info->cur_chip << GPMI_CTRL0_CS_OFFSET) | |
| 605 | GPMI_CTRL0_ADDRESS_NAND_DATA; |
| 606 | |
| 607 | mxs_dma_desc_append(channel, d); |
| 608 | |
| 609 | /* Compile the DMA descriptor - enable the BCH block and read. */ |
| 610 | d = mxs_nand_get_dma_desc(nand_info); |
| 611 | d->cmd.data = |
| 612 | MXS_DMA_DESC_COMMAND_NO_DMAXFER | MXS_DMA_DESC_CHAIN | |
| 613 | MXS_DMA_DESC_WAIT4END | (6 << MXS_DMA_DESC_PIO_WORDS_OFFSET); |
| 614 | |
| 615 | d->cmd.address = 0; |
| 616 | |
| 617 | d->cmd.pio_words[0] = |
| 618 | GPMI_CTRL0_COMMAND_MODE_READ | |
| 619 | GPMI_CTRL0_WORD_LENGTH | |
| 620 | (nand_info->cur_chip << GPMI_CTRL0_CS_OFFSET) | |
| 621 | GPMI_CTRL0_ADDRESS_NAND_DATA | |
| 622 | (mtd->writesize + mtd->oobsize); |
| 623 | d->cmd.pio_words[1] = 0; |
| 624 | d->cmd.pio_words[2] = |
| 625 | GPMI_ECCCTRL_ENABLE_ECC | |
| 626 | GPMI_ECCCTRL_ECC_CMD_DECODE | |
| 627 | GPMI_ECCCTRL_BUFFER_MASK_BCH_PAGE; |
| 628 | d->cmd.pio_words[3] = mtd->writesize + mtd->oobsize; |
| 629 | d->cmd.pio_words[4] = (dma_addr_t)nand_info->data_buf; |
| 630 | d->cmd.pio_words[5] = (dma_addr_t)nand_info->oob_buf; |
| 631 | |
| 632 | mxs_dma_desc_append(channel, d); |
| 633 | |
| 634 | /* Compile the DMA descriptor - disable the BCH block. */ |
| 635 | d = mxs_nand_get_dma_desc(nand_info); |
| 636 | d->cmd.data = |
| 637 | MXS_DMA_DESC_COMMAND_NO_DMAXFER | MXS_DMA_DESC_CHAIN | |
| 638 | MXS_DMA_DESC_NAND_WAIT_4_READY | MXS_DMA_DESC_WAIT4END | |
| 639 | (3 << MXS_DMA_DESC_PIO_WORDS_OFFSET); |
| 640 | |
| 641 | d->cmd.address = 0; |
| 642 | |
| 643 | d->cmd.pio_words[0] = |
| 644 | GPMI_CTRL0_COMMAND_MODE_WAIT_FOR_READY | |
| 645 | GPMI_CTRL0_WORD_LENGTH | |
| 646 | (nand_info->cur_chip << GPMI_CTRL0_CS_OFFSET) | |
| 647 | GPMI_CTRL0_ADDRESS_NAND_DATA | |
| 648 | (mtd->writesize + mtd->oobsize); |
| 649 | d->cmd.pio_words[1] = 0; |
| 650 | d->cmd.pio_words[2] = 0; |
| 651 | |
| 652 | mxs_dma_desc_append(channel, d); |
| 653 | |
| 654 | /* Compile the DMA descriptor - deassert the NAND lock and interrupt. */ |
| 655 | d = mxs_nand_get_dma_desc(nand_info); |
| 656 | d->cmd.data = |
| 657 | MXS_DMA_DESC_COMMAND_NO_DMAXFER | MXS_DMA_DESC_IRQ | |
| 658 | MXS_DMA_DESC_DEC_SEM; |
| 659 | |
| 660 | d->cmd.address = 0; |
| 661 | |
| 662 | mxs_dma_desc_append(channel, d); |
| 663 | |
Peng Fan | ecfb876 | 2015-07-21 16:15:21 +0800 | [diff] [blame] | 664 | /* Invalidate caches */ |
| 665 | mxs_nand_inval_data_buf(nand_info); |
| 666 | |
Marek Vasut | 0d4e850 | 2011-11-08 23:18:16 +0000 | [diff] [blame] | 667 | /* Execute the DMA chain. */ |
| 668 | ret = mxs_dma_go(channel); |
| 669 | if (ret) { |
| 670 | printf("MXS NAND: DMA read error\n"); |
| 671 | goto rtn; |
| 672 | } |
| 673 | |
| 674 | ret = mxs_nand_wait_for_bch_complete(); |
| 675 | if (ret) { |
| 676 | printf("MXS NAND: BCH read timeout\n"); |
| 677 | goto rtn; |
| 678 | } |
| 679 | |
Marek Vasut | 6b9408e | 2012-03-15 18:33:19 +0000 | [diff] [blame] | 680 | /* Invalidate caches */ |
| 681 | mxs_nand_inval_data_buf(nand_info); |
| 682 | |
Marek Vasut | 0d4e850 | 2011-11-08 23:18:16 +0000 | [diff] [blame] | 683 | /* Read DMA completed, now do the mark swapping. */ |
Stefan Agner | 28897e8 | 2018-06-22 17:19:49 +0200 | [diff] [blame^] | 684 | mxs_nand_swap_block_mark(geo, nand_info->data_buf, nand_info->oob_buf); |
Marek Vasut | 0d4e850 | 2011-11-08 23:18:16 +0000 | [diff] [blame] | 685 | |
| 686 | /* Loop over status bytes, accumulating ECC status. */ |
| 687 | status = nand_info->oob_buf + mxs_nand_aux_status_offset(); |
Stefan Agner | 28897e8 | 2018-06-22 17:19:49 +0200 | [diff] [blame^] | 688 | for (i = 0; i < geo->ecc_chunk_count; i++) { |
Marek Vasut | 0d4e850 | 2011-11-08 23:18:16 +0000 | [diff] [blame] | 689 | if (status[i] == 0x00) |
| 690 | continue; |
| 691 | |
| 692 | if (status[i] == 0xff) |
| 693 | continue; |
| 694 | |
| 695 | if (status[i] == 0xfe) { |
| 696 | failed++; |
| 697 | continue; |
| 698 | } |
| 699 | |
| 700 | corrected += status[i]; |
| 701 | } |
| 702 | |
| 703 | /* Propagate ECC status to the owning MTD. */ |
| 704 | mtd->ecc_stats.failed += failed; |
| 705 | mtd->ecc_stats.corrected += corrected; |
| 706 | |
| 707 | /* |
| 708 | * It's time to deliver the OOB bytes. See mxs_nand_ecc_read_oob() for |
| 709 | * details about our policy for delivering the OOB. |
| 710 | * |
| 711 | * We fill the caller's buffer with set bits, and then copy the block |
| 712 | * mark to the caller's buffer. Note that, if block mark swapping was |
| 713 | * necessary, it has already been done, so we can rely on the first |
| 714 | * byte of the auxiliary buffer to contain the block mark. |
| 715 | */ |
| 716 | memset(nand->oob_poi, 0xff, mtd->oobsize); |
| 717 | |
| 718 | nand->oob_poi[0] = nand_info->oob_buf[0]; |
| 719 | |
| 720 | memcpy(buf, nand_info->data_buf, mtd->writesize); |
| 721 | |
| 722 | rtn: |
| 723 | mxs_nand_return_dma_descs(nand_info); |
| 724 | |
| 725 | return ret; |
| 726 | } |
| 727 | |
| 728 | /* |
| 729 | * Write a page to NAND. |
| 730 | */ |
Sergey Lapin | dfe64e2 | 2013-01-14 03:46:50 +0000 | [diff] [blame] | 731 | static int mxs_nand_ecc_write_page(struct mtd_info *mtd, |
| 732 | struct nand_chip *nand, const uint8_t *buf, |
Scott Wood | 81c7725 | 2016-05-30 13:57:57 -0500 | [diff] [blame] | 733 | int oob_required, int page) |
Marek Vasut | 0d4e850 | 2011-11-08 23:18:16 +0000 | [diff] [blame] | 734 | { |
Scott Wood | 17cb4b8 | 2016-05-30 13:57:56 -0500 | [diff] [blame] | 735 | struct mxs_nand_info *nand_info = nand_get_controller_data(nand); |
Stefan Agner | 28897e8 | 2018-06-22 17:19:49 +0200 | [diff] [blame^] | 736 | struct bch_geometry *geo = &nand_info->bch_geometry; |
Marek Vasut | 0d4e850 | 2011-11-08 23:18:16 +0000 | [diff] [blame] | 737 | struct mxs_dma_desc *d; |
| 738 | uint32_t channel = MXS_DMA_CHANNEL_AHB_APBH_GPMI0 + nand_info->cur_chip; |
| 739 | int ret; |
| 740 | |
| 741 | memcpy(nand_info->data_buf, buf, mtd->writesize); |
| 742 | memcpy(nand_info->oob_buf, nand->oob_poi, mtd->oobsize); |
| 743 | |
| 744 | /* Handle block mark swapping. */ |
Stefan Agner | 28897e8 | 2018-06-22 17:19:49 +0200 | [diff] [blame^] | 745 | mxs_nand_swap_block_mark(geo, nand_info->data_buf, nand_info->oob_buf); |
Marek Vasut | 0d4e850 | 2011-11-08 23:18:16 +0000 | [diff] [blame] | 746 | |
| 747 | /* Compile the DMA descriptor - write data. */ |
| 748 | d = mxs_nand_get_dma_desc(nand_info); |
| 749 | d->cmd.data = |
| 750 | MXS_DMA_DESC_COMMAND_NO_DMAXFER | MXS_DMA_DESC_IRQ | |
| 751 | MXS_DMA_DESC_DEC_SEM | MXS_DMA_DESC_WAIT4END | |
| 752 | (6 << MXS_DMA_DESC_PIO_WORDS_OFFSET); |
| 753 | |
| 754 | d->cmd.address = 0; |
| 755 | |
| 756 | d->cmd.pio_words[0] = |
| 757 | GPMI_CTRL0_COMMAND_MODE_WRITE | |
| 758 | GPMI_CTRL0_WORD_LENGTH | |
| 759 | (nand_info->cur_chip << GPMI_CTRL0_CS_OFFSET) | |
| 760 | GPMI_CTRL0_ADDRESS_NAND_DATA; |
| 761 | d->cmd.pio_words[1] = 0; |
| 762 | d->cmd.pio_words[2] = |
| 763 | GPMI_ECCCTRL_ENABLE_ECC | |
| 764 | GPMI_ECCCTRL_ECC_CMD_ENCODE | |
| 765 | GPMI_ECCCTRL_BUFFER_MASK_BCH_PAGE; |
| 766 | d->cmd.pio_words[3] = (mtd->writesize + mtd->oobsize); |
| 767 | d->cmd.pio_words[4] = (dma_addr_t)nand_info->data_buf; |
| 768 | d->cmd.pio_words[5] = (dma_addr_t)nand_info->oob_buf; |
| 769 | |
| 770 | mxs_dma_desc_append(channel, d); |
| 771 | |
Marek Vasut | 6b9408e | 2012-03-15 18:33:19 +0000 | [diff] [blame] | 772 | /* Flush caches */ |
| 773 | mxs_nand_flush_data_buf(nand_info); |
| 774 | |
Marek Vasut | 0d4e850 | 2011-11-08 23:18:16 +0000 | [diff] [blame] | 775 | /* Execute the DMA chain. */ |
| 776 | ret = mxs_dma_go(channel); |
| 777 | if (ret) { |
| 778 | printf("MXS NAND: DMA write error\n"); |
| 779 | goto rtn; |
| 780 | } |
| 781 | |
| 782 | ret = mxs_nand_wait_for_bch_complete(); |
| 783 | if (ret) { |
| 784 | printf("MXS NAND: BCH write timeout\n"); |
| 785 | goto rtn; |
| 786 | } |
| 787 | |
| 788 | rtn: |
| 789 | mxs_nand_return_dma_descs(nand_info); |
Sergey Lapin | dfe64e2 | 2013-01-14 03:46:50 +0000 | [diff] [blame] | 790 | return 0; |
Marek Vasut | 0d4e850 | 2011-11-08 23:18:16 +0000 | [diff] [blame] | 791 | } |
| 792 | |
| 793 | /* |
| 794 | * Read OOB from NAND. |
| 795 | * |
| 796 | * This function is a veneer that replaces the function originally installed by |
| 797 | * the NAND Flash MTD code. |
| 798 | */ |
| 799 | static int mxs_nand_hook_read_oob(struct mtd_info *mtd, loff_t from, |
| 800 | struct mtd_oob_ops *ops) |
| 801 | { |
Scott Wood | 17cb4b8 | 2016-05-30 13:57:56 -0500 | [diff] [blame] | 802 | struct nand_chip *chip = mtd_to_nand(mtd); |
| 803 | struct mxs_nand_info *nand_info = nand_get_controller_data(chip); |
Marek Vasut | 0d4e850 | 2011-11-08 23:18:16 +0000 | [diff] [blame] | 804 | int ret; |
| 805 | |
Sergey Lapin | dfe64e2 | 2013-01-14 03:46:50 +0000 | [diff] [blame] | 806 | if (ops->mode == MTD_OPS_RAW) |
Marek Vasut | 0d4e850 | 2011-11-08 23:18:16 +0000 | [diff] [blame] | 807 | nand_info->raw_oob_mode = 1; |
| 808 | else |
| 809 | nand_info->raw_oob_mode = 0; |
| 810 | |
| 811 | ret = nand_info->hooked_read_oob(mtd, from, ops); |
| 812 | |
| 813 | nand_info->raw_oob_mode = 0; |
| 814 | |
| 815 | return ret; |
| 816 | } |
| 817 | |
| 818 | /* |
| 819 | * Write OOB to NAND. |
| 820 | * |
| 821 | * This function is a veneer that replaces the function originally installed by |
| 822 | * the NAND Flash MTD code. |
| 823 | */ |
| 824 | static int mxs_nand_hook_write_oob(struct mtd_info *mtd, loff_t to, |
| 825 | struct mtd_oob_ops *ops) |
| 826 | { |
Scott Wood | 17cb4b8 | 2016-05-30 13:57:56 -0500 | [diff] [blame] | 827 | struct nand_chip *chip = mtd_to_nand(mtd); |
| 828 | struct mxs_nand_info *nand_info = nand_get_controller_data(chip); |
Marek Vasut | 0d4e850 | 2011-11-08 23:18:16 +0000 | [diff] [blame] | 829 | int ret; |
| 830 | |
Sergey Lapin | dfe64e2 | 2013-01-14 03:46:50 +0000 | [diff] [blame] | 831 | if (ops->mode == MTD_OPS_RAW) |
Marek Vasut | 0d4e850 | 2011-11-08 23:18:16 +0000 | [diff] [blame] | 832 | nand_info->raw_oob_mode = 1; |
| 833 | else |
| 834 | nand_info->raw_oob_mode = 0; |
| 835 | |
| 836 | ret = nand_info->hooked_write_oob(mtd, to, ops); |
| 837 | |
| 838 | nand_info->raw_oob_mode = 0; |
| 839 | |
| 840 | return ret; |
| 841 | } |
| 842 | |
| 843 | /* |
| 844 | * Mark a block bad in NAND. |
| 845 | * |
| 846 | * This function is a veneer that replaces the function originally installed by |
| 847 | * the NAND Flash MTD code. |
| 848 | */ |
| 849 | static int mxs_nand_hook_block_markbad(struct mtd_info *mtd, loff_t ofs) |
| 850 | { |
Scott Wood | 17cb4b8 | 2016-05-30 13:57:56 -0500 | [diff] [blame] | 851 | struct nand_chip *chip = mtd_to_nand(mtd); |
| 852 | struct mxs_nand_info *nand_info = nand_get_controller_data(chip); |
Marek Vasut | 0d4e850 | 2011-11-08 23:18:16 +0000 | [diff] [blame] | 853 | int ret; |
| 854 | |
| 855 | nand_info->marking_block_bad = 1; |
| 856 | |
| 857 | ret = nand_info->hooked_block_markbad(mtd, ofs); |
| 858 | |
| 859 | nand_info->marking_block_bad = 0; |
| 860 | |
| 861 | return ret; |
| 862 | } |
| 863 | |
| 864 | /* |
| 865 | * There are several places in this driver where we have to handle the OOB and |
| 866 | * block marks. This is the function where things are the most complicated, so |
| 867 | * this is where we try to explain it all. All the other places refer back to |
| 868 | * here. |
| 869 | * |
| 870 | * These are the rules, in order of decreasing importance: |
| 871 | * |
| 872 | * 1) Nothing the caller does can be allowed to imperil the block mark, so all |
| 873 | * write operations take measures to protect it. |
| 874 | * |
| 875 | * 2) In read operations, the first byte of the OOB we return must reflect the |
| 876 | * true state of the block mark, no matter where that block mark appears in |
| 877 | * the physical page. |
| 878 | * |
| 879 | * 3) ECC-based read operations return an OOB full of set bits (since we never |
| 880 | * allow ECC-based writes to the OOB, it doesn't matter what ECC-based reads |
| 881 | * return). |
| 882 | * |
| 883 | * 4) "Raw" read operations return a direct view of the physical bytes in the |
| 884 | * page, using the conventional definition of which bytes are data and which |
| 885 | * are OOB. This gives the caller a way to see the actual, physical bytes |
| 886 | * in the page, without the distortions applied by our ECC engine. |
| 887 | * |
| 888 | * What we do for this specific read operation depends on whether we're doing |
| 889 | * "raw" read, or an ECC-based read. |
| 890 | * |
| 891 | * It turns out that knowing whether we want an "ECC-based" or "raw" read is not |
| 892 | * easy. When reading a page, for example, the NAND Flash MTD code calls our |
| 893 | * ecc.read_page or ecc.read_page_raw function. Thus, the fact that MTD wants an |
| 894 | * ECC-based or raw view of the page is implicit in which function it calls |
| 895 | * (there is a similar pair of ECC-based/raw functions for writing). |
| 896 | * |
| 897 | * Since MTD assumes the OOB is not covered by ECC, there is no pair of |
| 898 | * ECC-based/raw functions for reading or or writing the OOB. The fact that the |
| 899 | * caller wants an ECC-based or raw view of the page is not propagated down to |
| 900 | * this driver. |
| 901 | * |
| 902 | * Since our OOB *is* covered by ECC, we need this information. So, we hook the |
| 903 | * ecc.read_oob and ecc.write_oob function pointers in the owning |
| 904 | * struct mtd_info with our own functions. These hook functions set the |
| 905 | * raw_oob_mode field so that, when control finally arrives here, we'll know |
| 906 | * what to do. |
| 907 | */ |
| 908 | static int mxs_nand_ecc_read_oob(struct mtd_info *mtd, struct nand_chip *nand, |
Sergey Lapin | dfe64e2 | 2013-01-14 03:46:50 +0000 | [diff] [blame] | 909 | int page) |
Marek Vasut | 0d4e850 | 2011-11-08 23:18:16 +0000 | [diff] [blame] | 910 | { |
Scott Wood | 17cb4b8 | 2016-05-30 13:57:56 -0500 | [diff] [blame] | 911 | struct mxs_nand_info *nand_info = nand_get_controller_data(nand); |
Marek Vasut | 0d4e850 | 2011-11-08 23:18:16 +0000 | [diff] [blame] | 912 | |
| 913 | /* |
| 914 | * First, fill in the OOB buffer. If we're doing a raw read, we need to |
| 915 | * get the bytes from the physical page. If we're not doing a raw read, |
| 916 | * we need to fill the buffer with set bits. |
| 917 | */ |
| 918 | if (nand_info->raw_oob_mode) { |
| 919 | /* |
| 920 | * If control arrives here, we're doing a "raw" read. Send the |
| 921 | * command to read the conventional OOB and read it. |
| 922 | */ |
| 923 | nand->cmdfunc(mtd, NAND_CMD_READ0, mtd->writesize, page); |
| 924 | nand->read_buf(mtd, nand->oob_poi, mtd->oobsize); |
| 925 | } else { |
| 926 | /* |
| 927 | * If control arrives here, we're not doing a "raw" read. Fill |
| 928 | * the OOB buffer with set bits and correct the block mark. |
| 929 | */ |
| 930 | memset(nand->oob_poi, 0xff, mtd->oobsize); |
| 931 | |
| 932 | nand->cmdfunc(mtd, NAND_CMD_READ0, mtd->writesize, page); |
| 933 | mxs_nand_read_buf(mtd, nand->oob_poi, 1); |
| 934 | } |
| 935 | |
| 936 | return 0; |
| 937 | |
| 938 | } |
| 939 | |
| 940 | /* |
| 941 | * Write OOB data to NAND. |
| 942 | */ |
| 943 | static int mxs_nand_ecc_write_oob(struct mtd_info *mtd, struct nand_chip *nand, |
| 944 | int page) |
| 945 | { |
Scott Wood | 17cb4b8 | 2016-05-30 13:57:56 -0500 | [diff] [blame] | 946 | struct mxs_nand_info *nand_info = nand_get_controller_data(nand); |
Marek Vasut | 0d4e850 | 2011-11-08 23:18:16 +0000 | [diff] [blame] | 947 | uint8_t block_mark = 0; |
| 948 | |
| 949 | /* |
| 950 | * There are fundamental incompatibilities between the i.MX GPMI NFC and |
| 951 | * the NAND Flash MTD model that make it essentially impossible to write |
| 952 | * the out-of-band bytes. |
| 953 | * |
| 954 | * We permit *ONE* exception. If the *intent* of writing the OOB is to |
| 955 | * mark a block bad, we can do that. |
| 956 | */ |
| 957 | |
| 958 | if (!nand_info->marking_block_bad) { |
| 959 | printf("NXS NAND: Writing OOB isn't supported\n"); |
| 960 | return -EIO; |
| 961 | } |
| 962 | |
| 963 | /* Write the block mark. */ |
| 964 | nand->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page); |
| 965 | nand->write_buf(mtd, &block_mark, 1); |
| 966 | nand->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1); |
| 967 | |
| 968 | /* Check if it worked. */ |
| 969 | if (nand->waitfunc(mtd, nand) & NAND_STATUS_FAIL) |
| 970 | return -EIO; |
| 971 | |
| 972 | return 0; |
| 973 | } |
| 974 | |
| 975 | /* |
| 976 | * Claims all blocks are good. |
| 977 | * |
| 978 | * In principle, this function is *only* called when the NAND Flash MTD system |
| 979 | * isn't allowed to keep an in-memory bad block table, so it is forced to ask |
| 980 | * the driver for bad block information. |
| 981 | * |
| 982 | * In fact, we permit the NAND Flash MTD system to have an in-memory BBT, so |
| 983 | * this function is *only* called when we take it away. |
| 984 | * |
| 985 | * Thus, this function is only called when we want *all* blocks to look good, |
| 986 | * so it *always* return success. |
| 987 | */ |
Scott Wood | ceee07b | 2016-05-30 13:57:58 -0500 | [diff] [blame] | 988 | static int mxs_nand_block_bad(struct mtd_info *mtd, loff_t ofs) |
Marek Vasut | 0d4e850 | 2011-11-08 23:18:16 +0000 | [diff] [blame] | 989 | { |
| 990 | return 0; |
| 991 | } |
| 992 | |
| 993 | /* |
Marek Vasut | 0d4e850 | 2011-11-08 23:18:16 +0000 | [diff] [blame] | 994 | * At this point, the physical NAND Flash chips have been identified and |
| 995 | * counted, so we know the physical geometry. This enables us to make some |
| 996 | * important configuration decisions. |
| 997 | * |
Robert P. J. Day | 62a3b7d | 2016-07-15 13:44:45 -0400 | [diff] [blame] | 998 | * The return value of this function propagates directly back to this driver's |
Stefan Agner | 5346c31 | 2018-06-22 17:19:47 +0200 | [diff] [blame] | 999 | * board_nand_init(). Anything other than zero will cause this driver to |
Marek Vasut | 0d4e850 | 2011-11-08 23:18:16 +0000 | [diff] [blame] | 1000 | * tear everything down and declare failure. |
| 1001 | */ |
Stefan Agner | 5346c31 | 2018-06-22 17:19:47 +0200 | [diff] [blame] | 1002 | int mxs_nand_setup_ecc(struct mtd_info *mtd) |
Marek Vasut | 0d4e850 | 2011-11-08 23:18:16 +0000 | [diff] [blame] | 1003 | { |
Scott Wood | 17cb4b8 | 2016-05-30 13:57:56 -0500 | [diff] [blame] | 1004 | struct nand_chip *nand = mtd_to_nand(mtd); |
| 1005 | struct mxs_nand_info *nand_info = nand_get_controller_data(nand); |
Stefan Agner | 28897e8 | 2018-06-22 17:19:49 +0200 | [diff] [blame^] | 1006 | struct bch_geometry *geo = &nand_info->bch_geometry; |
Otavio Salvador | 9c47114 | 2012-08-05 09:05:31 +0000 | [diff] [blame] | 1007 | struct mxs_bch_regs *bch_regs = (struct mxs_bch_regs *)MXS_BCH_BASE; |
Marek Vasut | 0d4e850 | 2011-11-08 23:18:16 +0000 | [diff] [blame] | 1008 | uint32_t tmp; |
| 1009 | |
Stefan Agner | 28897e8 | 2018-06-22 17:19:49 +0200 | [diff] [blame^] | 1010 | if (mxs_nand_calc_ecc_layout(geo, mtd)) |
Peng Fan | 63b29d8 | 2015-07-21 16:15:19 +0800 | [diff] [blame] | 1011 | return -EINVAL; |
Peng Fan | 63b29d8 | 2015-07-21 16:15:19 +0800 | [diff] [blame] | 1012 | |
Marek Vasut | 0d4e850 | 2011-11-08 23:18:16 +0000 | [diff] [blame] | 1013 | /* Configure BCH and set NFC geometry */ |
Otavio Salvador | fa7a51c | 2012-08-13 09:53:12 +0000 | [diff] [blame] | 1014 | mxs_reset_block(&bch_regs->hw_bch_ctrl_reg); |
Marek Vasut | 0d4e850 | 2011-11-08 23:18:16 +0000 | [diff] [blame] | 1015 | |
| 1016 | /* Configure layout 0 */ |
Stefan Agner | 28897e8 | 2018-06-22 17:19:49 +0200 | [diff] [blame^] | 1017 | tmp = (geo->ecc_chunk_count - 1) << BCH_FLASHLAYOUT0_NBLOCKS_OFFSET; |
Marek Vasut | 0d4e850 | 2011-11-08 23:18:16 +0000 | [diff] [blame] | 1018 | tmp |= MXS_NAND_METADATA_SIZE << BCH_FLASHLAYOUT0_META_SIZE_OFFSET; |
Stefan Agner | 28897e8 | 2018-06-22 17:19:49 +0200 | [diff] [blame^] | 1019 | tmp |= (geo->ecc_strength >> 1) << BCH_FLASHLAYOUT0_ECC0_OFFSET; |
| 1020 | tmp |= geo->ecc_chunk_size >> MXS_NAND_CHUNK_DATA_CHUNK_SIZE_SHIFT; |
| 1021 | tmp |= (geo->gf_len == 14 ? 1 : 0) << |
Peng Fan | 63b29d8 | 2015-07-21 16:15:19 +0800 | [diff] [blame] | 1022 | BCH_FLASHLAYOUT0_GF13_0_GF14_1_OFFSET; |
Marek Vasut | 0d4e850 | 2011-11-08 23:18:16 +0000 | [diff] [blame] | 1023 | writel(tmp, &bch_regs->hw_bch_flash0layout0); |
| 1024 | |
| 1025 | tmp = (mtd->writesize + mtd->oobsize) |
| 1026 | << BCH_FLASHLAYOUT1_PAGE_SIZE_OFFSET; |
Stefan Agner | 28897e8 | 2018-06-22 17:19:49 +0200 | [diff] [blame^] | 1027 | tmp |= (geo->ecc_strength >> 1) << BCH_FLASHLAYOUT1_ECCN_OFFSET; |
| 1028 | tmp |= geo->ecc_chunk_size >> MXS_NAND_CHUNK_DATA_CHUNK_SIZE_SHIFT; |
| 1029 | tmp |= (geo->gf_len == 14 ? 1 : 0) << |
Peng Fan | 63b29d8 | 2015-07-21 16:15:19 +0800 | [diff] [blame] | 1030 | BCH_FLASHLAYOUT1_GF13_0_GF14_1_OFFSET; |
Marek Vasut | 0d4e850 | 2011-11-08 23:18:16 +0000 | [diff] [blame] | 1031 | writel(tmp, &bch_regs->hw_bch_flash0layout1); |
| 1032 | |
| 1033 | /* Set *all* chip selects to use layout 0 */ |
| 1034 | writel(0, &bch_regs->hw_bch_layoutselect); |
| 1035 | |
| 1036 | /* Enable BCH complete interrupt */ |
| 1037 | writel(BCH_CTRL_COMPLETE_IRQ_EN, &bch_regs->hw_bch_ctrl_set); |
| 1038 | |
| 1039 | /* Hook some operations at the MTD level. */ |
Sergey Lapin | dfe64e2 | 2013-01-14 03:46:50 +0000 | [diff] [blame] | 1040 | if (mtd->_read_oob != mxs_nand_hook_read_oob) { |
| 1041 | nand_info->hooked_read_oob = mtd->_read_oob; |
| 1042 | mtd->_read_oob = mxs_nand_hook_read_oob; |
Marek Vasut | 0d4e850 | 2011-11-08 23:18:16 +0000 | [diff] [blame] | 1043 | } |
| 1044 | |
Sergey Lapin | dfe64e2 | 2013-01-14 03:46:50 +0000 | [diff] [blame] | 1045 | if (mtd->_write_oob != mxs_nand_hook_write_oob) { |
| 1046 | nand_info->hooked_write_oob = mtd->_write_oob; |
| 1047 | mtd->_write_oob = mxs_nand_hook_write_oob; |
Marek Vasut | 0d4e850 | 2011-11-08 23:18:16 +0000 | [diff] [blame] | 1048 | } |
| 1049 | |
Sergey Lapin | dfe64e2 | 2013-01-14 03:46:50 +0000 | [diff] [blame] | 1050 | if (mtd->_block_markbad != mxs_nand_hook_block_markbad) { |
| 1051 | nand_info->hooked_block_markbad = mtd->_block_markbad; |
| 1052 | mtd->_block_markbad = mxs_nand_hook_block_markbad; |
Marek Vasut | 0d4e850 | 2011-11-08 23:18:16 +0000 | [diff] [blame] | 1053 | } |
| 1054 | |
Stefan Agner | 5346c31 | 2018-06-22 17:19:47 +0200 | [diff] [blame] | 1055 | return 0; |
Marek Vasut | 0d4e850 | 2011-11-08 23:18:16 +0000 | [diff] [blame] | 1056 | } |
| 1057 | |
| 1058 | /* |
| 1059 | * Allocate DMA buffers |
| 1060 | */ |
| 1061 | int mxs_nand_alloc_buffers(struct mxs_nand_info *nand_info) |
| 1062 | { |
| 1063 | uint8_t *buf; |
| 1064 | const int size = NAND_MAX_PAGESIZE + NAND_MAX_OOBSIZE; |
| 1065 | |
Marek Vasut | 6b9408e | 2012-03-15 18:33:19 +0000 | [diff] [blame] | 1066 | nand_info->data_buf_size = roundup(size, MXS_DMA_ALIGNMENT); |
| 1067 | |
Marek Vasut | 0d4e850 | 2011-11-08 23:18:16 +0000 | [diff] [blame] | 1068 | /* DMA buffers */ |
Marek Vasut | 6b9408e | 2012-03-15 18:33:19 +0000 | [diff] [blame] | 1069 | buf = memalign(MXS_DMA_ALIGNMENT, nand_info->data_buf_size); |
Marek Vasut | 0d4e850 | 2011-11-08 23:18:16 +0000 | [diff] [blame] | 1070 | if (!buf) { |
| 1071 | printf("MXS NAND: Error allocating DMA buffers\n"); |
| 1072 | return -ENOMEM; |
| 1073 | } |
| 1074 | |
Marek Vasut | 6b9408e | 2012-03-15 18:33:19 +0000 | [diff] [blame] | 1075 | memset(buf, 0, nand_info->data_buf_size); |
Marek Vasut | 0d4e850 | 2011-11-08 23:18:16 +0000 | [diff] [blame] | 1076 | |
| 1077 | nand_info->data_buf = buf; |
| 1078 | nand_info->oob_buf = buf + NAND_MAX_PAGESIZE; |
Marek Vasut | 0d4e850 | 2011-11-08 23:18:16 +0000 | [diff] [blame] | 1079 | /* Command buffers */ |
| 1080 | nand_info->cmd_buf = memalign(MXS_DMA_ALIGNMENT, |
| 1081 | MXS_NAND_COMMAND_BUFFER_SIZE); |
| 1082 | if (!nand_info->cmd_buf) { |
| 1083 | free(buf); |
| 1084 | printf("MXS NAND: Error allocating command buffers\n"); |
| 1085 | return -ENOMEM; |
| 1086 | } |
| 1087 | memset(nand_info->cmd_buf, 0, MXS_NAND_COMMAND_BUFFER_SIZE); |
| 1088 | nand_info->cmd_queue_len = 0; |
| 1089 | |
| 1090 | return 0; |
| 1091 | } |
| 1092 | |
| 1093 | /* |
| 1094 | * Initializes the NFC hardware. |
| 1095 | */ |
| 1096 | int mxs_nand_init(struct mxs_nand_info *info) |
| 1097 | { |
Otavio Salvador | 9c47114 | 2012-08-05 09:05:31 +0000 | [diff] [blame] | 1098 | struct mxs_gpmi_regs *gpmi_regs = |
| 1099 | (struct mxs_gpmi_regs *)MXS_GPMI_BASE; |
Wolfram Sang | 0b38fff | 2012-12-05 10:48:47 +0000 | [diff] [blame] | 1100 | struct mxs_bch_regs *bch_regs = |
| 1101 | (struct mxs_bch_regs *)MXS_BCH_BASE; |
Peng Fan | 549d7c0 | 2016-01-27 10:38:02 +0800 | [diff] [blame] | 1102 | int i = 0, j, ret = 0; |
Marek Vasut | 0d4e850 | 2011-11-08 23:18:16 +0000 | [diff] [blame] | 1103 | |
| 1104 | info->desc = malloc(sizeof(struct mxs_dma_desc *) * |
| 1105 | MXS_NAND_DMA_DESCRIPTOR_COUNT); |
Peng Fan | 549d7c0 | 2016-01-27 10:38:02 +0800 | [diff] [blame] | 1106 | if (!info->desc) { |
| 1107 | ret = -ENOMEM; |
Marek Vasut | 0d4e850 | 2011-11-08 23:18:16 +0000 | [diff] [blame] | 1108 | goto err1; |
Peng Fan | 549d7c0 | 2016-01-27 10:38:02 +0800 | [diff] [blame] | 1109 | } |
Marek Vasut | 0d4e850 | 2011-11-08 23:18:16 +0000 | [diff] [blame] | 1110 | |
| 1111 | /* Allocate the DMA descriptors. */ |
| 1112 | for (i = 0; i < MXS_NAND_DMA_DESCRIPTOR_COUNT; i++) { |
| 1113 | info->desc[i] = mxs_dma_desc_alloc(); |
Peng Fan | 549d7c0 | 2016-01-27 10:38:02 +0800 | [diff] [blame] | 1114 | if (!info->desc[i]) { |
| 1115 | ret = -ENOMEM; |
Marek Vasut | 0d4e850 | 2011-11-08 23:18:16 +0000 | [diff] [blame] | 1116 | goto err2; |
Peng Fan | 549d7c0 | 2016-01-27 10:38:02 +0800 | [diff] [blame] | 1117 | } |
Marek Vasut | 0d4e850 | 2011-11-08 23:18:16 +0000 | [diff] [blame] | 1118 | } |
| 1119 | |
| 1120 | /* Init the DMA controller. */ |
Fabio Estevam | a1d1fdc | 2017-06-29 09:33:44 -0300 | [diff] [blame] | 1121 | mxs_dma_init(); |
Marek Vasut | 96666a3 | 2012-04-08 17:34:46 +0000 | [diff] [blame] | 1122 | for (j = MXS_DMA_CHANNEL_AHB_APBH_GPMI0; |
| 1123 | j <= MXS_DMA_CHANNEL_AHB_APBH_GPMI7; j++) { |
Peng Fan | 549d7c0 | 2016-01-27 10:38:02 +0800 | [diff] [blame] | 1124 | ret = mxs_dma_init_channel(j); |
| 1125 | if (ret) |
Marek Vasut | 96666a3 | 2012-04-08 17:34:46 +0000 | [diff] [blame] | 1126 | goto err3; |
| 1127 | } |
Marek Vasut | 0d4e850 | 2011-11-08 23:18:16 +0000 | [diff] [blame] | 1128 | |
| 1129 | /* Reset the GPMI block. */ |
Otavio Salvador | fa7a51c | 2012-08-13 09:53:12 +0000 | [diff] [blame] | 1130 | mxs_reset_block(&gpmi_regs->hw_gpmi_ctrl0_reg); |
Wolfram Sang | 0b38fff | 2012-12-05 10:48:47 +0000 | [diff] [blame] | 1131 | mxs_reset_block(&bch_regs->hw_bch_ctrl_reg); |
Marek Vasut | 0d4e850 | 2011-11-08 23:18:16 +0000 | [diff] [blame] | 1132 | |
| 1133 | /* |
| 1134 | * Choose NAND mode, set IRQ polarity, disable write protection and |
| 1135 | * select BCH ECC. |
| 1136 | */ |
| 1137 | clrsetbits_le32(&gpmi_regs->hw_gpmi_ctrl1, |
| 1138 | GPMI_CTRL1_GPMI_MODE, |
| 1139 | GPMI_CTRL1_ATA_IRQRDY_POLARITY | GPMI_CTRL1_DEV_RESET | |
| 1140 | GPMI_CTRL1_BCH_MODE); |
| 1141 | |
| 1142 | return 0; |
| 1143 | |
Marek Vasut | 96666a3 | 2012-04-08 17:34:46 +0000 | [diff] [blame] | 1144 | err3: |
Peng Fan | 549d7c0 | 2016-01-27 10:38:02 +0800 | [diff] [blame] | 1145 | for (--j; j >= MXS_DMA_CHANNEL_AHB_APBH_GPMI0; j--) |
Marek Vasut | 96666a3 | 2012-04-08 17:34:46 +0000 | [diff] [blame] | 1146 | mxs_dma_release(j); |
Marek Vasut | 0d4e850 | 2011-11-08 23:18:16 +0000 | [diff] [blame] | 1147 | err2: |
Marek Vasut | 0d4e850 | 2011-11-08 23:18:16 +0000 | [diff] [blame] | 1148 | for (--i; i >= 0; i--) |
| 1149 | mxs_dma_desc_free(info->desc[i]); |
Peng Fan | 549d7c0 | 2016-01-27 10:38:02 +0800 | [diff] [blame] | 1150 | free(info->desc); |
| 1151 | err1: |
| 1152 | if (ret == -ENOMEM) |
| 1153 | printf("MXS NAND: Unable to allocate DMA descriptors\n"); |
| 1154 | return ret; |
Marek Vasut | 0d4e850 | 2011-11-08 23:18:16 +0000 | [diff] [blame] | 1155 | } |
| 1156 | |
Stefan Agner | 9345943 | 2018-06-22 17:19:46 +0200 | [diff] [blame] | 1157 | int mxs_nand_init_spl(struct nand_chip *nand) |
| 1158 | { |
| 1159 | struct mxs_nand_info *nand_info; |
| 1160 | int err; |
| 1161 | |
| 1162 | nand_info = malloc(sizeof(struct mxs_nand_info)); |
| 1163 | if (!nand_info) { |
| 1164 | printf("MXS NAND: Failed to allocate private data\n"); |
| 1165 | return -ENOMEM; |
| 1166 | } |
| 1167 | memset(nand_info, 0, sizeof(struct mxs_nand_info)); |
| 1168 | |
| 1169 | err = mxs_nand_alloc_buffers(nand_info); |
| 1170 | if (err) |
| 1171 | return err; |
| 1172 | |
| 1173 | err = mxs_nand_init(nand_info); |
| 1174 | if (err) |
| 1175 | return err; |
| 1176 | |
| 1177 | nand_set_controller_data(nand, nand_info); |
| 1178 | |
| 1179 | nand->options |= NAND_NO_SUBPAGE_WRITE; |
| 1180 | |
| 1181 | nand->cmd_ctrl = mxs_nand_cmd_ctrl; |
| 1182 | nand->dev_ready = mxs_nand_device_ready; |
| 1183 | nand->select_chip = mxs_nand_select_chip; |
Stefan Agner | 9345943 | 2018-06-22 17:19:46 +0200 | [diff] [blame] | 1184 | |
| 1185 | nand->read_byte = mxs_nand_read_byte; |
| 1186 | nand->read_buf = mxs_nand_read_buf; |
| 1187 | |
| 1188 | nand->ecc.read_page = mxs_nand_ecc_read_page; |
| 1189 | |
| 1190 | nand->ecc.mode = NAND_ECC_HW; |
| 1191 | nand->ecc.bytes = 9; |
| 1192 | nand->ecc.size = 512; |
| 1193 | nand->ecc.strength = 8; |
| 1194 | |
| 1195 | return 0; |
| 1196 | } |
| 1197 | |
Stefan Agner | 5346c31 | 2018-06-22 17:19:47 +0200 | [diff] [blame] | 1198 | void board_nand_init(void) |
Marek Vasut | 0d4e850 | 2011-11-08 23:18:16 +0000 | [diff] [blame] | 1199 | { |
Stefan Agner | 5346c31 | 2018-06-22 17:19:47 +0200 | [diff] [blame] | 1200 | struct mtd_info *mtd; |
Marek Vasut | 0d4e850 | 2011-11-08 23:18:16 +0000 | [diff] [blame] | 1201 | struct mxs_nand_info *nand_info; |
Stefan Agner | 5346c31 | 2018-06-22 17:19:47 +0200 | [diff] [blame] | 1202 | struct nand_chip *nand; |
Marek Vasut | 0d4e850 | 2011-11-08 23:18:16 +0000 | [diff] [blame] | 1203 | int err; |
| 1204 | |
| 1205 | nand_info = malloc(sizeof(struct mxs_nand_info)); |
| 1206 | if (!nand_info) { |
| 1207 | printf("MXS NAND: Failed to allocate private data\n"); |
Stefan Agner | 5346c31 | 2018-06-22 17:19:47 +0200 | [diff] [blame] | 1208 | return; |
Marek Vasut | 0d4e850 | 2011-11-08 23:18:16 +0000 | [diff] [blame] | 1209 | } |
| 1210 | memset(nand_info, 0, sizeof(struct mxs_nand_info)); |
| 1211 | |
Stefan Agner | 5346c31 | 2018-06-22 17:19:47 +0200 | [diff] [blame] | 1212 | nand = &nand_info->chip; |
| 1213 | mtd = nand_to_mtd(nand); |
Marek Vasut | 0d4e850 | 2011-11-08 23:18:16 +0000 | [diff] [blame] | 1214 | err = mxs_nand_alloc_buffers(nand_info); |
| 1215 | if (err) |
| 1216 | goto err1; |
| 1217 | |
| 1218 | err = mxs_nand_init(nand_info); |
| 1219 | if (err) |
| 1220 | goto err2; |
| 1221 | |
| 1222 | memset(&fake_ecc_layout, 0, sizeof(fake_ecc_layout)); |
| 1223 | |
Stefan Agner | dc0b69f | 2018-06-22 17:19:48 +0200 | [diff] [blame] | 1224 | #ifdef CONFIG_SYS_NAND_USE_FLASH_BBT |
| 1225 | nand->bbt_options |= NAND_BBT_USE_FLASH | NAND_BBT_NO_OOB; |
| 1226 | #endif |
| 1227 | |
Scott Wood | 17cb4b8 | 2016-05-30 13:57:56 -0500 | [diff] [blame] | 1228 | nand_set_controller_data(nand, nand_info); |
Marek Vasut | 0d4e850 | 2011-11-08 23:18:16 +0000 | [diff] [blame] | 1229 | nand->options |= NAND_NO_SUBPAGE_WRITE; |
| 1230 | |
| 1231 | nand->cmd_ctrl = mxs_nand_cmd_ctrl; |
| 1232 | |
| 1233 | nand->dev_ready = mxs_nand_device_ready; |
| 1234 | nand->select_chip = mxs_nand_select_chip; |
| 1235 | nand->block_bad = mxs_nand_block_bad; |
Marek Vasut | 0d4e850 | 2011-11-08 23:18:16 +0000 | [diff] [blame] | 1236 | |
| 1237 | nand->read_byte = mxs_nand_read_byte; |
| 1238 | |
| 1239 | nand->read_buf = mxs_nand_read_buf; |
| 1240 | nand->write_buf = mxs_nand_write_buf; |
| 1241 | |
Stefan Agner | 5346c31 | 2018-06-22 17:19:47 +0200 | [diff] [blame] | 1242 | /* first scan to find the device and get the page size */ |
| 1243 | if (nand_scan_ident(mtd, CONFIG_SYS_MAX_NAND_DEVICE, NULL)) |
| 1244 | goto err2; |
| 1245 | |
| 1246 | if (mxs_nand_setup_ecc(mtd)) |
| 1247 | goto err2; |
| 1248 | |
Marek Vasut | 0d4e850 | 2011-11-08 23:18:16 +0000 | [diff] [blame] | 1249 | nand->ecc.read_page = mxs_nand_ecc_read_page; |
| 1250 | nand->ecc.write_page = mxs_nand_ecc_write_page; |
| 1251 | nand->ecc.read_oob = mxs_nand_ecc_read_oob; |
| 1252 | nand->ecc.write_oob = mxs_nand_ecc_write_oob; |
| 1253 | |
| 1254 | nand->ecc.layout = &fake_ecc_layout; |
| 1255 | nand->ecc.mode = NAND_ECC_HW; |
| 1256 | nand->ecc.bytes = 9; |
| 1257 | nand->ecc.size = 512; |
Sergey Lapin | dfe64e2 | 2013-01-14 03:46:50 +0000 | [diff] [blame] | 1258 | nand->ecc.strength = 8; |
Marek Vasut | 0d4e850 | 2011-11-08 23:18:16 +0000 | [diff] [blame] | 1259 | |
Stefan Agner | 5346c31 | 2018-06-22 17:19:47 +0200 | [diff] [blame] | 1260 | /* second phase scan */ |
| 1261 | err = nand_scan_tail(mtd); |
| 1262 | if (err) |
| 1263 | goto err2; |
| 1264 | |
| 1265 | err = nand_register(0, mtd); |
| 1266 | if (err) |
| 1267 | goto err2; |
| 1268 | |
| 1269 | return; |
Marek Vasut | 0d4e850 | 2011-11-08 23:18:16 +0000 | [diff] [blame] | 1270 | |
| 1271 | err2: |
| 1272 | free(nand_info->data_buf); |
| 1273 | free(nand_info->cmd_buf); |
| 1274 | err1: |
| 1275 | free(nand_info); |
Stefan Agner | 5346c31 | 2018-06-22 17:19:47 +0200 | [diff] [blame] | 1276 | return; |
Marek Vasut | 0d4e850 | 2011-11-08 23:18:16 +0000 | [diff] [blame] | 1277 | } |