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TsiChung Liew012522f2008-10-21 10:03:07 +00001/*
2 * Queue Serial Peripheral Interface Memory Map
3 *
4 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
5 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
6 *
7 * See file CREDITS for list of people who contributed to this
8 * project.
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 * MA 02111-1307 USA
24 */
25
26#ifndef __QSPI_H__
27#define __QSPI_H__
28
29/* QSPI module registers */
30typedef struct qspi_ctrl {
31 u16 mr; /* 0x00 Mode */
32 u16 res1;
33 u16 dlyr; /* 0x04 Delay */
34 u16 res2;
35 u16 wr; /* 0x08 Wrap */
36 u16 res3;
37 u16 ir; /* 0x0C Interrupt */
38 u16 res4;
39 u16 ar; /* 0x10 Address */
40 u16 res5;
41 u16 dr; /* 0x14 Data */
42 u16 res6;
43} qspi_t;
44
45/* MR */
46#define QSPI_QMR_MSTR (0x8000)
47#define QSPI_QMR_DOHIE (0x4000)
48#define QSPI_QMR_BITS(x) (((x)&0x000F)<<10)
49#define QSPI_QMR_BITS_MASK (0xC3FF)
50#define QSPI_QMR_BITS_8 (0x2000)
51#define QSPI_QMR_BITS_9 (0x2400)
52#define QSPI_QMR_BITS_10 (0x2800)
53#define QSPI_QMR_BITS_11 (0x2C00)
54#define QSPI_QMR_BITS_12 (0x3000)
55#define QSPI_QMR_BITS_13 (0x3400)
56#define QSPI_QMR_BITS_14 (0x3800)
57#define QSPI_QMR_BITS_15 (0x3C00)
58#define QSPI_QMR_BITS_16 (0x0000)
59#define QSPI_QMR_CPOL (0x0200)
60#define QSPI_QMR_CPHA (0x0100)
61#define QSPI_QMR_BAUD(x) ((x)&0x00FF)
62#define QSPI_QMR_BAUD_MASK (0xFF00)
63
64/* DLYR */
65#define QSPI_QDLYR_SPE (0x8000)
66#define QSPI_QDLYR_QCD(x) (((x)&0x007F)<<8)
67#define QSPI_QDLYR_QCD_MASK (0x80FF)
68#define QSPI_QDLYR_DTL(x) ((x)&0x00FF)
69#define QSPI_QDLYR_DTL_MASK (0xFF00)
70
71/* WR */
72#define QSPI_QWR_HALT (0x8000)
73#define QSPI_QWR_WREN (0x4000)
74#define QSPI_QWR_WRTO (0x2000)
75#define QSPI_QWR_CSIV (0x1000)
76#define QSPI_QWR_ENDQP(x) (((x)&0x000F)<<8)
77#define QSPI_QWR_ENDQP_MASK (0xF0FF)
78#define QSPI_QWR_CPTQP(x) (((x)&0x000F)<<4)
79#define QSPI_QWR_CPTQP_MASK (0xFF0F)
80#define QSPI_QWR_NEWQP(x) ((x)&0x000F)
81#define QSPI_QWR_NEWQP_MASK (0xFFF0)
82
83/* IR */
84#define QSPI_QIR_WCEFB (0x8000)
85#define QSPI_QIR_ABRTB (0x4000)
86#define QSPI_QIR_ABRTL (0x1000)
87#define QSPI_QIR_WCEFE (0x0800)
88#define QSPI_QIR_ABRTE (0x0400)
89#define QSPI_QIR_SPIFE (0x0100)
90#define QSPI_QIR_WCEF (0x0008)
91#define QSPI_QIR_ABRT (0x0004)
92#define QSPI_QIR_SPIF (0x0001)
93
94/* AR */
95#define QSPI_QAR_ADDR(x) ((x)&0x003F)
96#define QSPI_QAR_ADDR_MASK (0xFFC0)
97#define QSPI_QAR_TRANS (0x0000)
98#define QSPI_QAR_RECV (0x0010)
99#define QSPI_QAR_CMD (0x0020)
100
101/* DR */
102#define QSPI_QDR_CONT (0x8000)
103#define QSPI_QDR_BITSE (0x4000)
104#define QSPI_QDR_DT (0x2000)
105#define QSPI_QDR_DSCK (0x1000)
106#define QSPI_QDR_QSPI_CS3 (0x0800)
107#define QSPI_QDR_QSPI_CS2 (0x0400)
108#define QSPI_QDR_QSPI_CS1 (0x0200)
109#define QSPI_QDR_QSPI_CS0 (0x0100)
110
111#endif /* __QSPI_H__ */