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wdenk354bc6f2002-08-26 21:53:16 +00001/*
2 * (C) Copyright 2000
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02005 * SPDX-License-Identifier: GPL-2.0+
wdenk354bc6f2002-08-26 21:53:16 +00006 */
7
8#include <common.h>
Masahiro Yamada02987932013-11-11 10:30:20 +09009#include "dipsw.h"
10#include "lcd.h"
11#include "rtc.h"
12#include "par.h"
13#include "pci.h"
wdenk354bc6f2002-08-26 21:53:16 +000014
15/* ------------------------------------------------------------------------- */
16
17#if defined(CONFIG_8260)
18
19#include <ioports.h>
20
21/*
22 * I/O Port configuration table
23 *
24 * if conf is 1, then that port pin will be configured at boot time
25 * according to the five values podr/pdir/ppar/psor/pdat for that entry
26 */
27
28const iop_conf_t iop_conf_tab[4][32] = {
29
wdenkbf9e3b32004-02-12 00:47:09 +000030 /* Port A configuration */
31 { /* conf ppar psor pdir podr pdat */
32 /* PA31 */ {0, 0, 0, 0, 0, 0},
33 /* PA30 */ {0, 0, 0, 0, 0, 0},
34 /* PA29 */ {0, 0, 0, 0, 0, 0},
35 /* PA28 */ {0, 0, 0, 0, 0, 0},
36 /* PA27 */ {0, 0, 0, 0, 0, 0},
37 /* PA26 */ {0, 0, 0, 0, 0, 0},
38 /* PA25 */ {0, 0, 0, 0, 0, 0},
39 /* PA24 */ {0, 0, 0, 0, 0, 0},
40 /* PA23 */ {0, 0, 0, 0, 0, 0},
41 /* PA22 */ {0, 0, 0, 0, 0, 0},
42 /* PA21 */ {0, 0, 0, 0, 0, 0},
43 /* PA20 */ {0, 0, 0, 0, 0, 0},
44 /* PA19 */ {0, 0, 0, 0, 0, 0},
45 /* PA18 */ {0, 0, 0, 0, 0, 0},
46 /* PA17 */ {0, 0, 0, 0, 0, 0},
47 /* PA16 */ {0, 0, 0, 0, 0, 0},
48 /* PA15 */ {0, 0, 0, 0, 0, 0},
49 /* PA14 */ {0, 0, 0, 0, 0, 0},
50 /* PA13 */ {0, 0, 0, 0, 0, 0},
51 /* PA12 */ {0, 0, 0, 0, 0, 0},
52 /* PA11 */ {0, 0, 0, 0, 0, 0},
53 /* PA10 */ {0, 0, 0, 0, 0, 0},
54 /* PA9 */ {1, 1, 0, 1, 0, 0},
55 /* SMC2 TXD */
56 /* PA8 */ {1, 1, 0, 0, 0, 0},
57 /* SMC2 RXD */
58 /* PA7 */ {0, 0, 0, 0, 0, 0},
59 /* PA6 */ {0, 0, 0, 0, 0, 0},
60 /* PA5 */ {0, 0, 0, 0, 0, 0},
61 /* PA4 */ {0, 0, 0, 0, 0, 0},
62 /* PA3 */ {0, 0, 0, 0, 0, 0},
63 /* PA2 */ {0, 0, 0, 0, 0, 0},
64 /* PA1 */ {0, 0, 0, 0, 0, 0},
65 /* PA0 */ {0, 0, 0, 0, 0, 0}
66 },
wdenk354bc6f2002-08-26 21:53:16 +000067
68
wdenkbf9e3b32004-02-12 00:47:09 +000069 { /* conf ppar psor pdir podr pdat */
70 /* PB31 */ {0, 0, 0, 0, 0, 0},
71 /* PB30 */ {0, 0, 0, 0, 0, 0},
72 /* PB29 */ {0, 0, 0, 0, 0, 0},
73 /* PB28 */ {0, 0, 0, 0, 0, 0},
74 /* PB27 */ {0, 0, 0, 0, 0, 0},
75 /* PB26 */ {0, 0, 0, 0, 0, 0},
76 /* PB25 */ {0, 0, 0, 0, 0, 0},
77 /* PB24 */ {0, 0, 0, 0, 0, 0},
78 /* PB23 */ {0, 0, 0, 0, 0, 0},
79 /* PB22 */ {0, 0, 0, 0, 0, 0},
80 /* PB21 */ {0, 0, 0, 0, 0, 0},
81 /* PB20 */ {0, 0, 0, 0, 0, 0},
82 /* PB19 */ {0, 0, 0, 0, 0, 0},
83 /* PB18 */ {0, 0, 0, 0, 0, 0},
84 /* PB17 */ {0, 0, 0, 0, 0, 0},
85 /* PB16 */ {0, 0, 0, 0, 0, 0},
86 /* PB15 */ {0, 0, 0, 0, 0, 0},
87 /* PB14 */ {0, 0, 0, 0, 0, 0},
88 /* PB13 */ {0, 0, 0, 0, 0, 0},
89 /* PB12 */ {0, 0, 0, 0, 0, 0},
90 /* PB11 */ {0, 0, 0, 0, 0, 0},
91 /* PB10 */ {0, 0, 0, 0, 0, 0},
92 /* PB9 */ {0, 0, 0, 0, 0, 0},
93 /* PB8 */ {0, 0, 0, 0, 0, 0},
94 /* PB7 */ {0, 0, 0, 0, 0, 0},
95 /* PB6 */ {0, 0, 0, 0, 0, 0},
96 /* PB5 */ {0, 0, 0, 0, 0, 0},
97 /* PB4 */ {0, 0, 0, 0, 0, 0},
98 /* PB3 */ {0, 0, 0, 0, 0, 0},
99 /* pin doesn't exist */
100 /* PB2 */ {0, 0, 0, 0, 0, 0},
101 /* pin doesn't exist */
102 /* PB1 */ {0, 0, 0, 0, 0, 0},
103 /* pin doesn't exist */
104 /* PB0 */ {0, 0, 0, 0, 0, 0}
105 /* pin doesn't exist */
106 },
wdenk354bc6f2002-08-26 21:53:16 +0000107
108
wdenkbf9e3b32004-02-12 00:47:09 +0000109 { /* conf ppar psor pdir podr pdat */
110 /* PC31 */ {0, 0, 0, 0, 0, 0},
111 /* PC30 */ {0, 0, 0, 0, 0, 0},
112 /* PC29 */ {0, 0, 0, 0, 0, 0},
113 /* PC28 */ {0, 0, 0, 0, 0, 0},
114 /* PC27 */ {0, 0, 0, 0, 0, 0},
115 /* PC26 */ {0, 0, 0, 0, 0, 0},
116 /* PC25 */ {0, 0, 0, 0, 0, 0},
117 /* PC24 */ {0, 0, 0, 0, 0, 0},
118 /* PC23 */ {0, 0, 0, 0, 0, 0},
119 /* PC22 */ {0, 0, 0, 0, 0, 0},
120 /* PC21 */ {0, 0, 0, 0, 0, 0},
121 /* PC20 */ {0, 0, 0, 0, 0, 0},
122 /* PC19 */ {0, 0, 0, 0, 0, 0},
123 /* PC18 */ {0, 0, 0, 0, 0, 0},
124 /* PC17 */ {0, 0, 0, 0, 0, 0},
125 /* PC16 */ {0, 0, 0, 0, 0, 0},
126 /* PC15 */ {0, 0, 0, 0, 0, 0},
127 /* PC14 */ {0, 0, 0, 0, 0, 0},
128 /* PC13 */ {0, 0, 0, 0, 0, 0},
129 /* PC12 */ {0, 0, 0, 0, 0, 0},
130 /* PC11 */ {0, 0, 0, 0, 0, 0},
131 /* PC10 */ {0, 0, 0, 0, 0, 0},
132 /* PC9 */ {0, 0, 0, 0, 0, 0},
133 /* PC8 */ {0, 0, 0, 0, 0, 0},
134 /* PC7 */ {0, 0, 0, 0, 0, 0},
135 /* PC6 */ {0, 0, 0, 0, 0, 0},
136 /* PC5 */ {0, 0, 0, 0, 0, 0},
137 /* PC4 */ {0, 0, 0, 0, 0, 0},
138 /* PC3 */ {0, 0, 0, 0, 0, 0},
139 /* PC2 */ {0, 0, 0, 0, 0, 0},
140 /* PC1 */ {0, 0, 0, 0, 0, 0},
141 /* PC0 */ {0, 0, 0, 0, 0, 0}
142 },
wdenk354bc6f2002-08-26 21:53:16 +0000143
144
wdenkbf9e3b32004-02-12 00:47:09 +0000145 { /* conf ppar psor pdir podr pdat */
146 /* PD31 */ {0, 0, 0, 0, 0, 0},
147 /* PD30 */ {0, 0, 0, 0, 0, 0},
148 /* PD29 */ {0, 0, 0, 0, 0, 0},
149 /* PD28 */ {0, 0, 0, 0, 0, 0},
150 /* PD27 */ {0, 0, 0, 0, 0, 0},
151 /* PD26 */ {0, 0, 0, 0, 0, 0},
152 /* PD25 */ {0, 0, 0, 0, 0, 0},
153 /* PD24 */ {0, 0, 0, 0, 0, 0},
154 /* PD23 */ {0, 0, 0, 0, 0, 0},
155 /* PD22 */ {0, 0, 0, 0, 0, 0},
156 /* PD21 */ {0, 0, 0, 0, 0, 0},
157 /* PD20 */ {0, 0, 0, 0, 0, 0},
158 /* PD19 */ {0, 0, 0, 0, 0, 0},
159 /* PD18 */ {0, 0, 0, 0, 0, 0},
160 /* PD17 */ {0, 0, 0, 0, 0, 0},
161 /* PD16 */ {0, 0, 0, 0, 0, 0},
162 /* PD15 */ {1, 1, 1, 0, 0, 0},
163 /* I2C SDA */
164 /* PD14 */ {1, 1, 1, 0, 0, 0},
165 /* I2C SCL */
166 /* PD13 */ {0, 0, 0, 0, 0, 0},
167 /* PD12 */ {0, 0, 0, 0, 0, 0},
168 /* PD11 */ {0, 0, 0, 0, 0, 0},
169 /* PD10 */ {0, 0, 0, 0, 0, 0},
170 /* PD9 */ {1, 1, 0, 1, 0, 0},
171 /* SMC1 TXD */
172 /* PD8 */ {1, 1, 0, 0, 0, 0},
173 /* SMC1 RXD */
174 /* PD7 */ {0, 0, 0, 0, 0, 0},
175 /* PD6 */ {0, 0, 0, 0, 0, 0},
176 /* PD5 */ {0, 0, 0, 0, 0, 0},
177 /* PD4 */ {0, 0, 0, 0, 0, 0},
178 /* PD3 */ {0, 0, 0, 0, 0, 0},
179 /* pin doesn't exist */
180 /* PD2 */ {0, 0, 0, 0, 0, 0},
181 /* pin doesn't exist */
182 /* PD1 */ {0, 0, 0, 0, 0, 0},
183 /* pin doesn't exist */
184 /* PD0 */ {0, 0, 0, 0, 0, 0}
185 /* pin doesn't exist */
186 }
wdenk354bc6f2002-08-26 21:53:16 +0000187};
188
wdenkbf9e3b32004-02-12 00:47:09 +0000189#endif /* CONFIG_8260 */
wdenk354bc6f2002-08-26 21:53:16 +0000190
191/* ------------------------------------------------------------------------- */
192
193/*
194 * Check Board Identity:
195 */
196
wdenkbf9e3b32004-02-12 00:47:09 +0000197int checkboard (void)
wdenk354bc6f2002-08-26 21:53:16 +0000198{
wdenkbf9e3b32004-02-12 00:47:09 +0000199 puts ("Board: Cogent " COGENT_MOTHERBOARD " motherboard with a "
200 COGENT_CPU_MODULE " CPU Module\n");
201 return (0);
wdenk354bc6f2002-08-26 21:53:16 +0000202}
203
204/* ------------------------------------------------------------------------- */
205
206/*
207 * Miscelaneous platform dependent initialisations while still
208 * running in flash
209 */
210
211int misc_init_f (void)
212{
wdenkbf9e3b32004-02-12 00:47:09 +0000213 printf ("DIPSW: ");
214 dipsw_init ();
215 return (0);
wdenk354bc6f2002-08-26 21:53:16 +0000216}
217
218/* ------------------------------------------------------------------------- */
219
Becky Bruce9973e3c2008-06-09 16:03:40 -0500220phys_size_t initdram (int board_type)
wdenk354bc6f2002-08-26 21:53:16 +0000221{
wdenk42dfe7a2004-03-14 22:25:36 +0000222#ifdef CONFIG_CMA111
wdenkbf9e3b32004-02-12 00:47:09 +0000223 return (32L * 1024L * 1024L);
wdenk354bc6f2002-08-26 21:53:16 +0000224#else
wdenkbf9e3b32004-02-12 00:47:09 +0000225 unsigned char dipsw_val;
226 int dual, size0, size1;
227 long int memsize;
wdenk354bc6f2002-08-26 21:53:16 +0000228
wdenkbf9e3b32004-02-12 00:47:09 +0000229 dipsw_val = dipsw_cooked ();
wdenk354bc6f2002-08-26 21:53:16 +0000230
wdenkbf9e3b32004-02-12 00:47:09 +0000231 dual = dipsw_val & 0x01;
232 size0 = (dipsw_val & 0x08) >> 3;
233 size1 = (dipsw_val & 0x04) >> 2;
wdenk354bc6f2002-08-26 21:53:16 +0000234
wdenkbf9e3b32004-02-12 00:47:09 +0000235 if (size0)
236 if (size1)
237 memsize = 16L * 1024L * 1024L;
238 else
239 memsize = 1L * 1024L * 1024L;
240 else if (size1)
241 memsize = 4L * 1024L * 1024L;
wdenk354bc6f2002-08-26 21:53:16 +0000242 else {
wdenkbf9e3b32004-02-12 00:47:09 +0000243 printf ("[Illegal dip switch settings - assuming 16Mbyte SIMMs] ");
244 memsize = 16L * 1024L * 1024L; /* shouldn't happen - guess 16M */
wdenk354bc6f2002-08-26 21:53:16 +0000245 }
246
wdenkbf9e3b32004-02-12 00:47:09 +0000247 if (dual)
248 memsize *= 2L;
wdenk354bc6f2002-08-26 21:53:16 +0000249
wdenkbf9e3b32004-02-12 00:47:09 +0000250 return (memsize);
wdenk354bc6f2002-08-26 21:53:16 +0000251#endif
252}
253
254/* ------------------------------------------------------------------------- */
255
256/*
257 * Miscelaneous platform dependent initialisations after monitor
258 * has been relocated into ram
259 */
260
261int misc_init_r (void)
262{
wdenkbf9e3b32004-02-12 00:47:09 +0000263 printf ("LCD: ");
264 lcd_init ();
wdenk354bc6f2002-08-26 21:53:16 +0000265
266#if 0
wdenkbf9e3b32004-02-12 00:47:09 +0000267 printf ("RTC: ");
268 rtc_init ();
wdenk354bc6f2002-08-26 21:53:16 +0000269
wdenkbf9e3b32004-02-12 00:47:09 +0000270 printf ("PAR: ");
271 par_init ();
wdenk354bc6f2002-08-26 21:53:16 +0000272
wdenkbf9e3b32004-02-12 00:47:09 +0000273 printf ("KBM: ");
274 kbm_init ();
wdenk354bc6f2002-08-26 21:53:16 +0000275
wdenkbf9e3b32004-02-12 00:47:09 +0000276 printf ("PCI: ");
277 pci_init ();
wdenk354bc6f2002-08-26 21:53:16 +0000278#endif
wdenkbf9e3b32004-02-12 00:47:09 +0000279 return (0);
wdenk354bc6f2002-08-26 21:53:16 +0000280}