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Po-Yu Chuang43a5f0d2009-11-11 17:27:30 +08001/*
2 * (C) Copyright 2009 Faraday Technology
3 * Po-Yu Chuang <ratbert@faraday-tech.com>
4 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02005 * SPDX-License-Identifier: GPL-2.0+
Po-Yu Chuang43a5f0d2009-11-11 17:27:30 +08006 */
7
8#include <config.h>
9#include <version.h>
10
11#include <asm/macro.h>
Macpaul Lin5656b402011-04-15 21:37:10 +000012#include <faraday/ftsdmc020.h>
Po-Yu Chuang43a5f0d2009-11-11 17:27:30 +080013
14/*
15 * parameters for the SDRAM controller
16 */
17#define TP0_A (CONFIG_FTSDMC020_BASE + FTSDMC020_OFFSET_TP0)
18#define TP1_A (CONFIG_FTSDMC020_BASE + FTSDMC020_OFFSET_TP1)
19#define CR_A (CONFIG_FTSDMC020_BASE + FTSDMC020_OFFSET_CR)
20#define B0_BSR_A (CONFIG_FTSDMC020_BASE + FTSDMC020_OFFSET_BANK0_BSR)
21#define ACR_A (CONFIG_FTSDMC020_BASE + FTSDMC020_OFFSET_ACR)
22
23#define TP0_D CONFIG_SYS_FTSDMC020_TP0
24#define TP1_D CONFIG_SYS_FTSDMC020_TP1
25#define CR_D1 FTSDMC020_CR_IPREC
26#define CR_D2 FTSDMC020_CR_ISMR
27#define CR_D3 FTSDMC020_CR_IREF
28
29#define B0_BSR_D (CONFIG_SYS_FTSDMC020_BANK0_BSR | \
30 FTSDMC020_BANK_BASE(PHYS_SDRAM_1))
31#define ACR_D FTSDMC020_ACR_TOC(0x18)
32
33/*
34 * numeric 7 segment display
35 */
36.macro led, num
37 write32 CONFIG_DEBUG_LED, \num
38.endm
39
40/*
41 * Waiting for SDRAM to set up
42 */
43.macro wait_sdram
44 ldr r0, =CONFIG_FTSDMC020_BASE
451:
46 ldr r1, [r0, #FTSDMC020_OFFSET_CR]
47 cmp r1, #0
48 bne 1b
49.endm
50
51.globl lowlevel_init
52lowlevel_init:
53 mov r11, lr
54
55 led 0x0
56
57 bl init_sdmc
58
59 led 0x1
60
61 /* everything is fine now */
62 mov lr, r11
63 mov pc, lr
64
65/*
66 * memory initialization
67 */
68init_sdmc:
69 led 0x10
70
71 /* set SDRAM register */
72
73 write32 TP0_A, TP0_D
74 led 0x11
75
76 write32 TP1_A, TP1_D
77 led 0x12
78
79 /* set to precharge */
80 write32 CR_A, CR_D1
81 led 0x13
82
83 wait_sdram
84 led 0x14
85
86 /* set mode register */
87 write32 CR_A, CR_D2
88 led 0x15
89
90 wait_sdram
91 led 0x16
92
93 /* set to refresh */
94 write32 CR_A, CR_D3
95 led 0x17
96
97 wait_sdram
98 led 0x18
99
100 write32 B0_BSR_A, B0_BSR_D
101 led 0x19
102
103 write32 ACR_A, ACR_D
104 led 0x1a
105
106 mov pc, lr