blob: b2a5c19e0ef291645c17d69ddcfef6ba04f78249 [file] [log] [blame]
York Sunb5b06fb2012-12-23 19:25:27 +00001/*
2 * Copyright 2011-2012 Freescale Semiconductor, Inc.
3 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02004 * SPDX-License-Identifier: GPL-2.0+
York Sunb5b06fb2012-12-23 19:25:27 +00005 */
6
7#ifndef __CONFIG_H
8#define __CONFIG_H
9
10/*
11 * B4860 QDS board configuration file
12 */
13#define CONFIG_B4860QDS
14#define CONFIG_PHYS_64BIT
15
16#ifdef CONFIG_RAMBOOT_PBL
17#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
18#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
Shaohui Xie83d92562013-09-22 09:56:02 +080019#define CONFIG_PBLPBI_CONFIG $(SRCTREE)/board/freescale/b4860qds/b4_pbi.cfg
20#define CONFIG_PBLRCW_CONFIG $(SRCTREE)/board/freescale/b4860qds/b4_rcw.cfg
York Sunb5b06fb2012-12-23 19:25:27 +000021#endif
22
Liu Gang5870fe42013-05-07 16:30:48 +080023#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
24/* Set 1M boot space */
25#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
26#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
27 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
28#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
29#define CONFIG_SYS_NO_FLASH
30#endif
31
York Sunb5b06fb2012-12-23 19:25:27 +000032/* High Level Configuration Options */
33#define CONFIG_BOOKE
York Sunb5b06fb2012-12-23 19:25:27 +000034#define CONFIG_E500 /* BOOKE e500 family */
35#define CONFIG_E500MC /* BOOKE e500mc family */
36#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
37#define CONFIG_MPC85xx /* MPC85xx/PQ3 platform */
York Sunb5b06fb2012-12-23 19:25:27 +000038#define CONFIG_MP /* support multiple processors */
39
40#ifndef CONFIG_SYS_TEXT_BASE
41#define CONFIG_SYS_TEXT_BASE 0xeff80000
42#endif
43
44#ifndef CONFIG_RESET_VECTOR_ADDRESS
45#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
46#endif
47
48#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
49#define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS
50#define CONFIG_FSL_IFC /* Enable IFC Support */
51#define CONFIG_PCI /* Enable PCI/PCIE */
52#define CONFIG_PCIE1 /* PCIE controler 1 */
53#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
54#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
55
56#ifndef CONFIG_PPC_B4420
57#define CONFIG_SYS_SRIO
58#define CONFIG_SRIO1 /* SRIO port 1 */
59#define CONFIG_SRIO2 /* SRIO port 2 */
Liu Gang3a017992013-05-07 16:30:47 +080060#define CONFIG_SRIO_PCIE_BOOT_MASTER
York Sunb5b06fb2012-12-23 19:25:27 +000061#endif
62
63#define CONFIG_FSL_LAW /* Use common FSL init code */
64
65/* I2C bus multiplexer */
66#define I2C_MUX_PCA_ADDR 0x77
67
68/* VSC Crossbar switches */
69#define CONFIG_VSC_CROSSBAR
70#define I2C_CH_DEFAULT 0x8
71#define I2C_CH_VSC3316 0xc
72#define I2C_CH_VSC3308 0xd
73
74#define VSC3316_TX_ADDRESS 0x70
75#define VSC3316_RX_ADDRESS 0x71
76#define VSC3308_TX_ADDRESS 0x02
77#define VSC3308_RX_ADDRESS 0x03
78
Shaveta Leekhacb033742013-07-02 14:43:53 +053079/* IDT clock synthesizers */
80#define CONFIG_IDT8T49N222A
81#define I2C_CH_IDT 0x9
82
83#define IDT_SERDES1_ADDRESS 0x6E
84#define IDT_SERDES2_ADDRESS 0x6C
85
York Sunb5b06fb2012-12-23 19:25:27 +000086#define CONFIG_ENV_OVERWRITE
87
88#ifdef CONFIG_SYS_NO_FLASH
Liu Gang5870fe42013-05-07 16:30:48 +080089#if !defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) && !defined(CONFIG_RAMBOOT_PBL)
York Sunb5b06fb2012-12-23 19:25:27 +000090#define CONFIG_ENV_IS_NOWHERE
Liu Gang5870fe42013-05-07 16:30:48 +080091#endif
York Sunb5b06fb2012-12-23 19:25:27 +000092#else
93#define CONFIG_FLASH_CFI_DRIVER
94#define CONFIG_SYS_FLASH_CFI
95#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
96#endif
97
York Sunb5b06fb2012-12-23 19:25:27 +000098#if defined(CONFIG_SPIFLASH)
99#define CONFIG_SYS_EXTRA_ENV_RELOC
100#define CONFIG_ENV_IS_IN_SPI_FLASH
101#define CONFIG_ENV_SPI_BUS 0
102#define CONFIG_ENV_SPI_CS 0
103#define CONFIG_ENV_SPI_MAX_HZ 10000000
104#define CONFIG_ENV_SPI_MODE 0
105#define CONFIG_ENV_SIZE 0x2000 /* 8KB */
106#define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
107#define CONFIG_ENV_SECT_SIZE 0x10000
108#elif defined(CONFIG_SDCARD)
109#define CONFIG_SYS_EXTRA_ENV_RELOC
110#define CONFIG_ENV_IS_IN_MMC
111#define CONFIG_SYS_MMC_ENV_DEV 0
112#define CONFIG_ENV_SIZE 0x2000
113#define CONFIG_ENV_OFFSET (512 * 1097)
114#elif defined(CONFIG_NAND)
115#define CONFIG_SYS_EXTRA_ENV_RELOC
116#define CONFIG_ENV_IS_IN_NAND
117#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
118#define CONFIG_ENV_OFFSET (5 * CONFIG_SYS_NAND_BLOCK_SIZE)
Liu Gang5870fe42013-05-07 16:30:48 +0800119#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
120#define CONFIG_ENV_IS_IN_REMOTE
121#define CONFIG_ENV_ADDR 0xffe20000
122#define CONFIG_ENV_SIZE 0x2000
123#elif defined(CONFIG_ENV_IS_NOWHERE)
124#define CONFIG_ENV_SIZE 0x2000
York Sunb5b06fb2012-12-23 19:25:27 +0000125#else
126#define CONFIG_ENV_IS_IN_FLASH
127#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
128#define CONFIG_ENV_SIZE 0x2000
129#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
130#endif
York Sunb5b06fb2012-12-23 19:25:27 +0000131
132#ifndef __ASSEMBLY__
133unsigned long get_board_sys_clk(void);
134unsigned long get_board_ddr_clk(void);
135#endif
136#define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */
137#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk()
138
139/*
140 * These can be toggled for performance analysis, otherwise use default.
141 */
142#define CONFIG_SYS_CACHE_STASHING
143#define CONFIG_BTB /* toggle branch predition */
144#define CONFIG_DDR_ECC
145#ifdef CONFIG_DDR_ECC
146#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
147#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
148#endif
149
150#define CONFIG_ENABLE_36BIT_PHYS
151
152#ifdef CONFIG_PHYS_64BIT
153#define CONFIG_ADDR_MAP
154#define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */
155#endif
156
157#if 0
158#define CONFIG_POST CONFIG_SYS_POST_MEMORY /* test POST memory test */
159#endif
160#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
161#define CONFIG_SYS_MEMTEST_END 0x00400000
162#define CONFIG_SYS_ALT_MEMTEST
163#define CONFIG_PANIC_HANG /* do not reset board on panic */
164
165/*
166 * Config the L3 Cache as L3 SRAM
167 */
168#define CONFIG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE
169
170#ifdef CONFIG_PHYS_64BIT
171#define CONFIG_SYS_DCSRBAR 0xf0000000
172#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
173#endif
174
175/* EEPROM */
176#define CONFIG_SYS_I2C_EEPROM_NXID
177#define CONFIG_SYS_EEPROM_BUS_NUM 0
178#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
179#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
180#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
181#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
182
183/*
184 * DDR Setup
185 */
186#define CONFIG_VERY_BIG_RAM
187#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
188#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
189
190/* CONFIG_NUM_DDR_CONTROLLERS is defined in include/asm/config_mpc85xx.h */
191#define CONFIG_DIMM_SLOTS_PER_CTLR 1
192#define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
193
194#define CONFIG_DDR_SPD
195#define CONFIG_SYS_DDR_RAW_TIMING
York Sun5614e712013-09-30 09:22:09 -0700196#define CONFIG_SYS_FSL_DDR3
York Sunb5b06fb2012-12-23 19:25:27 +0000197#define CONFIG_FSL_DDR_INTERACTIVE
198
199#define CONFIG_SYS_SPD_BUS_NUM 0
200#define SPD_EEPROM_ADDRESS1 0x51
201#define SPD_EEPROM_ADDRESS2 0x53
202
203#define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1
204#define CONFIG_SYS_SDRAM_SIZE 2048 /* for fixed parameter use */
205
206/*
207 * IFC Definitions
208 */
209#define CONFIG_SYS_FLASH_BASE 0xe0000000
210#ifdef CONFIG_PHYS_64BIT
211#define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
212#else
213#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
214#endif
215
216#define CONFIG_SYS_NOR0_CSPR_EXT (0xf)
217#define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
218 + 0x8000000) | \
219 CSPR_PORT_SIZE_16 | \
220 CSPR_MSEL_NOR | \
221 CSPR_V)
222#define CONFIG_SYS_NOR1_CSPR_EXT (0xf)
223#define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
224 CSPR_PORT_SIZE_16 | \
225 CSPR_MSEL_NOR | \
226 CSPR_V)
227#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024)
228/* NOR Flash Timing Params */
229#define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(4)
230#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x01) | \
Prabhakar Kushwaha4d0e6e02013-05-17 13:40:52 +0530231 FTIM0_NOR_TEADC(0x04) | \
York Sunb5b06fb2012-12-23 19:25:27 +0000232 FTIM0_NOR_TEAHC(0x20))
233#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
234 FTIM1_NOR_TRAD_NOR(0x1A) |\
235 FTIM1_NOR_TSEQRAD_NOR(0x13))
236#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x01) | \
237 FTIM2_NOR_TCH(0x0E) | \
238 FTIM2_NOR_TWPH(0x0E) | \
239 FTIM2_NOR_TWP(0x1c))
240#define CONFIG_SYS_NOR_FTIM3 0x0
241
242#define CONFIG_SYS_FLASH_QUIET_TEST
243#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
244
245#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
246#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
247#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
248#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
249
250#define CONFIG_SYS_FLASH_EMPTY_INFO
251#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \
252 + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
253
254#define CONFIG_FSL_QIXIS /* use common QIXIS code */
255#define CONFIG_FSL_QIXIS_V2
256#define QIXIS_BASE 0xffdf0000
257#ifdef CONFIG_PHYS_64BIT
258#define QIXIS_BASE_PHYS (0xf00000000ull | QIXIS_BASE)
259#else
260#define QIXIS_BASE_PHYS QIXIS_BASE
261#endif
262#define QIXIS_LBMAP_SWITCH 0x01
263#define QIXIS_LBMAP_MASK 0x0f
264#define QIXIS_LBMAP_SHIFT 0
265#define QIXIS_LBMAP_DFLTBANK 0x00
266#define QIXIS_LBMAP_ALTBANK 0x02
267#define QIXIS_RST_CTL_RESET 0x31
268#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
269#define QIXIS_RCFG_CTL_RECONFIG_START 0x21
270#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
271
272#define CONFIG_SYS_CSPR3_EXT (0xf)
273#define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
274 | CSPR_PORT_SIZE_8 \
275 | CSPR_MSEL_GPCM \
276 | CSPR_V)
277#define CONFIG_SYS_AMASK3 IFC_AMASK(4 * 1024)
278#define CONFIG_SYS_CSOR3 0x0
279/* QIXIS Timing parameters for IFC CS3 */
280#define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
281 FTIM0_GPCM_TEADC(0x0e) | \
282 FTIM0_GPCM_TEAHC(0x0e))
283#define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \
284 FTIM1_GPCM_TRAD(0x1f))
285#define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
286 FTIM2_GPCM_TCH(0x0) | \
287 FTIM2_GPCM_TWP(0x1f))
288#define CONFIG_SYS_CS3_FTIM3 0x0
289
290/* NAND Flash on IFC */
291#define CONFIG_NAND_FSL_IFC
292#define CONFIG_SYS_NAND_BASE 0xff800000
293#ifdef CONFIG_PHYS_64BIT
294#define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)
295#else
296#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
297#endif
298
299#define CONFIG_SYS_NAND_CSPR_EXT (0xf)
300#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
301 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
302 | CSPR_MSEL_NAND /* MSEL = NAND */ \
303 | CSPR_V)
304#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024)
305
306#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
307 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
308 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
309 | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \
310 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \
311 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
312 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
313
314#define CONFIG_SYS_NAND_ONFI_DETECTION
315
316/* ONFI NAND Flash mode0 Timing Params */
317#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
318 FTIM0_NAND_TWP(0x18) | \
319 FTIM0_NAND_TWCHT(0x07) | \
320 FTIM0_NAND_TWH(0x0a))
321#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
322 FTIM1_NAND_TWBE(0x39) | \
323 FTIM1_NAND_TRR(0x0e) | \
324 FTIM1_NAND_TRP(0x18))
325#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
326 FTIM2_NAND_TREH(0x0a) | \
327 FTIM2_NAND_TWHRE(0x1e))
328#define CONFIG_SYS_NAND_FTIM3 0x0
329
330#define CONFIG_SYS_NAND_DDR_LAW 11
331
332#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
333#define CONFIG_SYS_MAX_NAND_DEVICE 1
334#define CONFIG_MTD_NAND_VERIFY_WRITE
335#define CONFIG_CMD_NAND
336
337#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
338
339#if defined(CONFIG_NAND)
340#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
341#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
342#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
343#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
344#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
345#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
346#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
347#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
348#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR0_CSPR_EXT
349#define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR0_CSPR
350#define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK
351#define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
352#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
353#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
354#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
355#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
356#else
357#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
358#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
359#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
360#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
361#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
362#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
363#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
364#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
365#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
366#define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
367#define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
368#define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
369#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
370#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
371#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
372#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
373#endif
374#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT
375#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR
376#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
377#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
378#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
379#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
380#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
381#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
382
383#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
384
385#if defined(CONFIG_RAMBOOT_PBL)
386#define CONFIG_SYS_RAMBOOT
387#endif
388
389#define CONFIG_BOARD_EARLY_INIT_R
390#define CONFIG_MISC_INIT_R
391
392#define CONFIG_HWCONFIG
393
394/* define to use L1 as initial stack */
395#define CONFIG_L1_INIT_RAM
396#define CONFIG_SYS_INIT_RAM_LOCK
397#define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
398#ifdef CONFIG_PHYS_64BIT
399#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
400#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe0ec000
401/* The assembler doesn't like typecast */
402#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
403 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
404 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
405#else
406#define CONFIG_SYS_INIT_RAM_ADDR_PHYS 0xfe0ec000 /* Initial L1 address */
407#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
408#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
409#endif
410#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
411
412#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
413 GENERATED_GBL_DATA_SIZE)
414#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
415
416#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
417#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
418
419/* Serial Port - controlled on board with jumper J8
420 * open - index 2
421 * shorted - index 1
422 */
423#define CONFIG_CONS_INDEX 1
424#define CONFIG_SYS_NS16550
425#define CONFIG_SYS_NS16550_SERIAL
426#define CONFIG_SYS_NS16550_REG_SIZE 1
427#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
428
429#define CONFIG_SYS_BAUDRATE_TABLE \
430 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
431
432#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
433#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
434#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
435#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
436#define CONFIG_SERIAL_MULTI /* Enable both serial ports */
437#define CONFIG_SYS_CONSOLE_IS_IN_ENV /* determine from environment */
438
439
440/* Use the HUSH parser */
441#define CONFIG_SYS_HUSH_PARSER
442#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
443
444/* pass open firmware flat tree */
445#define CONFIG_OF_LIBFDT
446#define CONFIG_OF_BOARD_SETUP
447#define CONFIG_OF_STDOUT_VIA_ALIAS
448
449/* new uImage format support */
450#define CONFIG_FIT
451#define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */
452
453/* I2C */
Heiko Schocher00f792e2012-10-24 13:48:22 +0200454#define CONFIG_SYS_I2C
455#define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */
456#define CONFIG_SYS_FSL_I2C_SPEED 400000 /* I2C speed in Hz */
457#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
458#define CONFIG_SYS_FSL_I2C2_SPEED 400000 /* I2C speed in Hz */
459#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
460#define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
461#define CONFIG_SYS_FSL_I2C2_OFFSET 0x119000
York Sunb5b06fb2012-12-23 19:25:27 +0000462
463/*
464 * RTC configuration
465 */
466#define RTC
467#define CONFIG_RTC_DS3231 1
468#define CONFIG_SYS_I2C_RTC_ADDR 0x68
469
470/*
471 * RapidIO
472 */
473#ifdef CONFIG_SYS_SRIO
474#ifdef CONFIG_SRIO1
475#define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000
476#ifdef CONFIG_PHYS_64BIT
477#define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull
478#else
479#define CONFIG_SYS_SRIO1_MEM_PHYS 0xa0000000
480#endif
481#define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */
482#endif
483
484#ifdef CONFIG_SRIO2
485#define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000
486#ifdef CONFIG_PHYS_64BIT
487#define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull
488#else
489#define CONFIG_SYS_SRIO2_MEM_PHYS 0xb0000000
490#endif
491#define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */
492#endif
493#endif
494
495/*
496 * for slave u-boot IMAGE instored in master memory space,
497 * PHYS must be aligned based on the SIZE
498 */
499#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef080000ull
500#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff80000ull
501#define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x80000 /* 512K */
502#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff80000ull
503/*
504 * for slave UCODE and ENV instored in master memory space,
505 * PHYS must be aligned based on the SIZE
506 */
507#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef040000ull
508#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
509#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */
510
511/* slave core release by master*/
512#define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
513#define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
514
515/*
516 * SRIO_PCIE_BOOT - SLAVE
517 */
518#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
519#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
520#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
521 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
522#endif
523
524/*
525 * eSPI - Enhanced SPI
526 */
527#define CONFIG_FSL_ESPI
528#define CONFIG_SPI_FLASH
529#define CONFIG_SPI_FLASH_SST
530#define CONFIG_CMD_SF
531#define CONFIG_SF_DEFAULT_SPEED 10000000
532#define CONFIG_SF_DEFAULT_MODE 0
533
534/*
Shaveta Leekha6eaeba22013-03-25 07:40:24 +0000535 * MAPLE
536 */
537#ifdef CONFIG_PHYS_64BIT
538#define CONFIG_SYS_MAPLE_MEM_PHYS 0xFA0000000ull
539#else
540#define CONFIG_SYS_MAPLE_MEM_PHYS 0xA0000000
541#endif
542
543/*
York Sunb5b06fb2012-12-23 19:25:27 +0000544 * General PCI
545 * Memory space is mapped 1-1, but I/O space must start from 0.
546 */
547
548/* controller 1, direct to uli, tgtid 3, Base address 20000 */
549#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
550#ifdef CONFIG_PHYS_64BIT
551#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
552#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
553#else
554#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
555#define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000
556#endif
557#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
558#define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
559#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
560#ifdef CONFIG_PHYS_64BIT
561#define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
562#else
563#define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000
564#endif
565#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
566
567/* Qman/Bman */
568#ifndef CONFIG_NOBQFMAN
569#define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */
570#define CONFIG_SYS_BMAN_NUM_PORTALS 25
571#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
572#ifdef CONFIG_PHYS_64BIT
573#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
574#else
575#define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE
576#endif
577#define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
578#define CONFIG_SYS_QMAN_NUM_PORTALS 25
579#define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
580#ifdef CONFIG_PHYS_64BIT
581#define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
582#else
583#define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE
584#endif
585#define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
586
587#define CONFIG_SYS_DPAA_FMAN
588
Minghuan Lian0795eff2013-07-03 18:32:41 +0800589#define CONFIG_SYS_DPAA_RMAN
590
York Sunb5b06fb2012-12-23 19:25:27 +0000591/* Default address of microcode for the Linux Fman driver */
592#if defined(CONFIG_SPIFLASH)
593/*
594 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
595 * env, so we got 0x110000.
596 */
597#define CONFIG_SYS_QE_FW_IN_SPIFLASH
598#define CONFIG_SYS_QE_FMAN_FW_ADDR 0x110000
599#elif defined(CONFIG_SDCARD)
600/*
601 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
602 * about 545KB (1089 blocks), Env is stored after the image, and the env size is
603 * 0x2000 (16 blocks), 8 + 1089 + 16 = 1113, enlarge it to 1130.
604 */
605#define CONFIG_SYS_QE_FMAN_FW_IN_MMC
606#define CONFIG_SYS_QE_FMAN_FW_ADDR (512 * 1130)
607#elif defined(CONFIG_NAND)
608#define CONFIG_SYS_QE_FMAN_FW_IN_NAND
609#define CONFIG_SYS_QE_FMAN_FW_ADDR (6 * CONFIG_SYS_NAND_BLOCK_SIZE)
Liu Gang5870fe42013-05-07 16:30:48 +0800610#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
611/*
612 * Slave has no ucode locally, it can fetch this from remote. When implementing
613 * in two corenet boards, slave's ucode could be stored in master's memory
614 * space, the address can be mapped from slave TLB->slave LAW->
615 * slave SRIO or PCIE outbound window->master inbound window->
616 * master LAW->the ucode address in master's memory space.
617 */
618#define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE
619#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xFFE00000
York Sunb5b06fb2012-12-23 19:25:27 +0000620#else
621#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
622#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xEFF40000
623#endif
624#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
625#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
626#endif /* CONFIG_NOBQFMAN */
627
628#ifdef CONFIG_SYS_DPAA_FMAN
629#define CONFIG_FMAN_ENET
630#define CONFIG_PHYLIB_10G
631#define CONFIG_PHY_VITESSE
632#define CONFIG_PHY_TERANETICS
633#define SGMII_CARD_PORT1_PHY_ADDR 0x1C
634#define SGMII_CARD_PORT2_PHY_ADDR 0x10
635#define SGMII_CARD_PORT3_PHY_ADDR 0x1E
636#define SGMII_CARD_PORT4_PHY_ADDR 0x11
637#endif
638
639#ifdef CONFIG_PCI
Gabor Juhos842033e2013-05-30 07:06:12 +0000640#define CONFIG_PCI_INDIRECT_BRIDGE
York Sunb5b06fb2012-12-23 19:25:27 +0000641#define CONFIG_NET_MULTI
642#define CONFIG_PCI_PNP /* do pci plug-and-play */
643#define CONFIG_E1000
644
645#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
646#define CONFIG_DOS_PARTITION
647#endif /* CONFIG_PCI */
648
649#ifdef CONFIG_FMAN_ENET
650#define CONFIG_SYS_FM1_DTSEC5_PHY_ADDR 0x10
651#define CONFIG_SYS_FM1_DTSEC6_PHY_ADDR 0x11
Suresh Gupta16d88f42013-03-25 07:40:13 +0000652
653/*B4860 QDS AMC2PEX-2S default PHY_ADDR */
654#define CONFIG_SYS_FM1_10GEC1_PHY_ADDR 0x7 /*SLOT 1*/
655#define CONFIG_SYS_FM1_10GEC2_PHY_ADDR 0x6 /*SLOT 2*/
656
York Sunb5b06fb2012-12-23 19:25:27 +0000657
658#define CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR 0x1c
659#define CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR 0x1d
660#define CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR 0x1e
661#define CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR 0x1f
662
663#define CONFIG_MII /* MII PHY management */
664#define CONFIG_ETHPRIME "FM1@DTSEC1"
665#define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
666#endif
667
668/*
669 * Environment
670 */
671#define CONFIG_LOADS_ECHO /* echo on for serial download */
672#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
673
674/*
675 * Command line configuration.
676 */
677#include <config_cmd_default.h>
678
679#define CONFIG_CMD_DATE
680#define CONFIG_CMD_DHCP
681#define CONFIG_CMD_EEPROM
682#define CONFIG_CMD_ELF
683#define CONFIG_CMD_ERRATA
684#define CONFIG_CMD_GREPENV
685#define CONFIG_CMD_IRQ
686#define CONFIG_CMD_I2C
687#define CONFIG_CMD_MII
688#define CONFIG_CMD_PING
689#define CONFIG_CMD_REGINFO
690#define CONFIG_CMD_SETEXPR
691
692#ifdef CONFIG_PCI
693#define CONFIG_CMD_PCI
694#define CONFIG_CMD_NET
695#endif
696
697/*
698* USB
699*/
700#define CONFIG_HAS_FSL_DR_USB
701
702#ifdef CONFIG_HAS_FSL_DR_USB
703#define CONFIG_USB_EHCI
704
705#ifdef CONFIG_USB_EHCI
706#define CONFIG_CMD_USB
707#define CONFIG_USB_STORAGE
708#define CONFIG_USB_EHCI_FSL
709#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
710#define CONFIG_CMD_EXT2
711#endif
712#endif
713
714/*
715 * Miscellaneous configurable options
716 */
717#define CONFIG_SYS_LONGHELP /* undef to save memory */
718#define CONFIG_CMDLINE_EDITING /* Command-line editing */
719#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
720#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
York Sunb5b06fb2012-12-23 19:25:27 +0000721#ifdef CONFIG_CMD_KGDB
722#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
723#else
724#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
725#endif
726#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
727#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
728#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
York Sunb5b06fb2012-12-23 19:25:27 +0000729
730/*
731 * For booting Linux, the board info and command line data
732 * have to be in the first 64 MB of memory, since this is
733 * the maximum mapped by the Linux kernel during initialization.
734 */
735#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/
736#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
737
738#ifdef CONFIG_CMD_KGDB
739#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
740#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
741#endif
742
743/*
744 * Environment Configuration
745 */
746#define CONFIG_ROOTPATH "/opt/nfsroot"
747#define CONFIG_BOOTFILE "uImage"
748#define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/
749
750/* default location for tftp and bootm */
751#define CONFIG_LOADADDR 1000000
752
753#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
754
755#define CONFIG_BAUDRATE 115200
756
757#define __USB_PHY_TYPE ulpi
758
759#define CONFIG_EXTRA_ENV_SETTINGS \
760 "hwconfig=fsl_ddr:ctlr_intlv=null," \
761 "bank_intlv=cs0_cs1;" \
762 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
763 "netdev=eth0\0" \
764 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
765 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
766 "tftpflash=tftpboot $loadaddr $uboot && " \
767 "protect off $ubootaddr +$filesize && " \
768 "erase $ubootaddr +$filesize && " \
769 "cp.b $loadaddr $ubootaddr $filesize && " \
770 "protect on $ubootaddr +$filesize && " \
771 "cmp.b $loadaddr $ubootaddr $filesize\0" \
772 "consoledev=ttyS0\0" \
773 "ramdiskaddr=2000000\0" \
774 "ramdiskfile=b4860qds/ramdisk.uboot\0" \
775 "fdtaddr=c00000\0" \
776 "fdtfile=b4860qds/b4860qds.dtb\0" \
777 "bdev=sda3\0" \
778 "c=ffe\0"
779
780/* For emulation this causes u-boot to jump to the start of the proof point
781 app code automatically */
782#define CONFIG_PROOF_POINTS \
783 "setenv bootargs root=/dev/$bdev rw " \
784 "console=$consoledev,$baudrate $othbootargs;" \
785 "cpu 1 release 0x29000000 - - -;" \
786 "cpu 2 release 0x29000000 - - -;" \
787 "cpu 3 release 0x29000000 - - -;" \
788 "cpu 4 release 0x29000000 - - -;" \
789 "cpu 5 release 0x29000000 - - -;" \
790 "cpu 6 release 0x29000000 - - -;" \
791 "cpu 7 release 0x29000000 - - -;" \
792 "go 0x29000000"
793
794#define CONFIG_HVBOOT \
795 "setenv bootargs config-addr=0x60000000; " \
796 "bootm 0x01000000 - 0x00f00000"
797
798#define CONFIG_ALU \
799 "setenv bootargs root=/dev/$bdev rw " \
800 "console=$consoledev,$baudrate $othbootargs;" \
801 "cpu 1 release 0x01000000 - - -;" \
802 "cpu 2 release 0x01000000 - - -;" \
803 "cpu 3 release 0x01000000 - - -;" \
804 "cpu 4 release 0x01000000 - - -;" \
805 "cpu 5 release 0x01000000 - - -;" \
806 "cpu 6 release 0x01000000 - - -;" \
807 "cpu 7 release 0x01000000 - - -;" \
808 "go 0x01000000"
809
810#define CONFIG_LINUX \
811 "setenv bootargs root=/dev/ram rw " \
812 "console=$consoledev,$baudrate $othbootargs;" \
813 "setenv ramdiskaddr 0x02000000;" \
814 "setenv fdtaddr 0x00c00000;" \
815 "setenv loadaddr 0x1000000;" \
816 "bootm $loadaddr $ramdiskaddr $fdtaddr"
817
818#define CONFIG_HDBOOT \
819 "setenv bootargs root=/dev/$bdev rw " \
820 "console=$consoledev,$baudrate $othbootargs;" \
821 "tftp $loadaddr $bootfile;" \
822 "tftp $fdtaddr $fdtfile;" \
823 "bootm $loadaddr - $fdtaddr"
824
825#define CONFIG_NFSBOOTCOMMAND \
826 "setenv bootargs root=/dev/nfs rw " \
827 "nfsroot=$serverip:$rootpath " \
828 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
829 "console=$consoledev,$baudrate $othbootargs;" \
830 "tftp $loadaddr $bootfile;" \
831 "tftp $fdtaddr $fdtfile;" \
832 "bootm $loadaddr - $fdtaddr"
833
834#define CONFIG_RAMBOOTCOMMAND \
835 "setenv bootargs root=/dev/ram rw " \
836 "console=$consoledev,$baudrate $othbootargs;" \
837 "tftp $ramdiskaddr $ramdiskfile;" \
838 "tftp $loadaddr $bootfile;" \
839 "tftp $fdtaddr $fdtfile;" \
840 "bootm $loadaddr $ramdiskaddr $fdtaddr"
841
842#define CONFIG_BOOTCOMMAND CONFIG_LINUX
843
York Sunb5b06fb2012-12-23 19:25:27 +0000844#include <asm/fsl_secure_boot.h>
York Sunb5b06fb2012-12-23 19:25:27 +0000845
846#endif /* __CONFIG_H */