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stroesea20b27a2004-12-16 18:05:42 +00001/*
2 * (C) Copyright 2001-2004
3 * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
4 *
Stefan Roese98f4a3d2005-09-22 09:04:17 +02005 * (C) Copyright 2005
6 * Stefan Roese, DENX Software Engineering, sr@denx.de.
7 *
Stefan Roese48a05a52006-02-07 16:51:04 +01008 * (C) Copyright 2006
9 * Matthias Fuchs, esd GmbH, matthias.fuchs@esd-electronics.com
10 *
Wolfgang Denk3765b3e2013-10-07 13:07:26 +020011 * SPDX-License-Identifier: GPL-2.0+
stroesea20b27a2004-12-16 18:05:42 +000012 */
13
14/*
15 * board/config.h - configuration options, board specific
16 */
17
18#ifndef __CONFIG_H
19#define __CONFIG_H
20
21/*
22 * High Level Configuration Options
23 * (easy to change)
24 */
25
26#define CONFIG_405EP 1 /* This is a PPC405 CPU */
27#define CONFIG_4xx 1 /* ...member of PPC4xx family */
Wolfgang Denk53677ef2008-05-20 16:00:29 +020028#define CONFIG_HH405 1 /* ...on a HH405 board */
stroesea20b27a2004-12-16 18:05:42 +000029
Wolfgang Denk2ae18242010-10-06 09:05:45 +020030#define CONFIG_SYS_TEXT_BASE 0xFFF80000
31
stroesea20b27a2004-12-16 18:05:42 +000032#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */
33#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */
34
35#define CONFIG_SYS_CLK_FREQ 33333400 /* external frequency to pll */
36
37#define CONFIG_BOARD_TYPES 1 /* support board types */
38
39#define CONFIG_BAUDRATE 9600
40#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */
41
42#undef CONFIG_BOOTARGS
43#undef CONFIG_BOOTCOMMAND
44
45#define CONFIG_PREBOOT "autoupd"
46
Stefan Roese2c7b2ab2005-09-30 16:41:12 +020047#define CONFIG_EXTRA_ENV_SETTINGS \
48 "pciconfighost=1\0" \
49 ""
50
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020051#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
stroesea20b27a2004-12-16 18:05:42 +000052
Ben Warren96e21f82008-10-27 23:50:15 -070053#define CONFIG_PPC4xx_EMAC
Stefan Roese48a05a52006-02-07 16:51:04 +010054#undef CONFIG_HAS_ETH1
55
stroesea20b27a2004-12-16 18:05:42 +000056#define CONFIG_MII 1 /* MII PHY management */
Stefan Roese48a05a52006-02-07 16:51:04 +010057#define CONFIG_PHY_ADDR 0 /* PHY address */
stroesea20b27a2004-12-16 18:05:42 +000058#define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */
Stefan Roese48a05a52006-02-07 16:51:04 +010059#define CONFIG_RESET_PHY_R 1 /* use reset_phy() to disable phy sleep mode */
stroesea20b27a2004-12-16 18:05:42 +000060
61#define CONFIG_PHY_CLK_FREQ EMAC_STACR_CLK_66MHZ /* 66 MHz OPB clock*/
62
Stefan Roese98f4a3d2005-09-22 09:04:17 +020063/*
64 * Video console
65 */
Stefan Roese2c7b2ab2005-09-30 16:41:12 +020066#define CONFIG_VIDEO /* for sm501 video support */
67
68#ifdef CONFIG_VIDEO
Stefan Roese98f4a3d2005-09-22 09:04:17 +020069#define CONFIG_VIDEO_SM501
70#if 0
71#define CONFIG_VIDEO_SM501_32BPP
72#else
73#define CONFIG_VIDEO_SM501_16BPP
74#endif
Stefan Roese48a05a52006-02-07 16:51:04 +010075#define CONFIG_VIDEO_SM501_FBMEM_OFFSET 0x10000
Stefan Roese98f4a3d2005-09-22 09:04:17 +020076#define CONFIG_CFB_CONSOLE
77#define CONFIG_VIDEO_LOGO
78#define CONFIG_VGA_AS_SINGLE_DEVICE
79#define CONFIG_CONSOLE_EXTRA_INFO
80#define CONFIG_VIDEO_SW_CURSOR
81#define CONFIG_SPLASH_SCREEN
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020082#define CONFIG_SYS_CONSOLE_IS_IN_ENV
Stefan Roese98f4a3d2005-09-22 09:04:17 +020083#define CONFIG_SPLASH_SCREEN
84#define CONFIG_VIDEO_BMP_GZIP /* gzip compressed bmp images */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020085#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (2 << 20) /* for decompressed img */
Stefan Roese98f4a3d2005-09-22 09:04:17 +020086
Stefan Roese2c7b2ab2005-09-30 16:41:12 +020087#endif /* CONFIG_VIDEO */
Stefan Roese98f4a3d2005-09-22 09:04:17 +020088
Jon Loeliger11799432007-07-10 09:02:57 -050089
90/*
91 * BOOTP options
92 */
93#define CONFIG_BOOTP_BOOTFILESIZE
94#define CONFIG_BOOTP_BOOTPATH
95#define CONFIG_BOOTP_GATEWAY
96#define CONFIG_BOOTP_HOSTNAME
97
98
Jon Loeliger6c4f4da2007-07-08 10:09:35 -050099/*
100 * Command line configuration.
101 */
102#include <config_cmd_default.h>
103
104#define CONFIG_CMD_DHCP
105#define CONFIG_CMD_PCI
106#define CONFIG_CMD_IRQ
107#define CONFIG_CMD_IDE
108#define CONFIG_CMD_FAT
109#define CONFIG_CMD_EXT2
110#define CONFIG_CMD_ELF
111#define CONFIG_CMD_NAND
112#define CONFIG_CMD_I2C
113#define CONFIG_CMD_DATE
114#define CONFIG_CMD_MII
115#define CONFIG_CMD_PING
Jon Loeliger6c4f4da2007-07-08 10:09:35 -0500116#define CONFIG_CMD_EEPROM
117
Jon Loeliger11799432007-07-10 09:02:57 -0500118#ifdef CONFIG_VIDEO
119#define CONFIG_CMD_BMP
120#endif
stroesea20b27a2004-12-16 18:05:42 +0000121
122#define CONFIG_MAC_PARTITION
123#define CONFIG_DOS_PARTITION
124
125#define CONFIG_SUPPORT_VFAT
126
127#define CONFIG_AUTO_UPDATE 1 /* autoupdate via compactflash */
128#undef CONFIG_AUTO_UPDATE_SHOW /* use board show routine */
129
stroesea20b27a2004-12-16 18:05:42 +0000130#undef CONFIG_BZIP2 /* include support for bzip2 compressed images */
131#undef CONFIG_WATCHDOG /* watchdog disabled */
132
133#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
134
135/*
136 * Miscellaneous configurable options
137 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200138#define CONFIG_SYS_LONGHELP /* undef to save memory */
stroesea20b27a2004-12-16 18:05:42 +0000139
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200140#undef CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
stroesea20b27a2004-12-16 18:05:42 +0000141
Jon Loeliger6c4f4da2007-07-08 10:09:35 -0500142#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200143#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
stroesea20b27a2004-12-16 18:05:42 +0000144#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200145#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
stroesea20b27a2004-12-16 18:05:42 +0000146#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200147#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
148#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
149#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
stroesea20b27a2004-12-16 18:05:42 +0000150
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200151#define CONFIG_SYS_DEVICE_NULLDEV 1 /* include nulldev device */
stroesea20b27a2004-12-16 18:05:42 +0000152
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200153#undef CONFIG_SYS_CONSOLE_INFO_QUIET /* print console @ startup */
stroesea20b27a2004-12-16 18:05:42 +0000154
155#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */
156
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200157#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
158#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
stroesea20b27a2004-12-16 18:05:42 +0000159
Stefan Roese550650d2010-09-20 16:05:31 +0200160#define CONFIG_CONS_INDEX 2 /* Use UART1 */
161#define CONFIG_SYS_NS16550
162#define CONFIG_SYS_NS16550_SERIAL
163#define CONFIG_SYS_NS16550_REG_SIZE 1
164#define CONFIG_SYS_NS16550_CLK get_serial_clock()
165
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200166#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200167#define CONFIG_SYS_BASE_BAUD 691200
stroesea20b27a2004-12-16 18:05:42 +0000168
169/* The following table includes the supported baudrates */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200170#define CONFIG_SYS_BAUDRATE_TABLE \
stroesea20b27a2004-12-16 18:05:42 +0000171 { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \
172 57600, 115200, 230400, 460800, 921600 }
173
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200174#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
175#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */
stroesea20b27a2004-12-16 18:05:42 +0000176
stroesea20b27a2004-12-16 18:05:42 +0000177#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
178
179#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
180
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200181#define CONFIG_SYS_RX_ETH_BUFFER 16 /* use 16 rx buffer on 405 emac */
stroesea20b27a2004-12-16 18:05:42 +0000182
183/*-----------------------------------------------------------------------
Stefan Roese98f4a3d2005-09-22 09:04:17 +0200184 * RTC stuff
185 *-----------------------------------------------------------------------
186 */
187#define CONFIG_RTC_DS1338
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200188#define CONFIG_SYS_I2C_RTC_ADDR 0x68
Stefan Roese98f4a3d2005-09-22 09:04:17 +0200189
190/*-----------------------------------------------------------------------
stroesea20b27a2004-12-16 18:05:42 +0000191 * NAND-FLASH stuff
192 *-----------------------------------------------------------------------
193 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200194#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200195#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
Matthias Fuchsbd84ee42007-07-09 10:10:06 +0200196#define NAND_BIG_DELAY_US 25
stroesea20b27a2004-12-16 18:05:42 +0000197
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200198#define CONFIG_SYS_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */
199#define CONFIG_SYS_NAND_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */
200#define CONFIG_SYS_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */
201#define CONFIG_SYS_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */
stroesea20b27a2004-12-16 18:05:42 +0000202
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200203#define CONFIG_SYS_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */
204#define CONFIG_SYS_NAND_QUIET 1
stroesea20b27a2004-12-16 18:05:42 +0000205
206/*-----------------------------------------------------------------------
207 * PCI stuff
208 *-----------------------------------------------------------------------
209 */
210#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */
211#define PCI_HOST_FORCE 1 /* configure as pci host */
212#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
213
214#define CONFIG_PCI /* include pci support */
Gabor Juhos842033e2013-05-30 07:06:12 +0000215#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
stroesea20b27a2004-12-16 18:05:42 +0000216#define CONFIG_PCI_HOST PCI_HOST_HOST /* select pci host function */
217#define CONFIG_PCI_PNP /* do pci plug-and-play */
218 /* resource configuration */
219
220#define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */
221
222#define CONFIG_PCI_CONFIG_HOST_BRIDGE 1 /* don't skip host bridge config*/
223
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200224#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */
225#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0405 /* PCI Device ID: CPCI-405 */
226#define CONFIG_SYS_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/
227#define CONFIG_SYS_PCI_PTM1LA 0x00000000 /* point to sdram */
228#define CONFIG_SYS_PCI_PTM1MS 0xfc000001 /* 64MB, enable hard-wired to 1 */
229#define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
230#define CONFIG_SYS_PCI_PTM2LA 0xffc00000 /* point to flash */
231#define CONFIG_SYS_PCI_PTM2MS 0xffc00001 /* 4MB, enable */
232#define CONFIG_SYS_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */
stroesea20b27a2004-12-16 18:05:42 +0000233
234/*-----------------------------------------------------------------------
235 * IDE/ATA stuff
236 *-----------------------------------------------------------------------
237 */
238#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */
239#undef CONFIG_IDE_LED /* no led for ide supported */
240#define CONFIG_IDE_RESET 1 /* reset for ide supported */
241
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200242#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE busses */
243#define CONFIG_SYS_IDE_MAXDEVICE (CONFIG_SYS_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */
stroesea20b27a2004-12-16 18:05:42 +0000244
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200245#define CONFIG_SYS_ATA_BASE_ADDR 0xF0100000
246#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
stroesea20b27a2004-12-16 18:05:42 +0000247
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200248#define CONFIG_SYS_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O */
249#define CONFIG_SYS_ATA_REG_OFFSET 0x0000 /* Offset for normal register accesses */
250#define CONFIG_SYS_ATA_ALT_OFFSET 0x0000 /* Offset for alternate registers */
stroesea20b27a2004-12-16 18:05:42 +0000251
252/*
253 * For booting Linux, the board info and command line data
254 * have to be in the first 8 MB of memory, since this is
255 * the maximum mapped by the Linux kernel during initialization.
256 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200257#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
stroesea20b27a2004-12-16 18:05:42 +0000258/*-----------------------------------------------------------------------
259 * FLASH organization
260 */
261#define FLASH_BASE0_PRELIM 0xFFC00000 /* FLASH bank #0 */
262
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200263#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
264#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
stroesea20b27a2004-12-16 18:05:42 +0000265
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200266#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
267#define CONFIG_SYS_FLASH_WRITE_TOUT 1000 /* Timeout for Flash Write (in ms) */
stroesea20b27a2004-12-16 18:05:42 +0000268
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200269#define CONFIG_SYS_FLASH_WORD_SIZE unsigned short /* flash word size (width) */
270#define CONFIG_SYS_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */
271#define CONFIG_SYS_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */
stroesea20b27a2004-12-16 18:05:42 +0000272/*
273 * The following defines are added for buggy IOP480 byte interface.
274 * All other boards should use the standard values (CPCI405 etc.)
275 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200276#define CONFIG_SYS_FLASH_READ0 0x0000 /* 0 is standard */
277#define CONFIG_SYS_FLASH_READ1 0x0001 /* 1 is standard */
278#define CONFIG_SYS_FLASH_READ2 0x0002 /* 2 is standard */
stroesea20b27a2004-12-16 18:05:42 +0000279
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200280#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
stroesea20b27a2004-12-16 18:05:42 +0000281
282#if 0 /* test-only */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200283#define CONFIG_SYS_JFFS2_FIRST_BANK 0 /* use for JFFS2 */
284#define CONFIG_SYS_JFFS2_NUM_BANKS 1 /* ! second bank contains U-Boot */
stroesea20b27a2004-12-16 18:05:42 +0000285#endif
286
287/*-----------------------------------------------------------------------
288 * Start addresses for the final memory configuration
289 * (Set up by the startup code)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200290 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
stroesea20b27a2004-12-16 18:05:42 +0000291 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200292#define CONFIG_SYS_SDRAM_BASE 0x00000000
293#define CONFIG_SYS_FLASH_BASE 0xFFF80000
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200294#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200295#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Monitor */
296#define CONFIG_SYS_MALLOC_LEN (4 << 20) /* Reserve 4 MB for malloc() */
stroesea20b27a2004-12-16 18:05:42 +0000297
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200298#if (CONFIG_SYS_MONITOR_BASE < FLASH_BASE0_PRELIM)
299# define CONFIG_SYS_RAMBOOT 1
stroesea20b27a2004-12-16 18:05:42 +0000300#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200301# undef CONFIG_SYS_RAMBOOT
stroesea20b27a2004-12-16 18:05:42 +0000302#endif
303
304/*-----------------------------------------------------------------------
305 * Environment Variable setup
306 */
Jean-Christophe PLAGNIOL-VILLARDbb1f8b42008-09-05 09:19:30 +0200307#define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200308#define CONFIG_ENV_OFFSET 0x100 /* environment starts at the beginning of the EEPROM */
309#define CONFIG_ENV_SIZE 0x700 /* 2048 bytes may be used for env vars*/
stroesea20b27a2004-12-16 18:05:42 +0000310 /* total size of a CAT24WC16 is 2048 bytes */
311
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200312#define CONFIG_SYS_NVRAM_BASE_ADDR 0xF4080000 /* NVRAM base address */
313#define CONFIG_SYS_NVRAM_SIZE 0x8000 /* NVRAM size */
stroesea20b27a2004-12-16 18:05:42 +0000314
315/*-----------------------------------------------------------------------
316 * I2C EEPROM (CAT24WC16) for environment
317 */
Dirk Eibach880540d2013-04-25 02:40:01 +0000318#define CONFIG_SYS_I2C
319#define CONFIG_SYS_I2C_PPC4XX
320#define CONFIG_SYS_I2C_PPC4XX_CH0
stroesea20b27a2004-12-16 18:05:42 +0000321#if 0 /* test-only */
Dirk Eibach880540d2013-04-25 02:40:01 +0000322#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000
stroesea20b27a2004-12-16 18:05:42 +0000323#else
Dirk Eibach880540d2013-04-25 02:40:01 +0000324#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 100000
stroesea20b27a2004-12-16 18:05:42 +0000325#endif
Dirk Eibach880540d2013-04-25 02:40:01 +0000326#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F
stroesea20b27a2004-12-16 18:05:42 +0000327
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200328#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT24WC08 */
329#define CONFIG_SYS_EEPROM_WREN 1
Stefan Roese98f4a3d2005-09-22 09:04:17 +0200330
stroesea20b27a2004-12-16 18:05:42 +0000331#if 1 /* test-only */
332/* CAT24WC08/16... */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200333#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
stroesea20b27a2004-12-16 18:05:42 +0000334/* mask of address bits that overflow into the "EEPROM chip address" */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200335#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07
336#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */
stroesea20b27a2004-12-16 18:05:42 +0000337 /* 16 byte page write mode using*/
338 /* last 4 bits of the address */
339#else
340/* CAT24WC32/64... */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200341#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* Bytes of address */
stroesea20b27a2004-12-16 18:05:42 +0000342/* mask of address bits that overflow into the "EEPROM chip address" */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200343#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x01
344#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 /* The Catalyst CAT24WC32 has */
stroesea20b27a2004-12-16 18:05:42 +0000345 /* 32 byte page write mode using*/
346 /* last 5 bits of the address */
347#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200348#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
stroesea20b27a2004-12-16 18:05:42 +0000349
350/*-----------------------------------------------------------------------
stroesea20b27a2004-12-16 18:05:42 +0000351 * External Bus Controller (EBC) Setup
352 */
353
354#define CAN_BA 0xF0000000 /* CAN Base Address */
355#define LCD_BA 0xF1000000 /* Epson LCD Base Address */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200356#define CONFIG_SYS_NAND_BASE 0xF4000000 /* NAND FLASH Base Address */
357#define CONFIG_SYS_NVRAM_BASE 0xF4080000 /* NVRAM Base Address */
stroesea20b27a2004-12-16 18:05:42 +0000358
359/* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200360#define CONFIG_SYS_EBC_PB0AP 0x92015480
361#define CONFIG_SYS_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
stroesea20b27a2004-12-16 18:05:42 +0000362
363/* Memory Bank 1 (Flash Bank 1, NAND-FLASH & NVRAM) initialization */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200364#define CONFIG_SYS_EBC_PB1AP 0x92015480
365#define CONFIG_SYS_EBC_PB1CR 0xF4018000 /* BAS=0xF40,BS=1MB,BU=R/W,BW=8bit */
stroesea20b27a2004-12-16 18:05:42 +0000366
367/* Memory Bank 2 (8 Bit Peripheral: CAN, UART, RTC) initialization */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200368#define CONFIG_SYS_EBC_PB2AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
369#define CONFIG_SYS_EBC_PB2CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */
stroesea20b27a2004-12-16 18:05:42 +0000370
371/* Memory Bank 3 (16 Bit Peripheral: FPGA internal, dig. IO) initialization */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200372#define CONFIG_SYS_EBC_PB3AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
373#define CONFIG_SYS_EBC_PB3CR 0xF011A000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */
stroesea20b27a2004-12-16 18:05:42 +0000374
375/* Memory Bank 4 (Epson LCD) initialization */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200376#define CONFIG_SYS_EBC_PB4AP 0x03805380 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=0 */
377#define CONFIG_SYS_EBC_PB4CR LCD_BA | 0x7A000 /* BAS=0xF10,BS=8MB,BU=R/W,BW=16bit */
stroesea20b27a2004-12-16 18:05:42 +0000378
379/*-----------------------------------------------------------------------
380 * LCD Setup
381 */
382
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200383#define CONFIG_SYS_LCD_BIG_MEM 0xF1200000 /* Epson S1D13806 Mem Base Address */
384#define CONFIG_SYS_LCD_BIG_REG 0xF1000000 /* Epson S1D13806 Reg Base Address */
385#define CONFIG_SYS_LCD_SMALL_MEM 0xF1400000 /* Epson S1D13704 Mem Base Address */
386#define CONFIG_SYS_LCD_SMALL_REG 0xF140FFE0 /* Epson S1D13704 Reg Base Address */
stroesea20b27a2004-12-16 18:05:42 +0000387
stroesea20b27a2004-12-16 18:05:42 +0000388/*-----------------------------------------------------------------------
389 * Universal Interrupt Controller (UIC) Setup
390 */
391
392/*
393 * define UIC_EXT0 ... UIC_EXT6 if external interrupt is active high
394 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200395#define CONFIG_SYS_UIC0_POLARITY (0xFFFFFF80 | UIC_MASK(VECNUM_EIRQ6))
stroesea20b27a2004-12-16 18:05:42 +0000396
397/*-----------------------------------------------------------------------
398 * FPGA stuff
399 */
400
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200401#define CONFIG_SYS_FPGA_BASE_ADDR 0xF0100100 /* FPGA internal Base Address */
stroesea20b27a2004-12-16 18:05:42 +0000402
stroesea20b27a2004-12-16 18:05:42 +0000403#define LCD_CLK_OFF 0x0000 /* Off */
404#define LCD_CLK_02083 0x1000 /* 2.083 MHz */
405#define LCD_CLK_03135 0x2000 /* 3.135 MHz */
406#define LCD_CLK_04165 0x3000 /* 4.165 MHz */
407#define LCD_CLK_06250 0x4000 /* 6.250 MHz */
408#define LCD_CLK_08330 0x5000 /* 8.330 MHz */
409#define LCD_CLK_12500 0x6000 /* 12.50 MHz */
410#define LCD_CLK_25000 0x7000 /* 25.00 MHz */
411
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200412#define CONFIG_SYS_FPGA_SPARTAN2 1 /* using Xilinx Spartan 2 now */
413#define CONFIG_SYS_FPGA_MAX_SIZE 128*1024 /* 128kByte is enough for XC2S50E*/
stroesea20b27a2004-12-16 18:05:42 +0000414
415/* FPGA program pin configuration */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200416#define CONFIG_SYS_FPGA_PRG 0x04000000 /* FPGA program pin (ppc output) */
417#define CONFIG_SYS_FPGA_CLK 0x02000000 /* FPGA clk pin (ppc output) */
418#define CONFIG_SYS_FPGA_DATA 0x01000000 /* FPGA data pin (ppc output) */
419#define CONFIG_SYS_FPGA_INIT 0x00010000 /* FPGA init pin (ppc input) */
420#define CONFIG_SYS_FPGA_DONE 0x00008000 /* FPGA done pin (ppc input) */
stroesea20b27a2004-12-16 18:05:42 +0000421
422/*-----------------------------------------------------------------------
423 * Definitions for initial stack pointer and data area (in data cache)
424 */
425/* use on chip memory ( OCM ) for temperary stack until sdram is tested */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200426#define CONFIG_SYS_TEMP_STACK_OCM 1
stroesea20b27a2004-12-16 18:05:42 +0000427
428/* On Chip Memory location */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200429#define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000
430#define CONFIG_SYS_OCM_DATA_SIZE 0x1000
431#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM */
Wolfgang Denk553f0982010-10-26 13:32:32 +0200432#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM */
stroesea20b27a2004-12-16 18:05:42 +0000433
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200434#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200435#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
stroesea20b27a2004-12-16 18:05:42 +0000436
437/*-----------------------------------------------------------------------
438 * Definitions for GPIO setup (PPC405EP specific)
439 *
440 * GPIO0[0] - External Bus Controller BLAST output
441 * GPIO0[1-9] - Instruction trace outputs -> GPIO
442 * GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs
443 * GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs -> GPIO
444 * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs
445 * GPIO0[24-27] - UART0 control signal inputs/outputs
446 * GPIO0[28-29] - UART1 data signal input/output
447 * GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs
448 */
Stefan Roeseafabb492010-09-12 06:21:37 +0200449#define CONFIG_SYS_GPIO0_OSRL 0x40000550
450#define CONFIG_SYS_GPIO0_OSRH 0x00000110
451#define CONFIG_SYS_GPIO0_ISR1L 0x00000000
452#define CONFIG_SYS_GPIO0_ISR1H 0x15555440
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200453#define CONFIG_SYS_GPIO0_TSRL 0x00000000
Stefan Roeseafabb492010-09-12 06:21:37 +0200454#define CONFIG_SYS_GPIO0_TSRH 0x00000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200455#define CONFIG_SYS_GPIO0_TCR 0xF7FE0017
stroesea20b27a2004-12-16 18:05:42 +0000456
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200457#define CONFIG_SYS_LCD_ENDIAN (0x80000000 >> 7)
458#define CONFIG_SYS_EEPROM_WP (0x80000000 >> 8) /* GPIO8 */
459#define CONFIG_SYS_TOUCH_RST (0x80000000 >> 9) /* GPIO9 */
460#define CONFIG_SYS_LCD0_RST (0x80000000 >> 30)
461#define CONFIG_SYS_LCD1_RST (0x80000000 >> 31)
stroesea20b27a2004-12-16 18:05:42 +0000462
463/*
stroesea20b27a2004-12-16 18:05:42 +0000464 * Default speed selection (cpu_plb_opb_ebc) in mhz.
465 * This value will be set if iic boot eprom is disabled.
466 */
467#if 0
468#define PLLMR0_DEFAULT PLLMR0_266_133_66_33
469#define PLLMR1_DEFAULT PLLMR1_266_133_66_33
470#endif
471#if 0
472#define PLLMR0_DEFAULT PLLMR0_200_100_50_33
473#define PLLMR1_DEFAULT PLLMR1_200_100_50_33
474#endif
475#if 1
476#define PLLMR0_DEFAULT PLLMR0_133_66_66_33
477#define PLLMR1_DEFAULT PLLMR1_133_66_66_33
478#endif
479
480#endif /* __CONFIG_H */