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Marian Balakowicz991425f2006-03-14 16:24:38 +01001/*
2 * (C) Copyright 2006
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/*
25 * mpc8349emds board configuration file
26 *
27 */
28
29#ifndef __CONFIG_H
30#define __CONFIG_H
31
Marian Balakowicz991425f2006-03-14 16:24:38 +010032#undef DEBUG
33
34/*
35 * High Level Configuration Options
36 */
37#define CONFIG_E300 1 /* E300 Family */
Kim Phillipsbf0b5422006-11-01 00:10:40 -060038#define CONFIG_MPC83XX 1 /* MPC83XX family */
Ben Warrenb24f1192006-09-07 16:51:04 -040039#define CONFIG_MPC834X 1 /* MPC834X family */
Marian Balakowicz991425f2006-03-14 16:24:38 +010040#define CONFIG_MPC8349 1 /* MPC8349 specific */
41#define CONFIG_MPC8349EMDS 1 /* MPC8349EMDS board specific */
42
Wolfgang Denk977b50f2006-05-10 17:43:20 +020043#undef CONFIG_PCI
Kumar Gala8fe9bf62006-04-20 13:45:32 -050044#undef CONFIG_MPC83XX_PCI2 /* support for 2nd PCI controller */
Marian Balakowicz991425f2006-03-14 16:24:38 +010045
46#define PCI_66M
47#ifdef PCI_66M
48#define CONFIG_83XX_CLKIN 66000000 /* in Hz */
49#else
50#define CONFIG_83XX_CLKIN 33000000 /* in Hz */
51#endif
52
53#ifndef CONFIG_SYS_CLK_FREQ
54#ifdef PCI_66M
55#define CONFIG_SYS_CLK_FREQ 66000000
Kumar Gala8fe9bf62006-04-20 13:45:32 -050056#define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_4X1
Marian Balakowicz991425f2006-03-14 16:24:38 +010057#else
58#define CONFIG_SYS_CLK_FREQ 33000000
Kumar Gala8fe9bf62006-04-20 13:45:32 -050059#define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_8X1
Marian Balakowicz991425f2006-03-14 16:24:38 +010060#endif
61#endif
62
63#define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */
64
Timur Tabid239d742006-11-03 12:00:28 -060065#define CFG_IMMR 0xE0000000
Marian Balakowicz991425f2006-03-14 16:24:38 +010066
67#undef CFG_DRAM_TEST /* memory test, takes time */
68#define CFG_MEMTEST_START 0x00000000 /* memtest region */
69#define CFG_MEMTEST_END 0x00100000
70
71/*
72 * DDR Setup
73 */
Xie Xiaobo8d172c02007-02-14 18:26:44 +080074#define CONFIG_DDR_ECC /* support DDR ECC function */
Marian Balakowiczd326f4a2006-03-16 15:19:35 +010075#define CONFIG_DDR_ECC_CMD /* use DDR ECC user commands */
Marian Balakowicz991425f2006-03-14 16:24:38 +010076#define CONFIG_SPD_EEPROM /* use SPD EEPROM for DDR setup*/
77
Rafal Jaworowskidc9e4992006-03-16 17:46:46 +010078/*
79 * 32-bit data path mode.
Wolfgang Denkcf48eb92006-04-16 10:51:58 +020080 *
Rafal Jaworowskidc9e4992006-03-16 17:46:46 +010081 * Please note that using this mode for devices with the real density of 64-bit
82 * effectively reduces the amount of available memory due to the effect of
83 * wrapping around while translating address to row/columns, for example in the
84 * 256MB module the upper 128MB get aliased with contents of the lower
85 * 128MB); normally this define should be used for devices with real 32-bit
Wolfgang Denkcf48eb92006-04-16 10:51:58 +020086 * data path.
Rafal Jaworowskidc9e4992006-03-16 17:46:46 +010087 */
88#undef CONFIG_DDR_32BIT
89
Marian Balakowicz991425f2006-03-14 16:24:38 +010090#define CFG_DDR_BASE 0x00000000 /* DDR is system memory*/
91#define CFG_SDRAM_BASE CFG_DDR_BASE
92#define CFG_DDR_SDRAM_BASE CFG_DDR_BASE
Xie Xiaobo8d172c02007-02-14 18:26:44 +080093#define CFG_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \
94 DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
Marian Balakowicz991425f2006-03-14 16:24:38 +010095#undef CONFIG_DDR_2T_TIMING
96
Xie Xiaobo8d172c02007-02-14 18:26:44 +080097/*
98 * DDRCDR - DDR Control Driver Register
99 */
100#define CFG_DDRCDR_VALUE 0x80080001
101
Marian Balakowicz991425f2006-03-14 16:24:38 +0100102#if defined(CONFIG_SPD_EEPROM)
Rafal Jaworowskidc9e4992006-03-16 17:46:46 +0100103/*
104 * Determine DDR configuration from I2C interface.
105 */
106#define SPD_EEPROM_ADDRESS 0x51 /* DDR DIMM */
Marian Balakowicz991425f2006-03-14 16:24:38 +0100107#else
Rafal Jaworowskidc9e4992006-03-16 17:46:46 +0100108/*
109 * Manually set up DDR parameters
110 */
111#define CFG_DDR_SIZE 256 /* MB */
Xie Xiaobo8d172c02007-02-14 18:26:44 +0800112#if defined(CONFIG_DDR_II)
113#define CFG_DDRCDR 0x80080001
114#define CFG_DDR_CS2_BNDS 0x0000000f
115#define CFG_DDR_CS2_CONFIG 0x80330102
116#define CFG_DDR_TIMING_0 0x00220802
117#define CFG_DDR_TIMING_1 0x38357322
118#define CFG_DDR_TIMING_2 0x2f9048c8
119#define CFG_DDR_TIMING_3 0x00000000
120#define CFG_DDR_CLK_CNTL 0x02000000
121#define CFG_DDR_MODE 0x47d00432
122#define CFG_DDR_MODE2 0x8000c000
123#define CFG_DDR_INTERVAL 0x03cf0080
124#define CFG_DDR_SDRAM_CFG 0x43000000
125#define CFG_DDR_SDRAM_CFG2 0x00401000
126#else
Rafal Jaworowskidc9e4992006-03-16 17:46:46 +0100127#define CFG_DDR_CONFIG (CSCONFIG_EN | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10)
128#define CFG_DDR_TIMING_1 0x36332321
129#define CFG_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */
130#define CFG_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */
131#define CFG_DDR_INTERVAL 0x04060100 /* autocharge,no open page */
132
133#if defined(CONFIG_DDR_32BIT)
134/* set burst length to 8 for 32-bit data path */
135#define CFG_DDR_MODE 0x00000023 /* DLL,normal,seq,4/2.5, 8 burst len */
136#else
137/* the default burst length is 4 - for 64-bit data path */
138#define CFG_DDR_MODE 0x00000022 /* DLL,normal,seq,4/2.5, 4 burst len */
139#endif
Marian Balakowicz991425f2006-03-14 16:24:38 +0100140#endif
Xie Xiaobo8d172c02007-02-14 18:26:44 +0800141#endif
Marian Balakowicz991425f2006-03-14 16:24:38 +0100142
143/*
144 * SDRAM on the Local Bus
145 */
146#define CFG_LBC_SDRAM_BASE 0xF0000000 /* Localbus SDRAM */
147#define CFG_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */
148
149/*
150 * FLASH on the Local Bus
151 */
152#define CFG_FLASH_CFI /* use the Common Flash Interface */
153#define CFG_FLASH_CFI_DRIVER /* use the CFI driver */
154#define CFG_FLASH_BASE 0xFE000000 /* start of FLASH */
Xie Xiaobo8d172c02007-02-14 18:26:44 +0800155#define CFG_FLASH_SIZE 32 /* max flash size in MB */
Marian Balakowicz991425f2006-03-14 16:24:38 +0100156/* #define CFG_FLASH_USE_BUFFER_WRITE */
157
158#define CFG_BR0_PRELIM (CFG_FLASH_BASE | /* flash Base address */ \
Xie Xiaobo8d172c02007-02-14 18:26:44 +0800159 (2 << BR_PS_SHIFT) | /* 16 bit port size */ \
Marian Balakowicz991425f2006-03-14 16:24:38 +0100160 BR_V) /* valid */
Xie Xiaobo8d172c02007-02-14 18:26:44 +0800161#define CFG_OR0_PRELIM ((~(CFG_FLASH_SIZE - 1) << 20) | OR_UPM_XAM | \
162 OR_GPCM_CSNT | OR_GPCM_ACS_0b11 | OR_GPCM_XACS | OR_GPCM_SCY_15 | \
163 OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD)
Marian Balakowicz991425f2006-03-14 16:24:38 +0100164#define CFG_LBLAWBAR0_PRELIM CFG_FLASH_BASE /* window base at flash base */
Xie Xiaobo8d172c02007-02-14 18:26:44 +0800165#define CFG_LBLAWAR0_PRELIM 0x80000018 /* 32 MB window size */
Marian Balakowicz991425f2006-03-14 16:24:38 +0100166
167#define CFG_MAX_FLASH_BANKS 1 /* number of banks */
Xie Xiaobo8d172c02007-02-14 18:26:44 +0800168#define CFG_MAX_FLASH_SECT 256 /* max sectors per device */
Marian Balakowicz991425f2006-03-14 16:24:38 +0100169
170#undef CFG_FLASH_CHECKSUM
171#define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
172#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
173
174#define CFG_MID_FLASH_JUMP 0x7F000000
175#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */
176
177#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
178#define CFG_RAMBOOT
179#else
180#undef CFG_RAMBOOT
181#endif
182
183/*
184 * BCSR register on local bus 32KB, 8-bit wide for MDS config reg
185 */
Kumar Gala8fe9bf62006-04-20 13:45:32 -0500186#define CFG_BCSR 0xE2400000
Marian Balakowicz991425f2006-03-14 16:24:38 +0100187#define CFG_LBLAWBAR1_PRELIM CFG_BCSR /* Access window base at BCSR base */
188#define CFG_LBLAWAR1_PRELIM 0x8000000E /* Access window size 32K */
189#define CFG_BR1_PRELIM (CFG_BCSR|0x00000801) /* Port-size=8bit, MSEL=GPCM */
190#define CFG_OR1_PRELIM 0xFFFFE8F0 /* length 32K */
191
192#define CONFIG_L1_INIT_RAM
193#define CFG_INIT_RAM_LOCK 1
Kumar Gala8fe9bf62006-04-20 13:45:32 -0500194#define CFG_INIT_RAM_ADDR 0xFD000000 /* Initial RAM address */
Marian Balakowicz991425f2006-03-14 16:24:38 +0100195#define CFG_INIT_RAM_END 0x1000 /* End of used area in RAM*/
196
197#define CFG_GBL_DATA_SIZE 0x100 /* num bytes initial data */
198#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
199#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
200
201#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
202#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
203
204/*
205 * Local Bus LCRR and LBCR regs
206 * LCRR: DLL bypass, Clock divider is 4
207 * External Local Bus rate is
208 * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV
209 */
210#define CFG_LCRR (LCRR_DBYP | LCRR_CLKDIV_4)
211#define CFG_LBC_LBCR 0x00000000
212
Xie Xiaobo8d172c02007-02-14 18:26:44 +0800213/*
214 * The MPC834xEA MDS for 834xE rev3.1 may not be assembled SDRAM memory.
215 * if board has SRDAM on local bus, you can define CFG_LB_SDRAM
216 */
217#undef CFG_LB_SDRAM
Marian Balakowicz991425f2006-03-14 16:24:38 +0100218
219#ifdef CFG_LB_SDRAM
220/* Local bus BR2, OR2 definition for SDRAM if soldered on the MDS board */
221/*
222 * Base Register 2 and Option Register 2 configure SDRAM.
223 * The SDRAM base address, CFG_LBC_SDRAM_BASE, is 0xf0000000.
224 *
225 * For BR2, need:
226 * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
227 * port-size = 32-bits = BR2[19:20] = 11
228 * no parity checking = BR2[21:22] = 00
229 * SDRAM for MSEL = BR2[24:26] = 011
230 * Valid = BR[31] = 1
231 *
232 * 0 4 8 12 16 20 24 28
233 * 1111 0000 0000 0000 0001 1000 0110 0001 = F0001861
234 *
235 * FIXME: CFG_LBC_SDRAM_BASE should be masked and OR'ed into
236 * FIXME: the top 17 bits of BR2.
237 */
238
239#define CFG_BR2_PRELIM 0xF0001861 /* Port-size=32bit, MSEL=SDRAM */
240#define CFG_LBLAWBAR2_PRELIM 0xF0000000
241#define CFG_LBLAWAR2_PRELIM 0x80000019 /* 64M */
242
243/*
244 * The SDRAM size in MB, CFG_LBC_SDRAM_SIZE, is 64.
245 *
246 * For OR2, need:
247 * 64MB mask for AM, OR2[0:7] = 1111 1100
248 * XAM, OR2[17:18] = 11
249 * 9 columns OR2[19-21] = 010
250 * 13 rows OR2[23-25] = 100
251 * EAD set for extra time OR[31] = 1
252 *
253 * 0 4 8 12 16 20 24 28
254 * 1111 1100 0000 0000 0110 1001 0000 0001 = FC006901
255 */
256
257#define CFG_OR2_PRELIM 0xFC006901
258
259#define CFG_LBC_LSRT 0x32000000 /* LB sdram refresh timer, about 6us */
260#define CFG_LBC_MRTPR 0x20000000 /* LB refresh timer prescal, 266MHz/32 */
261
262/*
263 * LSDMR masks
264 */
265#define CFG_LBC_LSDMR_RFEN (1 << (31 - 1))
266#define CFG_LBC_LSDMR_BSMA1516 (3 << (31 - 10))
267#define CFG_LBC_LSDMR_BSMA1617 (4 << (31 - 10))
268#define CFG_LBC_LSDMR_RFCR5 (3 << (31 - 16))
269#define CFG_LBC_LSDMR_RFCR8 (5 << (31 - 16))
270#define CFG_LBC_LSDMR_RFCR16 (7 << (31 - 16))
271#define CFG_LBC_LSDMR_PRETOACT3 (3 << (31 - 19))
272#define CFG_LBC_LSDMR_PRETOACT6 (5 << (31 - 19))
273#define CFG_LBC_LSDMR_PRETOACT7 (7 << (31 - 19))
274#define CFG_LBC_LSDMR_ACTTORW3 (3 << (31 - 22))
275#define CFG_LBC_LSDMR_ACTTORW7 (7 << (31 - 22))
276#define CFG_LBC_LSDMR_ACTTORW6 (6 << (31 - 22))
277#define CFG_LBC_LSDMR_BL8 (1 << (31 - 23))
278#define CFG_LBC_LSDMR_WRC2 (2 << (31 - 27))
279#define CFG_LBC_LSDMR_WRC3 (3 << (31 - 27))
280#define CFG_LBC_LSDMR_WRC4 (0 << (31 - 27))
281#define CFG_LBC_LSDMR_BUFCMD (1 << (31 - 29))
282#define CFG_LBC_LSDMR_CL3 (3 << (31 - 31))
283
284#define CFG_LBC_LSDMR_OP_NORMAL (0 << (31 - 4))
285#define CFG_LBC_LSDMR_OP_ARFRSH (1 << (31 - 4))
286#define CFG_LBC_LSDMR_OP_SRFRSH (2 << (31 - 4))
287#define CFG_LBC_LSDMR_OP_MRW (3 << (31 - 4))
288#define CFG_LBC_LSDMR_OP_PRECH (4 << (31 - 4))
289#define CFG_LBC_LSDMR_OP_PCHALL (5 << (31 - 4))
290#define CFG_LBC_LSDMR_OP_ACTBNK (6 << (31 - 4))
291#define CFG_LBC_LSDMR_OP_RWINV (7 << (31 - 4))
292
293#define CFG_LBC_LSDMR_COMMON ( CFG_LBC_LSDMR_RFEN \
294 | CFG_LBC_LSDMR_BSMA1516 \
295 | CFG_LBC_LSDMR_RFCR8 \
296 | CFG_LBC_LSDMR_PRETOACT6 \
297 | CFG_LBC_LSDMR_ACTTORW3 \
298 | CFG_LBC_LSDMR_BL8 \
299 | CFG_LBC_LSDMR_WRC3 \
300 | CFG_LBC_LSDMR_CL3 \
301 )
302
303/*
304 * SDRAM Controller configuration sequence.
305 */
306#define CFG_LBC_LSDMR_1 ( CFG_LBC_LSDMR_COMMON \
307 | CFG_LBC_LSDMR_OP_PCHALL)
308#define CFG_LBC_LSDMR_2 ( CFG_LBC_LSDMR_COMMON \
309 | CFG_LBC_LSDMR_OP_ARFRSH)
310#define CFG_LBC_LSDMR_3 ( CFG_LBC_LSDMR_COMMON \
311 | CFG_LBC_LSDMR_OP_ARFRSH)
312#define CFG_LBC_LSDMR_4 ( CFG_LBC_LSDMR_COMMON \
313 | CFG_LBC_LSDMR_OP_MRW)
314#define CFG_LBC_LSDMR_5 ( CFG_LBC_LSDMR_COMMON \
315 | CFG_LBC_LSDMR_OP_NORMAL)
316#endif
317
318/*
319 * Serial Port
320 */
321#define CONFIG_CONS_INDEX 1
322#undef CONFIG_SERIAL_SOFTWARE_FIFO
323#define CFG_NS16550
324#define CFG_NS16550_SERIAL
325#define CFG_NS16550_REG_SIZE 1
326#define CFG_NS16550_CLK get_bus_freq(0)
327
328#define CFG_BAUDRATE_TABLE \
329 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
330
Timur Tabid239d742006-11-03 12:00:28 -0600331#define CFG_NS16550_COM1 (CFG_IMMR+0x4500)
332#define CFG_NS16550_COM2 (CFG_IMMR+0x4600)
Marian Balakowicz991425f2006-03-14 16:24:38 +0100333
Kim Phillips22d71a72007-02-27 18:41:08 -0600334#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
Marian Balakowicz991425f2006-03-14 16:24:38 +0100335/* Use the HUSH parser */
336#define CFG_HUSH_PARSER
337#ifdef CFG_HUSH_PARSER
338#define CFG_PROMPT_HUSH_PS2 "> "
339#endif
340
Kim Phillipsbf0b5422006-11-01 00:10:40 -0600341/* pass open firmware flat tree */
Kim Phillips35cc4e42007-08-15 22:30:39 -0500342#define CONFIG_OF_LIBFDT 1
Kim Phillipsbf0b5422006-11-01 00:10:40 -0600343#define CONFIG_OF_BOARD_SETUP 1
Kim Phillips5b8bc602007-12-20 14:09:22 -0600344#define CONFIG_OF_STDOUT_VIA_ALIAS 1
Kim Phillipsbf0b5422006-11-01 00:10:40 -0600345
Marian Balakowicz991425f2006-03-14 16:24:38 +0100346/* I2C */
347#define CONFIG_HARD_I2C /* I2C with hardware support*/
348#undef CONFIG_SOFT_I2C /* I2C bit-banged */
Timur Tabibe5e6182006-11-03 19:15:00 -0600349#define CONFIG_FSL_I2C
Ben Warrenb24f1192006-09-07 16:51:04 -0400350#define CONFIG_I2C_MULTI_BUS
351#define CONFIG_I2C_CMD_TREE
Marian Balakowicz991425f2006-03-14 16:24:38 +0100352#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
353#define CFG_I2C_SLAVE 0x7F
Ben Warrenb24f1192006-09-07 16:51:04 -0400354#define CFG_I2C_NOPROBES {{0,0x69}} /* Don't probe these addrs */
Marian Balakowicz991425f2006-03-14 16:24:38 +0100355#define CFG_I2C_OFFSET 0x3000
356#define CFG_I2C2_OFFSET 0x3100
357
Ben Warren80ddd222008-01-16 22:37:42 -0500358/* SPI */
Kim Phillips2956acd2008-01-17 12:48:00 -0600359#define CONFIG_HARD_SPI /* SPI with hardware support */
Ben Warren80ddd222008-01-16 22:37:42 -0500360#undef CONFIG_SOFT_SPI /* SPI bit-banged */
Ben Warren80ddd222008-01-16 22:37:42 -0500361
362/* GPIOs. Used as SPI chip selects */
363#define CFG_GPIO1_PRELIM
364#define CFG_GPIO1_DIR 0xC0000000 /* SPI CS on 0, LED on 1 */
365#define CFG_GPIO1_DAT 0xC0000000 /* Both are active LOW */
366
Marian Balakowicz991425f2006-03-14 16:24:38 +0100367/* TSEC */
368#define CFG_TSEC1_OFFSET 0x24000
Timur Tabid239d742006-11-03 12:00:28 -0600369#define CFG_TSEC1 (CFG_IMMR+CFG_TSEC1_OFFSET)
Marian Balakowicz991425f2006-03-14 16:24:38 +0100370#define CFG_TSEC2_OFFSET 0x25000
Timur Tabid239d742006-11-03 12:00:28 -0600371#define CFG_TSEC2 (CFG_IMMR+CFG_TSEC2_OFFSET)
Marian Balakowicz991425f2006-03-14 16:24:38 +0100372
Kumar Gala8fe9bf62006-04-20 13:45:32 -0500373/* USB */
374#define CFG_USE_MPC834XSYS_USB_PHY 1 /* Use SYS board PHY */
Marian Balakowicz991425f2006-03-14 16:24:38 +0100375
376/*
377 * General PCI
378 * Addresses are mapped 1-1.
379 */
380#define CFG_PCI1_MEM_BASE 0x80000000
381#define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE
Kumar Gala8fe9bf62006-04-20 13:45:32 -0500382#define CFG_PCI1_MEM_SIZE 0x10000000 /* 256M */
383#define CFG_PCI1_MMIO_BASE 0x90000000
384#define CFG_PCI1_MMIO_PHYS CFG_PCI1_MMIO_BASE
385#define CFG_PCI1_MMIO_SIZE 0x10000000 /* 256M */
Marian Balakowicz991425f2006-03-14 16:24:38 +0100386#define CFG_PCI1_IO_BASE 0x00000000
Kumar Gala8fe9bf62006-04-20 13:45:32 -0500387#define CFG_PCI1_IO_PHYS 0xE2000000
388#define CFG_PCI1_IO_SIZE 0x00100000 /* 1M */
Marian Balakowicz991425f2006-03-14 16:24:38 +0100389
390#define CFG_PCI2_MEM_BASE 0xA0000000
391#define CFG_PCI2_MEM_PHYS CFG_PCI2_MEM_BASE
Kumar Gala8fe9bf62006-04-20 13:45:32 -0500392#define CFG_PCI2_MEM_SIZE 0x10000000 /* 256M */
393#define CFG_PCI2_MMIO_BASE 0xB0000000
394#define CFG_PCI2_MMIO_PHYS CFG_PCI2_MMIO_BASE
395#define CFG_PCI2_MMIO_SIZE 0x10000000 /* 256M */
Marian Balakowicz991425f2006-03-14 16:24:38 +0100396#define CFG_PCI2_IO_BASE 0x00000000
Kumar Gala8fe9bf62006-04-20 13:45:32 -0500397#define CFG_PCI2_IO_PHYS 0xE2100000
398#define CFG_PCI2_IO_SIZE 0x00100000 /* 1M */
Marian Balakowicz991425f2006-03-14 16:24:38 +0100399
400#if defined(CONFIG_PCI)
401
Kumar Gala8fe9bf62006-04-20 13:45:32 -0500402#define PCI_ONE_PCI1
Marian Balakowicz991425f2006-03-14 16:24:38 +0100403#if defined(PCI_64BIT)
404#undef PCI_ALL_PCI1
405#undef PCI_TWO_PCI1
406#undef PCI_ONE_PCI1
407#endif
408
409#define CONFIG_NET_MULTI
410#define CONFIG_PCI_PNP /* do pci plug-and-play */
411
412#undef CONFIG_EEPRO100
413#undef CONFIG_TULIP
414
415#if !defined(CONFIG_PCI_PNP)
416 #define PCI_ENET0_IOADDR 0xFIXME
417 #define PCI_ENET0_MEMADDR 0xFIXME
418 #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */
419#endif
420
421#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
422#define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
423
424#endif /* CONFIG_PCI */
425
426/*
427 * TSEC configuration
428 */
429#define CONFIG_TSEC_ENET /* TSEC ethernet support */
430
431#if defined(CONFIG_TSEC_ENET)
432#ifndef CONFIG_NET_MULTI
433#define CONFIG_NET_MULTI 1
434#endif
435
436#define CONFIG_GMII 1 /* MII PHY management */
Kim Phillips255a35772007-05-16 16:52:19 -0500437#define CONFIG_TSEC1 1
438#define CONFIG_TSEC1_NAME "TSEC0"
439#define CONFIG_TSEC2 1
440#define CONFIG_TSEC2_NAME "TSEC1"
Marian Balakowicz991425f2006-03-14 16:24:38 +0100441#define TSEC1_PHY_ADDR 0
442#define TSEC2_PHY_ADDR 1
443#define TSEC1_PHYIDX 0
444#define TSEC2_PHYIDX 0
Andy Fleming3a790132007-08-15 20:03:25 -0500445#define TSEC1_FLAGS TSEC_GIGABIT
446#define TSEC2_FLAGS TSEC_GIGABIT
Marian Balakowicz991425f2006-03-14 16:24:38 +0100447
448/* Options are: TSEC[0-1] */
449#define CONFIG_ETHPRIME "TSEC0"
450
451#endif /* CONFIG_TSEC_ENET */
452
453/*
454 * Configure on-board RTC
455 */
456#define CONFIG_RTC_DS1374 /* use ds1374 rtc via i2c */
457#define CFG_I2C_RTC_ADDR 0x68 /* at address 0x68 */
458
459/*
460 * Environment
461 */
462#ifndef CFG_RAMBOOT
463 #define CFG_ENV_IS_IN_FLASH 1
Timur Tabib2893e12007-11-05 09:34:06 -0600464 #define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN)
Marian Balakowicz991425f2006-03-14 16:24:38 +0100465 #define CFG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */
466 #define CFG_ENV_SIZE 0x2000
467
468/* Address and size of Redundant Environment Sector */
469#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR + CFG_ENV_SECT_SIZE)
470#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
471
472#else
473 #define CFG_NO_FLASH 1 /* Flash is not usable now */
474 #define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
475 #define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000)
476 #define CFG_ENV_SIZE 0x2000
477#endif
478
479#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
480#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
481
Jon Loeliger8ea54992007-07-04 22:30:06 -0500482
483/*
Jon Loeliger659e2f62007-07-10 09:10:49 -0500484 * BOOTP options
485 */
486#define CONFIG_BOOTP_BOOTFILESIZE
487#define CONFIG_BOOTP_BOOTPATH
488#define CONFIG_BOOTP_GATEWAY
489#define CONFIG_BOOTP_HOSTNAME
490
491
492/*
Jon Loeliger8ea54992007-07-04 22:30:06 -0500493 * Command line configuration.
494 */
495#include <config_cmd_default.h>
496
497#define CONFIG_CMD_PING
498#define CONFIG_CMD_I2C
499#define CONFIG_CMD_DATE
500#define CONFIG_CMD_MII
501
Marian Balakowicz991425f2006-03-14 16:24:38 +0100502#if defined(CONFIG_PCI)
Jon Loeliger8ea54992007-07-04 22:30:06 -0500503 #define CONFIG_CMD_PCI
Marian Balakowicz991425f2006-03-14 16:24:38 +0100504#endif
505
Jon Loeliger8ea54992007-07-04 22:30:06 -0500506#if defined(CFG_RAMBOOT)
507 #undef CONFIG_CMD_ENV
508 #undef CONFIG_CMD_LOADS
509#endif
510
Marian Balakowicz991425f2006-03-14 16:24:38 +0100511
512#undef CONFIG_WATCHDOG /* watchdog disabled */
513
514/*
515 * Miscellaneous configurable options
516 */
517#define CFG_LONGHELP /* undef to save memory */
518#define CFG_LOAD_ADDR 0x2000000 /* default load address */
519#define CFG_PROMPT "=> " /* Monitor Command Prompt */
520
Jon Loeliger8ea54992007-07-04 22:30:06 -0500521#if defined(CONFIG_CMD_KGDB)
Marian Balakowicz991425f2006-03-14 16:24:38 +0100522 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
523#else
524 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
525#endif
526
527#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
528#define CFG_MAXARGS 16 /* max number of command args */
529#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
530#define CFG_HZ 1000 /* decrementer freq: 1ms ticks */
531
532/*
533 * For booting Linux, the board info and command line data
534 * have to be in the first 8 MB of memory, since this is
535 * the maximum mapped by the Linux kernel during initialization.
536 */
537#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/
538
Marian Balakowicz991425f2006-03-14 16:24:38 +0100539#define CFG_RCWH_PCIHOST 0x80000000 /* PCIHOST */
540
541#if 1 /*528/264*/
542#define CFG_HRCW_LOW (\
543 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
544 HRCWL_DDR_TO_SCB_CLK_1X1 |\
Kumar Gala8fe9bf62006-04-20 13:45:32 -0500545 HRCWL_CSB_TO_CLKIN |\
Marian Balakowicz991425f2006-03-14 16:24:38 +0100546 HRCWL_VCO_1X2 |\
547 HRCWL_CORE_TO_CSB_2X1)
548#elif 0 /*396/132*/
549#define CFG_HRCW_LOW (\
550 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
551 HRCWL_DDR_TO_SCB_CLK_1X1 |\
Kumar Gala8fe9bf62006-04-20 13:45:32 -0500552 HRCWL_CSB_TO_CLKIN |\
Marian Balakowicz991425f2006-03-14 16:24:38 +0100553 HRCWL_VCO_1X4 |\
554 HRCWL_CORE_TO_CSB_3X1)
555#elif 0 /*264/132*/
556#define CFG_HRCW_LOW (\
557 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
558 HRCWL_DDR_TO_SCB_CLK_1X1 |\
Kumar Gala8fe9bf62006-04-20 13:45:32 -0500559 HRCWL_CSB_TO_CLKIN |\
Marian Balakowicz991425f2006-03-14 16:24:38 +0100560 HRCWL_VCO_1X4 |\
561 HRCWL_CORE_TO_CSB_2X1)
562#elif 0 /*132/132*/
563#define CFG_HRCW_LOW (\
564 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
565 HRCWL_DDR_TO_SCB_CLK_1X1 |\
Kumar Gala8fe9bf62006-04-20 13:45:32 -0500566 HRCWL_CSB_TO_CLKIN |\
Marian Balakowicz991425f2006-03-14 16:24:38 +0100567 HRCWL_VCO_1X4 |\
568 HRCWL_CORE_TO_CSB_1X1)
569#elif 0 /*264/264 */
570#define CFG_HRCW_LOW (\
571 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
572 HRCWL_DDR_TO_SCB_CLK_1X1 |\
Kumar Gala8fe9bf62006-04-20 13:45:32 -0500573 HRCWL_CSB_TO_CLKIN |\
Marian Balakowicz991425f2006-03-14 16:24:38 +0100574 HRCWL_VCO_1X4 |\
575 HRCWL_CORE_TO_CSB_1X1)
576#endif
577
578#if defined(PCI_64BIT)
579#define CFG_HRCW_HIGH (\
580 HRCWH_PCI_HOST |\
581 HRCWH_64_BIT_PCI |\
582 HRCWH_PCI1_ARBITER_ENABLE |\
583 HRCWH_PCI2_ARBITER_DISABLE |\
584 HRCWH_CORE_ENABLE |\
585 HRCWH_FROM_0X00000100 |\
586 HRCWH_BOOTSEQ_DISABLE |\
587 HRCWH_SW_WATCHDOG_DISABLE |\
588 HRCWH_ROM_LOC_LOCAL_16BIT |\
589 HRCWH_TSEC1M_IN_GMII |\
590 HRCWH_TSEC2M_IN_GMII )
591#else
592#define CFG_HRCW_HIGH (\
593 HRCWH_PCI_HOST |\
594 HRCWH_32_BIT_PCI |\
595 HRCWH_PCI1_ARBITER_ENABLE |\
596 HRCWH_PCI2_ARBITER_ENABLE |\
597 HRCWH_CORE_ENABLE |\
598 HRCWH_FROM_0X00000100 |\
599 HRCWH_BOOTSEQ_DISABLE |\
600 HRCWH_SW_WATCHDOG_DISABLE |\
601 HRCWH_ROM_LOC_LOCAL_16BIT |\
602 HRCWH_TSEC1M_IN_GMII |\
603 HRCWH_TSEC2M_IN_GMII )
604#endif
605
606/* System IO Config */
607#define CFG_SICRH SICRH_TSOBI1
608#define CFG_SICRL SICRL_LDP_A
609
610#define CFG_HID0_INIT 0x000000000
Kumar Gala8fe9bf62006-04-20 13:45:32 -0500611#define CFG_HID0_FINAL HID0_ENABLE_MACHINE_CHECK
Marian Balakowicz991425f2006-03-14 16:24:38 +0100612
613/* #define CFG_HID0_FINAL (\
614 HID0_ENABLE_INSTRUCTION_CACHE |\
615 HID0_ENABLE_M_BIT |\
616 HID0_ENABLE_ADDRESS_BROADCAST ) */
617
618
619#define CFG_HID2 HID2_HBE
620
621/* DDR @ 0x00000000 */
622#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
623#define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
624
625/* PCI @ 0x80000000 */
626#ifdef CONFIG_PCI
627#define CFG_IBAT1L (CFG_PCI1_MEM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
628#define CFG_IBAT1U (CFG_PCI1_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
629#define CFG_IBAT2L (CFG_PCI1_MMIO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
630#define CFG_IBAT2U (CFG_PCI1_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
631#else
632#define CFG_IBAT1L (0)
633#define CFG_IBAT1U (0)
634#define CFG_IBAT2L (0)
635#define CFG_IBAT2U (0)
636#endif
637
Kumar Gala8fe9bf62006-04-20 13:45:32 -0500638#ifdef CONFIG_MPC83XX_PCI2
639#define CFG_IBAT3L (CFG_PCI2_MEM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
640#define CFG_IBAT3U (CFG_PCI2_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
641#define CFG_IBAT4L (CFG_PCI2_MMIO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
642#define CFG_IBAT4U (CFG_PCI2_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
643#else
644#define CFG_IBAT3L (0)
645#define CFG_IBAT3U (0)
646#define CFG_IBAT4L (0)
647#define CFG_IBAT4U (0)
648#endif
Marian Balakowicz991425f2006-03-14 16:24:38 +0100649
Kumar Gala8fe9bf62006-04-20 13:45:32 -0500650/* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */
Timur Tabid239d742006-11-03 12:00:28 -0600651#define CFG_IBAT5L (CFG_IMMR | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
652#define CFG_IBAT5U (CFG_IMMR | BATU_BL_256M | BATU_VS | BATU_VP)
Marian Balakowicz991425f2006-03-14 16:24:38 +0100653
Kumar Gala8fe9bf62006-04-20 13:45:32 -0500654/* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */
655#define CFG_IBAT6L (0xF0000000 | BATL_PP_10 | BATL_MEMCOHERENCE)
656#define CFG_IBAT6U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
Marian Balakowicz991425f2006-03-14 16:24:38 +0100657
Kumar Gala8fe9bf62006-04-20 13:45:32 -0500658#define CFG_IBAT7L (0)
659#define CFG_IBAT7U (0)
Marian Balakowicz991425f2006-03-14 16:24:38 +0100660
661#define CFG_DBAT0L CFG_IBAT0L
662#define CFG_DBAT0U CFG_IBAT0U
663#define CFG_DBAT1L CFG_IBAT1L
664#define CFG_DBAT1U CFG_IBAT1U
665#define CFG_DBAT2L CFG_IBAT2L
666#define CFG_DBAT2U CFG_IBAT2U
667#define CFG_DBAT3L CFG_IBAT3L
668#define CFG_DBAT3U CFG_IBAT3U
669#define CFG_DBAT4L CFG_IBAT4L
670#define CFG_DBAT4U CFG_IBAT4U
671#define CFG_DBAT5L CFG_IBAT5L
672#define CFG_DBAT5U CFG_IBAT5U
673#define CFG_DBAT6L CFG_IBAT6L
674#define CFG_DBAT6U CFG_IBAT6U
675#define CFG_DBAT7L CFG_IBAT7L
676#define CFG_DBAT7U CFG_IBAT7U
677
678/*
679 * Internal Definitions
680 *
681 * Boot Flags
682 */
683#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
684#define BOOTFLAG_WARM 0x02 /* Software reboot */
685
Jon Loeliger8ea54992007-07-04 22:30:06 -0500686#if defined(CONFIG_CMD_KGDB)
Marian Balakowicz991425f2006-03-14 16:24:38 +0100687#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
688#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
689#endif
690
691/*
692 * Environment Configuration
693 */
694#define CONFIG_ENV_OVERWRITE
695
696#if defined(CONFIG_TSEC_ENET)
697#define CONFIG_ETHADDR 00:04:9f:ef:23:33
698#define CONFIG_HAS_ETH1
Andy Fleming10327dc2007-08-16 16:35:02 -0500699#define CONFIG_HAS_ETH0
Marian Balakowicz991425f2006-03-14 16:24:38 +0100700#define CONFIG_ETH1ADDR 00:E0:0C:00:7E:21
701#endif
702
Kim Phillipsbf0b5422006-11-01 00:10:40 -0600703#define CONFIG_IPADDR 192.168.1.253
Marian Balakowicz991425f2006-03-14 16:24:38 +0100704
705#define CONFIG_HOSTNAME mpc8349emds
Kim Phillipsbf0b5422006-11-01 00:10:40 -0600706#define CONFIG_ROOTPATH /nfsroot/rootfs
707#define CONFIG_BOOTFILE uImage
Marian Balakowicz991425f2006-03-14 16:24:38 +0100708
709#define CONFIG_SERVERIP 192.168.1.1
710#define CONFIG_GATEWAYIP 192.168.1.1
711#define CONFIG_NETMASK 255.255.255.0
712
713#define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */
714
715#define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */
716#undef CONFIG_BOOTARGS /* the boot command will set bootargs */
717
718#define CONFIG_BAUDRATE 115200
719
720#define CONFIG_PREBOOT "echo;" \
721 "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
722 "echo"
723
724#define CONFIG_EXTRA_ENV_SETTINGS \
725 "netdev=eth0\0" \
726 "hostname=mpc8349emds\0" \
727 "nfsargs=setenv bootargs root=/dev/nfs rw " \
728 "nfsroot=${serverip}:${rootpath}\0" \
729 "ramargs=setenv bootargs root=/dev/ram rw\0" \
730 "addip=setenv bootargs ${bootargs} " \
731 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
732 ":${hostname}:${netdev}:off panic=1\0" \
733 "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
734 "flash_nfs=run nfsargs addip addtty;" \
735 "bootm ${kernel_addr}\0" \
736 "flash_self=run ramargs addip addtty;" \
737 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
738 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
739 "bootm\0" \
Marian Balakowicz991425f2006-03-14 16:24:38 +0100740 "load=tftp 100000 /tftpboot/mpc8349emds/u-boot.bin\0" \
741 "update=protect off fe000000 fe03ffff; " \
742 "era fe000000 fe03ffff; cp.b 100000 fe000000 ${filesize}\0" \
743 "upd=run load;run update\0" \
Kim Phillipsbf0b5422006-11-01 00:10:40 -0600744 "fdtaddr=400000\0" \
745 "fdtfile=mpc8349emds.dtb\0" \
Marian Balakowicz991425f2006-03-14 16:24:38 +0100746 ""
747
Kim Phillipsbf0b5422006-11-01 00:10:40 -0600748#define CONFIG_NFSBOOTCOMMAND \
749 "setenv bootargs root=/dev/nfs rw " \
750 "nfsroot=$serverip:$rootpath " \
751 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
752 "console=$consoledev,$baudrate $othbootargs;" \
753 "tftp $loadaddr $bootfile;" \
754 "tftp $fdtaddr $fdtfile;" \
755 "bootm $loadaddr - $fdtaddr"
756
757#define CONFIG_RAMBOOTCOMMAND \
758 "setenv bootargs root=/dev/ram rw " \
759 "console=$consoledev,$baudrate $othbootargs;" \
760 "tftp $ramdiskaddr $ramdiskfile;" \
761 "tftp $loadaddr $bootfile;" \
762 "tftp $fdtaddr $fdtfile;" \
763 "bootm $loadaddr $ramdiskaddr $fdtaddr"
764
Marian Balakowicz991425f2006-03-14 16:24:38 +0100765#define CONFIG_BOOTCOMMAND "run flash_self"
766
767#endif /* __CONFIG_H */