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wdenk074cff02004-02-24 00:16:43 +00001/*
2 * Startup Code for S3C44B0 CPU-core
3 *
4 * (C) Copyright 2004
5 * DAVE Srl
6 *
7 * http://www.dave-tech.it
8 * http://www.wawnet.biz
9 * mailto:info@wawnet.biz
10 *
11 * See file CREDITS for list of people who contributed to this
12 * project.
13 *
14 * This program is free software; you can redistribute it and/or
15 * modify it under the terms of the GNU General Public License as
16 * published by the Free Software Foundation; either version 2 of
17 * the License, or (at your option) any later version.
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, write to the Free Software
26 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 * MA 02111-1307 USA
28 */
29
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +020030#include <asm-offsets.h>
wdenk074cff02004-02-24 00:16:43 +000031#include <config.h>
32#include <version.h>
33
wdenk074cff02004-02-24 00:16:43 +000034/*
35 * Jump vector table
36 */
37
38
39.globl _start
40_start: b reset
41 add pc, pc, #0x0c000000
42 add pc, pc, #0x0c000000
43 add pc, pc, #0x0c000000
44 add pc, pc, #0x0c000000
45 add pc, pc, #0x0c000000
46 add pc, pc, #0x0c000000
47 add pc, pc, #0x0c000000
48
49 .balignl 16,0xdeadbeef
50
51
52/*
53 *************************************************************************
54 *
55 * Startup Code (reset vector)
56 *
57 * do important init only if we don't start from memory!
58 * relocate u-boot to ram
59 * setup stack
60 * jump to second stage
61 *
62 *************************************************************************
63 */
64
Heiko Schocher01109552010-09-17 13:10:49 +020065.globl _TEXT_BASE
wdenk074cff02004-02-24 00:16:43 +000066_TEXT_BASE:
Wolfgang Denk14d0a022010-10-07 21:51:12 +020067 .word CONFIG_SYS_TEXT_BASE
wdenk074cff02004-02-24 00:16:43 +000068
wdenk074cff02004-02-24 00:16:43 +000069/*
wdenk42dfe7a2004-03-14 22:25:36 +000070 * These are defined in the board-specific linker script.
Albert Aribaud3336ca62010-11-25 22:45:02 +010071 * Subtracting _start from them lets the linker put their
72 * relative position in the executable instead of leaving
73 * them null.
wdenk074cff02004-02-24 00:16:43 +000074 */
Albert Aribaud3336ca62010-11-25 22:45:02 +010075.globl _bss_start_ofs
76_bss_start_ofs:
77 .word __bss_start - _start
wdenk42dfe7a2004-03-14 22:25:36 +000078
Albert Aribaud3336ca62010-11-25 22:45:02 +010079.globl _bss_end_ofs
80_bss_end_ofs:
81 .word _end - _start
wdenk074cff02004-02-24 00:16:43 +000082
83#ifdef CONFIG_USE_IRQ
84/* IRQ stack memory (calculated at run-time) */
85.globl IRQ_STACK_START
86IRQ_STACK_START:
87 .word 0x0badc0de
88
89/* IRQ stack memory (calculated at run-time) */
90.globl FIQ_STACK_START
91FIQ_STACK_START:
92 .word 0x0badc0de
93#endif
94
Heiko Schocher01109552010-09-17 13:10:49 +020095/* IRQ stack memory (calculated at run-time) + 8 bytes */
96.globl IRQ_STACK_START_IN
97IRQ_STACK_START_IN:
98 .word 0x0badc0de
wdenk074cff02004-02-24 00:16:43 +000099
Heiko Schocher01109552010-09-17 13:10:49 +0200100/*
101 * the actual reset code
102 */
103
104reset:
105 /*
106 * set the cpu to SVC32 mode
107 */
108 mrs r0,cpsr
109 bic r0,r0,#0x1f
110 orr r0,r0,#0xd3
111 msr cpsr,r0
112
113 /*
114 * we do sys-critical inits only at reboot,
115 * not when booting from ram!
116 */
117#ifndef CONFIG_SKIP_LOWLEVEL_INIT
118 bl cpu_init_crit
119 /*
120 * before relocating, we have to setup RAM timing
121 * because memory timing is board-dependend, you will
122 * find a lowlevel_init.S in your board directory.
123 */
124 bl lowlevel_init
125#endif
126
127/* Set stackpointer in internal RAM to call board_init_f */
128call_board_init_f:
129 ldr sp, =(CONFIG_SYS_INIT_SP_ADDR)
Heiko Schocher296cae72010-11-12 07:53:55 +0100130 bic sp, sp, #7 /* 8-byte alignment for ABI compliance */
Heiko Schocher01109552010-09-17 13:10:49 +0200131 ldr r0,=0x00000000
132 bl board_init_f
133
134/*------------------------------------------------------------------------------*/
135
136/*
137 * void relocate_code (addr_sp, gd, addr_moni)
138 *
139 * This "function" does not return, instead it continues in RAM
140 * after relocating the monitor code.
141 *
142 */
143 .globl relocate_code
144relocate_code:
145 mov r4, r0 /* save addr_sp */
146 mov r5, r1 /* save addr of gd */
147 mov r6, r2 /* save addr of destination */
148 mov r7, r2 /* save addr of destination */
149
150 /* Set up the stack */
151stack_setup:
152 mov sp, r4
153
154 adr r0, _start
155 ldr r2, _TEXT_BASE
Albert Aribaud3336ca62010-11-25 22:45:02 +0100156 ldr r3, _bss_start_ofs
157 add r2, r0, r3 /* r2 <- source end address */
Heiko Schocher01109552010-09-17 13:10:49 +0200158 cmp r0, r6
159 beq clear_bss
160
Heiko Schocher01109552010-09-17 13:10:49 +0200161copy_loop:
162 ldmia r0!, {r9-r10} /* copy from source address [r0] */
163 stmia r6!, {r9-r10} /* copy to target address [r1] */
Albert Aribaudda90d4c2010-10-05 16:06:39 +0200164 cmp r0, r2 /* until source end address [r2] */
165 blo copy_loop
Heiko Schocher01109552010-09-17 13:10:49 +0200166
167#ifndef CONFIG_PRELOADER
Albert Aribaud3336ca62010-11-25 22:45:02 +0100168 /*
169 * fix .rel.dyn relocations
170 */
171 ldr r0, _TEXT_BASE /* r0 <- Text base */
172 sub r9, r7, r0 /* r9 <- relocation offset */
173 ldr r10, _dynsym_start_ofs /* r10 <- sym table ofs */
174 add r10, r10, r0 /* r10 <- sym table in FLASH */
175 ldr r2, _rel_dyn_start_ofs /* r2 <- rel dyn start ofs */
176 add r2, r2, r0 /* r2 <- rel dyn start in FLASH */
177 ldr r3, _rel_dyn_end_ofs /* r3 <- rel dyn end ofs */
178 add r3, r3, r0 /* r3 <- rel dyn end in FLASH */
Heiko Schocher01109552010-09-17 13:10:49 +0200179fixloop:
Albert Aribaud3336ca62010-11-25 22:45:02 +0100180 ldr r0, [r2] /* r0 <- location to fix up, IN FLASH! */
181 add r0, r0, r9 /* r0 <- location to fix up in RAM */
182 ldr r1, [r2, #4]
183 and r8, r1, #0xff
184 cmp r8, #23 /* relative fixup? */
185 beq fixrel
186 cmp r8, #2 /* absolute fixup? */
187 beq fixabs
188 /* ignore unknown type of fixup */
189 b fixnext
190fixabs:
191 /* absolute fix: set location to (offset) symbol value */
192 mov r1, r1, LSR #4 /* r1 <- symbol index in .dynsym */
193 add r1, r10, r1 /* r1 <- address of symbol in table */
194 ldr r1, [r1, #4] /* r1 <- symbol value */
195 add r1, r9 /* r1 <- relocated sym addr */
196 b fixnext
197fixrel:
198 /* relative fix: increase location by offset */
199 ldr r1, [r0]
200 add r1, r1, r9
201fixnext:
202 str r1, [r0]
203 add r2, r2, #8 /* each rel.dyn entry is 8 bytes */
Heiko Schocher01109552010-09-17 13:10:49 +0200204 cmp r2, r3
Wolfgang Denk79e63132010-10-23 23:22:38 +0200205 blo fixloop
Heiko Schocher01109552010-09-17 13:10:49 +0200206#endif
Heiko Schocher01109552010-09-17 13:10:49 +0200207
208clear_bss:
209#ifndef CONFIG_PRELOADER
Albert Aribaud3336ca62010-11-25 22:45:02 +0100210 ldr r0, _bss_start_ofs
211 ldr r1, _bss_end_ofs
Heiko Schocher01109552010-09-17 13:10:49 +0200212 ldr r3, _TEXT_BASE /* Text base */
213 mov r4, r7 /* reloc addr */
Heiko Schocher01109552010-09-17 13:10:49 +0200214 add r0, r0, r4
Heiko Schocher01109552010-09-17 13:10:49 +0200215 add r1, r1, r4
216 mov r2, #0x00000000 /* clear */
217
218clbss_l:str r2, [r0] /* clear loop... */
219 add r0, r0, #4
220 cmp r0, r1
221 bne clbss_l
222
223 bl coloured_LED_init
224 bl red_LED_on
225#endif
226
227/*
228 * We are done. Do not return, instead branch to second part of board
229 * initialization, now running from RAM.
230 */
Albert Aribaud3336ca62010-11-25 22:45:02 +0100231 ldr r0, _board_init_r_ofs
232 adr r1, _start
233 add lr, r0, r1
234 add lr, lr, r9
Heiko Schocher01109552010-09-17 13:10:49 +0200235 /* setup parameters for board_init_r */
236 mov r0, r5 /* gd_t */
237 mov r1, r7 /* dest_addr */
238 /* jump to it ... */
Heiko Schocher01109552010-09-17 13:10:49 +0200239 mov pc, lr
240
Albert Aribaud3336ca62010-11-25 22:45:02 +0100241_board_init_r_ofs:
242 .word board_init_r - _start
243
244_rel_dyn_start_ofs:
245 .word __rel_dyn_start - _start
246_rel_dyn_end_ofs:
247 .word __rel_dyn_end - _start
248_dynsym_start_ofs:
249 .word __dynsym_start - _start
Heiko Schocher01109552010-09-17 13:10:49 +0200250
wdenk074cff02004-02-24 00:16:43 +0000251/*
252 *************************************************************************
253 *
254 * CPU_init_critical registers
255 *
256 * setup important registers
257 * setup memory timing
258 *
259 *************************************************************************
260 */
261
262#define INTCON (0x01c00000+0x200000)
263#define INTMSK (0x01c00000+0x20000c)
264#define LOCKTIME (0x01c00000+0x18000c)
265#define PLLCON (0x01c00000+0x180000)
266#define CLKCON (0x01c00000+0x180004)
267#define WTCON (0x01c00000+0x130000)
268cpu_init_crit:
269 /* disable watch dog */
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200270 ldr r0, =WTCON
wdenk074cff02004-02-24 00:16:43 +0000271 ldr r1, =0x0
272 str r1, [r0]
273
274 /*
275 * mask all IRQs by clearing all bits in the INTMRs
276 */
277 ldr r1,=INTMSK
278 ldr r0, =0x03fffeff
279 str r0, [r1]
280
281 ldr r1, =INTCON
282 ldr r0, =0x05
283 str r0, [r1]
284
285 /* Set Clock Control Register */
286 ldr r1, =LOCKTIME
287 ldrb r0, =800
288 strb r0, [r1]
289
290 ldr r1, =PLLCON
291
292#if CONFIG_S3C44B0_CLOCK_SPEED==66
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200293 ldr r0, =0x34031 /* 66MHz (Quartz=11MHz) */
wdenk074cff02004-02-24 00:16:43 +0000294#elif CONFIG_S3C44B0_CLOCK_SPEED==75
295 ldr r0, =0x610c1 /*B2: Xtal=20mhz Fclk=75MHz */
296#else
297# error CONFIG_S3C44B0_CLOCK_SPEED undefined
298#endif
299
300 str r0, [r1]
301
302 ldr r1,=CLKCON
303 ldr r0, =0x7ff8
304 str r0, [r1]
305
306 mov pc, lr
307
308
309/*************************************************/
310/* interrupt vectors */
311/*************************************************/
312real_vectors:
313 b reset
314 b undefined_instruction
315 b software_interrupt
316 b prefetch_abort
317 b data_abort
318 b not_used
319 b irq
320 b fiq
321
322/*************************************************/
323
324undefined_instruction:
325 mov r6, #3
326 b reset
327
328software_interrupt:
329 mov r6, #4
330 b reset
331
332prefetch_abort:
333 mov r6, #5
334 b reset
335
336data_abort:
337 mov r6, #6
338 b reset
339
340not_used:
341 /* we *should* never reach this */
342 mov r6, #7
343 b reset
344
345irq:
346 mov r6, #8
347 b reset
348
349fiq:
350 mov r6, #9
351 b reset