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Shengzhou Liuae6b03f2011-11-22 16:51:13 +08001Overview
2=========
3The P3060QDS is a Freescale reference board that hosts the six-core P3060 SOC.
4
5The P3060 Processor combines six e500mc Power Architecture processor
6cores(1.2GHz) with high-performance datapath acceleration
7architecture(DPAA), CoreNet fabric infrastructure, as well as network
8and peripheral bus interfaces required for networking, telecom/datacom,
9wireless infrastructure, and military/aerospace applications.
10
11
12P3060QDS Board Specifications:
13==============================
14Memory subsystem:
15 * 2G Bytes UDIMM DDR3(64bit bus) with ECC on
16 * 128M Bytes NOR flash single-chip memory
17 * 16M Bytes SPI flash
18 * 8K Bytes AT24C64 I2C EEPROM for RCW
19
20Ethernet(Default SERDES 0x19):
21 * FM1-dTSEC1: connected to RGMII PHY1 (Vitesse VSC8641 on board,Bottom of dual RJ45)
22 * FM1-dTSEC2: connected to RGMII PHY2 (Vitesse VSC8641 on board,Top of dual RJ45)
23 * FM1-dTSEC3: connected to SGMII PHY (Vitesse VSC8234 port1 in slot1)
24 * FM1-dTSEC4: connected to SGMII PHY (Vitesse VSC8234 port3 in slot1)
25 * FM2-dTSEC1: connected to SGMII PHY (Vitesse VSC8234 port0 in slot2)
26 * FM2-dTSEC2: connected to SGMII PHY (Vitesse VSC8234 port2 in slot2)
27 * FM2-dTSEC3: connected to SGMII PHY (Vitesse VSC8234 port0 in slot1)
28 * FM2-dTSEC4: connected to SGMII PHY (Vitesse VSC8234 port2 in slot1)
29
30PCIe:
31 * PCIe1: Lanes A, B, C and D of Bank1 are connected to one x4 PCIe SLOT4
32 * PCIe2: Lanes E, F, G and H of Bank1 are connected to one x4 PCIe SLOT3
33
34RapidIO:
35 * sRIO1: Lanes E, F, G and H of Bank1 are connected to sRIO1 (SLOT3)
36 * sRIO2: Lanes A, B, C and D of Bank1 are connected to sRIO2 (SLOT4)
37
38USB:
39 * USB1: connected via an external ULPI PHY SMC3315 to a TYPE-A interface
40 * USB2: connected via an external ULPI PHY SMC3315 to a TYPE-AB interface
41
42I2C:
43 * I2C1_CH0: EEPROM AT24C64(0x50) RCW, AT24C02(0x51) DDR SPD,
44 AT24C02(0x53) DDR SPD, AT24C02(0x57) SystemID, RTC DS3232(0x68)
45 * I2C1_CH1: 1588 RiserCard(0x55), HSLB Testport, TempMon
46 ADT7461(0x4C), SerDesMux DS64MB201(0x51/59/5C/5D)
47 * I2C1_CH2: VDD/GVDD/GIDD ZL6100 (0x21/0x22/0x23/0x24/0x40)
48 * I2C1_CH3: OCM CFG AT24C02(0x55), OCM IPL AT24C64(0x56)
49 * I2C1_CH4: PCIe SLOT1
50 * I2C1_CH5: PCIe SLOT2
51 * I2C1_CH6: PCIe SLOT3
52 * I2C1_CH7: PCIe SLOT4
53 * I2C2: NULL
54 * I2C3: NULL
55
56UART:
57 * Supports two UARTs up to 115200 bps for console
58
59
60Boot from NOR flash
61===================
621. Build image
63 export ARCH=powerpc
64 export CROSS_COMPILE=/your_path/gcc-4.5.xx-eglibc-2.11.xx/powerpc-linux-gnu/bin/powerpc-linux-gnu-
65 make P3060QDS_config
66 make
67
682. Program image
69 => tftp 1000000 u-boot.bin
70 => protect off all
71 => erase eff80000 efffffff
72 => cp.b 1000000 eff80000 80000
73
743. Program RCW
75 => tftp 1000000 rcw.bin
76 => protect off all
77 => erase e8000000 e801ffff
78 => cp.b 1000000 e8000000 50
79
804. Program FMAN Firmware ucode
81 => tftp 1000000 ucode.bin
82 => protect off all
83 => erase ef000000 ef0fffff
84 => cp.b 1000000 ef000000 2000
85
865. Change DIP-switch
87 RCW Location: SW1[1-5] = 01101 (eLBC 16bit NOR flash)
88 Note: 1 stands for 'on', 0 stands for 'off'
89
90
91Using the Device Tree Source File
92=================================
93To create the DTB (Device Tree Binary) image file, use a command
94similar to this:
95 dtc -O dtb -b 0 -p 1024 p3060qds.dts > p3060qds.dtb
96
97Or use the following command:
98 {linux-2.6}/make p3060qds.dtb ARCH=powerpc
99
100then the dtb file will be generated under the following directory:
101 {linux-2.6}/arch/powerpc/boot/p3060qds.dtb
102
103
104Booting Linux
105=============
106Place a linux uImage in the TFTP disk area.
107 tftp 1000000 uImage
108 tftp 2000000 rootfs.ext2.gz.uboot
109 tftp 3000000 p3060rdb.dtb
110 bootm 1000000 2000000 3000000
111