Gitiles
Code Review Sign In
gerrit.devboardsforandroid.linaro.org / platform / external / u-boot / 29cc2b542d9f4f4c811516b9fdbe4ba3018c6463 / . / configs / gazerbeam_defconfig
blob: 03cad403e0a230a9c86ad26944b70f9bb4886c80 [file] [log] [blame]
Dirk Eibachd494cdb2019-03-29 10:18:19 +0100[diff] [blame]1CONFIG_PPC=y
2CONFIG_SYS_TEXT_BASE=0xFE000000
Tom Rini98021542021-11-01 12:19:22 +0000[diff] [blame]3CONFIG_SYS_MALLOC_LEN=0x80000
Dirk Eibachd494cdb2019-03-29 10:18:19 +0100[diff] [blame]4CONFIG_SYS_MALLOC_F_LEN=0x600
Tom Rini53def462020-11-30 12:50:32 -0500[diff] [blame]5CONFIG_SYS_MEMTEST_START=0x00001000
6CONFIG_SYS_MEMTEST_END=0x07e00000
Tom Rinia09fea12019-11-18 20:02:10 -0500[diff] [blame]7CONFIG_ENV_SIZE=0x2000
8CONFIG_ENV_SECT_SIZE=0x10000
Tom Rini052170c2020-01-22 13:38:00 -0500[diff] [blame]9CONFIG_DM_GPIO=y
Tom Rini2bba7802021-06-28 10:17:29 -0400[diff] [blame]10CONFIG_DEFAULT_DEVICE_TREE="gazerbeam"
Dirk Eibachd494cdb2019-03-29 10:18:19 +0100[diff] [blame]11CONFIG_IDENT_STRING=" gazerbeam 0.01"
12CONFIG_SYS_CLK_FREQ=33333333
13CONFIG_MPC83xx=y
14CONFIG_TARGET_GAZERBEAM=y
15CONFIG_SYSTEM_PLL_VCO_DIV_2=y
16CONFIG_SYSTEM_PLL_FACTOR_4_1=y
17CONFIG_CORE_PLL_RATIO_3_1=y
18CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y
19CONFIG_TSEC1_MODE_RGMII=y
20CONFIG_TSEC2_MODE_RGMII=y
21CONFIG_BAT0=y
22CONFIG_BAT0_NAME="SDRAM"
23CONFIG_BAT0_BASE=0x00000000
24CONFIG_BAT0_LENGTH_128_MBYTES=y
25CONFIG_BAT0_ACCESS_RW=y
26CONFIG_BAT0_ICACHE_MEMORYCOHERENCE=y
27CONFIG_BAT0_DCACHE_MEMORYCOHERENCE=y
28CONFIG_BAT0_USER_MODE_VALID=y
29CONFIG_BAT0_SUPERVISOR_MODE_VALID=y
30CONFIG_BAT1=y
31CONFIG_BAT1_NAME="IMMR"
32CONFIG_BAT1_BASE=0xE0000000
33CONFIG_BAT1_LENGTH_8_MBYTES=y
34CONFIG_BAT1_ACCESS_RW=y
35CONFIG_BAT1_ICACHE_INHIBITED=y
36CONFIG_BAT1_ICACHE_GUARDED=y
37CONFIG_BAT1_DCACHE_INHIBITED=y
38CONFIG_BAT1_DCACHE_GUARDED=y
39CONFIG_BAT1_USER_MODE_VALID=y
40CONFIG_BAT1_SUPERVISOR_MODE_VALID=y
41CONFIG_BAT2=y
42CONFIG_BAT2_NAME="FLASH"
43CONFIG_BAT2_BASE=0xFE000000
44CONFIG_BAT2_LENGTH_8_MBYTES=y
45CONFIG_BAT2_ACCESS_RW=y
46CONFIG_BAT2_ICACHE_MEMORYCOHERENCE=y
47CONFIG_BAT2_DCACHE_INHIBITED=y
48CONFIG_BAT2_DCACHE_GUARDED=y
49CONFIG_BAT2_USER_MODE_VALID=y
50CONFIG_BAT2_SUPERVISOR_MODE_VALID=y
51CONFIG_BAT3=y
52CONFIG_BAT3_NAME="INIT_RAM"
53CONFIG_BAT3_BASE=0xE6000000
54CONFIG_BAT3_ACCESS_RW=y
55CONFIG_BAT3_USER_MODE_VALID=y
56CONFIG_BAT3_SUPERVISOR_MODE_VALID=y
57CONFIG_LBLAW0=y
58CONFIG_LBLAW0_BASE=0xFE000000
59CONFIG_LBLAW0_NAME="FLASH"
60CONFIG_LBLAW0_LENGTH_8_MBYTES=y
61CONFIG_LBLAW1=y
62CONFIG_LBLAW1_BASE=0xE0600000
63CONFIG_LBLAW1_NAME="FPGA0"
64CONFIG_LBLAW1_LENGTH_1_MBYTES=y
65CONFIG_LBLAW2=y
66CONFIG_LBLAW2_BASE=0xE0700000
67CONFIG_LBLAW2_NAME="FPGA1"
68CONFIG_LBLAW2_LENGTH_1_MBYTES=y
69CONFIG_ELBC_BR0_OR0=y
70CONFIG_BR0_OR0_NAME="FLASH"
71CONFIG_BR0_OR0_BASE=0xFE000000
72CONFIG_BR0_PORTSIZE_16BIT=y
73CONFIG_OR0_AM_8_MBYTES=y
74CONFIG_OR0_SCY_15=y
75CONFIG_OR0_CSNT_EARLIER=y
76CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y
77CONFIG_OR0_XACS_EXTENDED=y
78CONFIG_OR0_TRLX_RELAXED=y
79CONFIG_OR0_EHTR_8_CYCLE=y
80CONFIG_ELBC_BR1_OR1=y
81CONFIG_BR1_OR1_NAME="FPGA0"
82CONFIG_BR1_OR1_BASE=0xE0600000
83CONFIG_BR1_PORTSIZE_16BIT=y
84CONFIG_OR1_AM_1_MBYTES=y
85CONFIG_OR1_SCY_5=y
86CONFIG_OR1_CSNT_EARLIER=y
87CONFIG_ELBC_BR2_OR2=y
88CONFIG_BR2_OR2_NAME="FPGA1"
89CONFIG_BR2_OR2_BASE=0xE0700000
90CONFIG_BR2_PORTSIZE_16BIT=y
91CONFIG_OR2_AM_1_MBYTES=y
92CONFIG_OR2_SCY_5=y
93CONFIG_OR2_CSNT_EARLIER=y
94CONFIG_HID0_FINAL_EMCP=y
95CONFIG_HID0_FINAL_DPM=y
96CONFIG_HID0_FINAL_ICE=y
97CONFIG_HID2_HBE=y
98CONFIG_SICR_ETSEC1_A_TSEC_GTX_CLK125=y
99CONFIG_SICR_GPIO_A_TSEC2=y
100CONFIG_SICR_GPIO_B_TSEC_GTX_CLK125=y
101CONFIG_SICR_IEEE1588_A_GPIO=y
102CONFIG_SICR_GTM_GPIO=y
103CONFIG_SICR_ETSEC2_GPIO=y
104CONFIG_SICR_GPIOSEL_IEEE1588=y
105CONFIG_SICR_TMSOBI1_2_5_V=y
106CONFIG_SICR_TMSOBI2_2_5_V=y
107CONFIG_ACR_PIPE_DEP_4=y
108CONFIG_ACR_RPTCNT_4=y
109CONFIG_SPCR_TSECEP_3=y
110CONFIG_LCRR_DBYP_PLL_BYPASSED=y
111CONFIG_LCRR_CLKDIV_2=y
112CONFIG_SYS_FPGA_FLAVOR_GAZERBEAM=y
113CONFIG_CMD_IOLOOP=y
114CONFIG_FIT=y
115CONFIG_FIT_SIGNATURE=y
116CONFIG_FIT_VERBOSE=y
117CONFIG_OF_BOARD_SETUP=y
118CONFIG_OF_STDOUT_VIA_ALIAS=y
119CONFIG_BOOTDELAY=5
Tom Rini0817daa2020-10-09 12:22:06 -0400[diff] [blame]120CONFIG_AUTOBOOT_KEYED=y
121CONFIG_AUTOBOOT_STOP_STR=" "
Tom Rini970bf862021-11-10 09:11:40 -0500[diff] [blame]122CONFIG_USE_BOOTCOMMAND=y
123CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/mmcblk0p3 rw rootwait console=$consoledev,$baudrate $othbootargs;ext2load mmc 0:2 ${kernel_addr} $bootfile;ext2load mmc 0:2 ${fdt_addr} $fdtfile;bootm ${kernel_addr} - ${fdt_addr}"
Dirk Eibachd494cdb2019-03-29 10:18:19 +0100[diff] [blame]124# CONFIG_CONSOLE_MUX is not set
125CONFIG_SYS_CONSOLE_INFO_QUIET=y
126CONFIG_DISPLAY_CPUINFO=y
127# CONFIG_DISPLAY_BOARDINFO is not set
128CONFIG_DISPLAY_BOARDINFO_LATE=y
129CONFIG_BOARD_EARLY_INIT_R=y
130CONFIG_LAST_STAGE_INIT=y
131CONFIG_HUSH_PARSER=y
Dirk Eibachd494cdb2019-03-29 10:18:19 +0100[diff] [blame]132CONFIG_CMD_CPU=y
133CONFIG_CMD_BINOP=y
134CONFIG_CMD_MEMTEST=y
135CONFIG_SYS_ALT_MEMTEST=y
136CONFIG_CMD_GPIO=y
137CONFIG_CMD_I2C=y
138CONFIG_CMD_MMC=y
139CONFIG_CMD_AXI=y
140# CONFIG_CMD_SETEXPR is not set
141# CONFIG_CMD_NFS is not set
142CONFIG_CMD_MII=y
Dirk Eibachd494cdb2019-03-29 10:18:19 +0100[diff] [blame]143CONFIG_CMD_PING=y
144CONFIG_CMD_CACHE=y
145CONFIG_CMD_HASH=y
146CONFIG_CMD_TPM=y
147CONFIG_CMD_EXT2=y
148CONFIG_DOS_PARTITION=y
149CONFIG_OF_CONTROL=y
150CONFIG_OF_LIVE=y
Adam Forde91907a2020-07-03 06:48:56 -0500[diff] [blame]151CONFIG_ENV_OVERWRITE=y
Tom Rinicb6617a2019-11-10 11:28:03 -0500[diff] [blame]152CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
Tom Rinia09fea12019-11-18 20:02:10 -0500[diff] [blame]153CONFIG_ENV_ADDR=0xFE080000
154CONFIG_ENV_ADDR_REDUND=0xFE090000
Tom Rinifdfb17b2022-02-25 11:19:48 -0500[diff] [blame]155CONFIG_USE_BOOTFILE=y
156CONFIG_BOOTFILE="uImage"
Dirk Eibachd494cdb2019-03-29 10:18:19 +0100[diff] [blame]157CONFIG_DM=y
158CONFIG_REGMAP=y
159CONFIG_AXI=y
160CONFIG_IHS_AXI=y
161CONFIG_CLK=y
Sean Anderson052bebe2021-12-15 11:36:20 -0500[diff] [blame]162CONFIG_CLK_ICS8N3QV01=y
Dirk Eibachd494cdb2019-03-29 10:18:19 +0100[diff] [blame]163CONFIG_CPU=y
164CONFIG_CPU_MPC83XX=y
Tom Rinic7fad782021-11-13 18:10:40 -0500[diff] [blame]165CONFIG_SYS_BR0_PRELIM_BOOL=y
166CONFIG_SYS_BR0_PRELIM=0xFE001001
167CONFIG_SYS_OR0_PRELIM=0xFF800FF6
168CONFIG_SYS_BR1_PRELIM_BOOL=y
169CONFIG_SYS_BR1_PRELIM=0xE0601001
170CONFIG_SYS_OR1_PRELIM=0xFFF00850
171CONFIG_SYS_BR2_PRELIM_BOOL=y
172CONFIG_SYS_BR2_PRELIM=0xE0701001
173CONFIG_SYS_OR2_PRELIM=0xFFF00850
Dirk Eibachd494cdb2019-03-29 10:18:19 +0100[diff] [blame]174CONFIG_DM_PCA953X=y
175CONFIG_MPC8XXX_GPIO=y
176CONFIG_DM_I2C=y
177CONFIG_SYS_I2C_FSL=y
178CONFIG_SYS_I2C_IHS=y
179CONFIG_MISC=y
180CONFIG_GDSYS_RXAUI_CTRL=y
181CONFIG_GDSYS_IOEP=y
182CONFIG_MPC83XX_SERDES=y
183CONFIG_GDSYS_SOC=y
184CONFIG_IHS_FPGA=y
Dirk Eibachd494cdb2019-03-29 10:18:19 +0100[diff] [blame]185CONFIG_FSL_ESDHC=y
Miquel Raynal1de770d2019-10-03 19:50:04 +0200[diff] [blame]186CONFIG_DM_MTD=y
Dirk Eibachd494cdb2019-03-29 10:18:19 +0100[diff] [blame]187CONFIG_MTD_NOR_FLASH=y
Dirk Eibachd494cdb2019-03-29 10:18:19 +0100[diff] [blame]188CONFIG_CFI_FLASH=y
189CONFIG_SYS_FLASH_PROTECTION=y
190CONFIG_SYS_FLASH_CFI=y
191CONFIG_PHYLIB_10G=y
Tom Rini306881a2020-04-24 15:35:53 -0400[diff] [blame]192CONFIG_PHY_ATHEROS=y
193CONFIG_PHY_BROADCOM=y
194CONFIG_PHY_DAVICOM=y
195CONFIG_PHY_LXT=y
Dirk Eibachd494cdb2019-03-29 10:18:19 +0100[diff] [blame]196CONFIG_PHY_MARVELL=y
Tom Rini306881a2020-04-24 15:35:53 -0400[diff] [blame]197CONFIG_PHY_NATSEMI=y
198CONFIG_PHY_REALTEK=y
199CONFIG_PHY_SMSC=y
200CONFIG_PHY_TERANETICS=y
201CONFIG_PHY_VITESSE=y
Dirk Eibachd494cdb2019-03-29 10:18:19 +0100[diff] [blame]202CONFIG_DM_ETH=y
203CONFIG_TSEC_ENET=y
204# CONFIG_PCI is not set
205CONFIG_RAM=y
206CONFIG_MPC83XX_SDRAM=y
207CONFIG_DM_RESET=y
208CONFIG_DM_SERIAL=y
209CONFIG_SYS_NS16550=y
Simon Glass3a8ee3d2020-11-05 06:32:05 -0700[diff] [blame]210CONFIG_SYSINFO=y
211CONFIG_SYSINFO_GAZERBEAM=y
Dirk Eibachd494cdb2019-03-29 10:18:19 +0100[diff] [blame]212CONFIG_SYSRESET=y
Rasmus Villemoes875669d2019-12-13 15:47:58 +0000[diff] [blame]213CONFIG_SYSRESET_MPC83XX=y
Dirk Eibachd494cdb2019-03-29 10:18:19 +0100[diff] [blame]214CONFIG_TIMER=y
215CONFIG_MPC83XX_TIMER=y
216CONFIG_TPM_ATMEL_TWI=y
217CONFIG_TPM_AUTH_SESSIONS=y
218# CONFIG_TPM_V2 is not set
219CONFIG_DM_VIDEO=y
Dirk Eibachd494cdb2019-03-29 10:18:19 +0100[diff] [blame]220CONFIG_DISPLAY=y
221CONFIG_LOGICORE_DP_TX=y
222CONFIG_OSD=y
223CONFIG_IHS_VIDEO_OUT=y
224CONFIG_TPM=y