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wdenk717b5aa2002-04-27 11:09:31 +00001/*
2 * NS16550 Serial Port
Stefan Roesea47a12b2010-04-15 16:07:28 +02003 * originally from linux source (arch/powerpc/boot/ns16550.h)
Detlev Zundel200779e2009-04-03 11:53:01 +02004 *
5 * Cleanup and unification
6 * (C) 2009 by Detlev Zundel, DENX Software Engineering GmbH
7 *
wdenk717b5aa2002-04-27 11:09:31 +00008 * modified slightly to
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +02009 * have addresses as offsets from CONFIG_SYS_ISA_BASE
wdenk717b5aa2002-04-27 11:09:31 +000010 * added a few more definitions
11 * added prototypes for ns16550.c
12 * reduced no of com ports to 2
13 * modifications (c) Rob Taylor, Flying Pig Systems. 2000.
Wolfgang Denkb87dfd22006-07-19 13:50:38 +020014 *
Heiko Schocherf5e0d032006-06-19 11:02:41 +020015 * added support for port on 64-bit bus
16 * by Richard Danter (richard.danter@windriver.com), (C) 2005 Wind River Systems
wdenk717b5aa2002-04-27 11:09:31 +000017 */
18
Detlev Zundel453c0d72009-04-03 16:45:46 +020019/*
20 * Note that the following macro magic uses the fact that the compiler
21 * will not allocate storage for arrays of size 0
22 */
23
Simon Glassd30c7202020-12-22 19:30:18 -070024#ifndef __ns16550_h
25#define __ns16550_h
26
Dave Aldridge79df1202011-09-01 22:47:14 +000027#include <linux/types.h>
28
Simon Glass12e431b2014-09-04 16:27:34 -060029#ifdef CONFIG_DM_SERIAL
30/*
31 * For driver model we always use one byte per register, and sort out the
32 * differences in the driver
33 */
34#define CONFIG_SYS_NS16550_REG_SIZE (-1)
35#endif
36
Simon Glass62cbde42019-12-19 17:58:18 -070037#ifdef CONFIG_NS16550_DYNAMIC
38#define UART_REG(x) unsigned char x
39#else
Detlev Zundel453c0d72009-04-03 16:45:46 +020040#if !defined(CONFIG_SYS_NS16550_REG_SIZE) || (CONFIG_SYS_NS16550_REG_SIZE == 0)
wdenk717b5aa2002-04-27 11:09:31 +000041#error "Please define NS16550 registers size."
Simon Glass90914002015-05-12 14:55:02 -060042#elif defined(CONFIG_SYS_NS16550_MEM32) && !defined(CONFIG_DM_SERIAL)
Dave Aldridge79df1202011-09-01 22:47:14 +000043#define UART_REG(x) u32 x
Detlev Zundel453c0d72009-04-03 16:45:46 +020044#elif (CONFIG_SYS_NS16550_REG_SIZE > 0)
45#define UART_REG(x) \
46 unsigned char prepad_##x[CONFIG_SYS_NS16550_REG_SIZE - 1]; \
47 unsigned char x;
48#elif (CONFIG_SYS_NS16550_REG_SIZE < 0)
49#define UART_REG(x) \
50 unsigned char x; \
51 unsigned char postpad_##x[-CONFIG_SYS_NS16550_REG_SIZE - 1];
wdenk717b5aa2002-04-27 11:09:31 +000052#endif
Simon Glass62cbde42019-12-19 17:58:18 -070053#endif /* CONFIG_NS16550_DYNAMIC */
54
55enum ns16550_flags {
56 NS16550_FLAG_IO = 1 << 0, /* Use I/O access (else mem-mapped) */
57 NS16550_FLAG_ENDIAN = 1 << 1, /* Use out_le/be_32() */
58 NS16550_FLAG_BE = 1 << 2, /* Big-endian access (else little) */
59};
wdenk717b5aa2002-04-27 11:09:31 +000060
Simon Glass12e431b2014-09-04 16:27:34 -060061/**
Simon Glass8a8d24b2020-12-03 16:55:23 -070062 * struct ns16550_plat - information about a NS16550 port
Simon Glass12e431b2014-09-04 16:27:34 -060063 *
64 * @base: Base register address
Simon Glass62cbde42019-12-19 17:58:18 -070065 * @reg_width: IO accesses size of registers (in bytes, 1 or 4)
Simon Glass12e431b2014-09-04 16:27:34 -060066 * @reg_shift: Shift size of registers (0=byte, 1=16bit, 2=32bit...)
Simon Glass62cbde42019-12-19 17:58:18 -070067 * @reg_offset: Offset to start of registers (normally 0)
Simon Glass12e431b2014-09-04 16:27:34 -060068 * @clock: UART base clock speed in Hz
Simon Glass62cbde42019-12-19 17:58:18 -070069 * @fcr: Offset of FCR register (normally UART_FCR_DEFVAL)
70 * @flags: A few flags (enum ns16550_flags)
Simon Glass4e8de062019-09-25 08:56:18 -060071 * @bdf: PCI slot/function (pci_dev_t)
Simon Glass12e431b2014-09-04 16:27:34 -060072 */
Simon Glass8a8d24b2020-12-03 16:55:23 -070073struct ns16550_plat {
Simon Glass167efe02014-10-22 21:37:04 -060074 unsigned long base;
Andy Shevchenko4e720772018-11-20 23:52:35 +020075 int reg_width;
Simon Glass12e431b2014-09-04 16:27:34 -060076 int reg_shift;
Michal Simek59b35dd2016-02-16 16:17:49 +010077 int reg_offset;
Andy Shevchenko0af76162018-11-20 23:52:34 +020078 int clock;
Marek Vasut65f83802016-12-01 02:06:29 +010079 u32 fcr;
Simon Glass62cbde42019-12-19 17:58:18 -070080 int flags;
Simon Glass4e8de062019-09-25 08:56:18 -060081#if defined(CONFIG_PCI) && defined(CONFIG_SPL)
82 int bdf;
83#endif
Simon Glass12e431b2014-09-04 16:27:34 -060084};
85
86struct udevice;
87
Simon Glassd30c7202020-12-22 19:30:18 -070088struct ns16550 {
Detlev Zundel453c0d72009-04-03 16:45:46 +020089 UART_REG(rbr); /* 0 */
90 UART_REG(ier); /* 1 */
91 UART_REG(fcr); /* 2 */
92 UART_REG(lcr); /* 3 */
93 UART_REG(mcr); /* 4 */
94 UART_REG(lsr); /* 5 */
95 UART_REG(msr); /* 6 */
96 UART_REG(spr); /* 7 */
Mikhail Kshevetskiy99b603e2012-07-09 08:52:43 +000097#ifdef CONFIG_SOC_DA8XX
98 UART_REG(reg8); /* 8 */
99 UART_REG(reg9); /* 9 */
100 UART_REG(revid1); /* A */
101 UART_REG(revid2); /* B */
102 UART_REG(pwr_mgmt); /* C */
103 UART_REG(mdr1); /* D */
104#else
Detlev Zundel453c0d72009-04-03 16:45:46 +0200105 UART_REG(mdr1); /* 8 */
106 UART_REG(reg9); /* 9 */
107 UART_REG(regA); /* A */
108 UART_REG(regB); /* B */
109 UART_REG(regC); /* C */
110 UART_REG(regD); /* D */
111 UART_REG(regE); /* E */
112 UART_REG(uasr); /* F */
113 UART_REG(scr); /* 10*/
114 UART_REG(ssr); /* 11*/
Mikhail Kshevetskiy99b603e2012-07-09 08:52:43 +0000115#endif
Simon Glass12e431b2014-09-04 16:27:34 -0600116#ifdef CONFIG_DM_SERIAL
Simon Glass8a8d24b2020-12-03 16:55:23 -0700117 struct ns16550_plat *plat;
Simon Glass12e431b2014-09-04 16:27:34 -0600118#endif
Detlev Zundel453c0d72009-04-03 16:45:46 +0200119};
120
wdenk717b5aa2002-04-27 11:09:31 +0000121#define thr rbr
122#define iir fcr
123#define dll rbr
124#define dlm ier
125
Detlev Zundel200779e2009-04-03 11:53:01 +0200126/*
127 * These are the definitions for the FIFO Control Register
128 */
Simon Glassf8df9d02011-10-15 19:14:09 +0000129#define UART_FCR_FIFO_EN 0x01 /* Fifo enable */
Detlev Zundel200779e2009-04-03 11:53:01 +0200130#define UART_FCR_CLEAR_RCVR 0x02 /* Clear the RCVR FIFO */
131#define UART_FCR_CLEAR_XMIT 0x04 /* Clear the XMIT FIFO */
132#define UART_FCR_DMA_SELECT 0x08 /* For DMA applications */
133#define UART_FCR_TRIGGER_MASK 0xC0 /* Mask for the FIFO trigger range */
134#define UART_FCR_TRIGGER_1 0x00 /* Mask for trigger set at 1 */
135#define UART_FCR_TRIGGER_4 0x40 /* Mask for trigger set at 4 */
136#define UART_FCR_TRIGGER_8 0x80 /* Mask for trigger set at 8 */
137#define UART_FCR_TRIGGER_14 0xC0 /* Mask for trigger set at 14 */
wdenk717b5aa2002-04-27 11:09:31 +0000138
Detlev Zundel200779e2009-04-03 11:53:01 +0200139#define UART_FCR_RXSR 0x02 /* Receiver soft reset */
140#define UART_FCR_TXSR 0x04 /* Transmitter soft reset */
wdenk717b5aa2002-04-27 11:09:31 +0000141
Marek Vasut0b060ee2016-12-01 02:06:31 +0100142/* Ingenic JZ47xx specific UART-enable bit. */
143#define UART_FCR_UME 0x10
144
Heiko Schocher17fa0322017-01-18 08:05:49 +0100145/* Clear & enable FIFOs */
146#define UART_FCR_DEFVAL (UART_FCR_FIFO_EN | \
147 UART_FCR_RXSR | \
148 UART_FCR_TXSR)
149
Detlev Zundel200779e2009-04-03 11:53:01 +0200150/*
151 * These are the definitions for the Modem Control Register
152 */
153#define UART_MCR_DTR 0x01 /* DTR */
154#define UART_MCR_RTS 0x02 /* RTS */
155#define UART_MCR_OUT1 0x04 /* Out 1 */
156#define UART_MCR_OUT2 0x08 /* Out 2 */
157#define UART_MCR_LOOP 0x10 /* Enable loopback test mode */
Karicheri, Muralidharand57dee52014-04-09 15:38:46 -0400158#define UART_MCR_AFE 0x20 /* Enable auto-RTS/CTS */
wdenk717b5aa2002-04-27 11:09:31 +0000159
Detlev Zundel200779e2009-04-03 11:53:01 +0200160#define UART_MCR_DMA_EN 0x04
161#define UART_MCR_TX_DFR 0x08
wdenk717b5aa2002-04-27 11:09:31 +0000162
Detlev Zundel200779e2009-04-03 11:53:01 +0200163/*
164 * These are the definitions for the Line Control Register
165 *
166 * Note: if the word length is 5 bits (UART_LCR_WLEN5), then setting
167 * UART_LCR_STOP will select 1.5 stop bits, not 2 stop bits.
168 */
169#define UART_LCR_WLS_MSK 0x03 /* character length select mask */
170#define UART_LCR_WLS_5 0x00 /* 5 bit character length */
171#define UART_LCR_WLS_6 0x01 /* 6 bit character length */
172#define UART_LCR_WLS_7 0x02 /* 7 bit character length */
173#define UART_LCR_WLS_8 0x03 /* 8 bit character length */
Simon Glassf8df9d02011-10-15 19:14:09 +0000174#define UART_LCR_STB 0x04 /* # stop Bits, off=1, on=1.5 or 2) */
Detlev Zundel200779e2009-04-03 11:53:01 +0200175#define UART_LCR_PEN 0x08 /* Parity eneble */
176#define UART_LCR_EPS 0x10 /* Even Parity Select */
177#define UART_LCR_STKP 0x20 /* Stick Parity */
178#define UART_LCR_SBRK 0x40 /* Set Break */
179#define UART_LCR_BKSE 0x80 /* Bank select enable */
180#define UART_LCR_DLAB 0x80 /* Divisor latch access bit */
181
182/*
183 * These are the definitions for the Line Status Register
184 */
185#define UART_LSR_DR 0x01 /* Data ready */
186#define UART_LSR_OE 0x02 /* Overrun */
187#define UART_LSR_PE 0x04 /* Parity error */
188#define UART_LSR_FE 0x08 /* Framing error */
189#define UART_LSR_BI 0x10 /* Break */
190#define UART_LSR_THRE 0x20 /* Xmit holding register empty */
191#define UART_LSR_TEMT 0x40 /* Xmitter empty */
192#define UART_LSR_ERR 0x80 /* Error */
193
194#define UART_MSR_DCD 0x80 /* Data Carrier Detect */
195#define UART_MSR_RI 0x40 /* Ring Indicator */
196#define UART_MSR_DSR 0x20 /* Data Set Ready */
197#define UART_MSR_CTS 0x10 /* Clear to Send */
198#define UART_MSR_DDCD 0x08 /* Delta DCD */
199#define UART_MSR_TERI 0x04 /* Trailing edge ring indicator */
200#define UART_MSR_DDSR 0x02 /* Delta DSR */
201#define UART_MSR_DCTS 0x01 /* Delta CTS */
202
203/*
204 * These are the definitions for the Interrupt Identification Register
205 */
206#define UART_IIR_NO_INT 0x01 /* No interrupts pending */
207#define UART_IIR_ID 0x06 /* Mask for the interrupt ID */
208
209#define UART_IIR_MSI 0x00 /* Modem status interrupt */
210#define UART_IIR_THRI 0x02 /* Transmitter holding register empty */
211#define UART_IIR_RDI 0x04 /* Receiver data interrupt */
212#define UART_IIR_RLSI 0x06 /* Receiver line status interrupt */
213
214/*
215 * These are the definitions for the Interrupt Enable Register
216 */
217#define UART_IER_MSI 0x08 /* Enable Modem status interrupt */
218#define UART_IER_RLSI 0x04 /* Enable receiver line status interrupt */
219#define UART_IER_THRI 0x02 /* Enable Transmitter holding register int. */
220#define UART_IER_RDI 0x01 /* Enable receiver data interrupt */
221
wdenk717b5aa2002-04-27 11:09:31 +0000222/* useful defaults for LCR */
Detlev Zundel200779e2009-04-03 11:53:01 +0200223#define UART_LCR_8N1 0x03
wdenk717b5aa2002-04-27 11:09:31 +0000224
Simon Glass2d6bf752020-12-22 19:30:19 -0700225void ns16550_init(struct ns16550 *com_port, int baud_divisor);
226void ns16550_putc(struct ns16550 *com_port, char c);
227char ns16550_getc(struct ns16550 *com_port);
228int ns16550_tstc(struct ns16550 *com_port);
229void ns16550_reinit(struct ns16550 *com_port, int baud_divisor);
Simon Glassfa54eb12014-09-04 16:27:32 -0600230
231/**
232 * ns16550_calc_divisor() - calculate the divisor given clock and baud rate
233 *
234 * Given the UART input clock and required baudrate, calculate the divisor
235 * that should be used.
236 *
237 * @port: UART port
238 * @clock: UART input clock speed in Hz
239 * @baudrate: Required baud rate
Heinrich Schuchardt185f8122022-01-19 18:05:50 +0100240 * Return: baud rate divisor that should be used
Simon Glassfa54eb12014-09-04 16:27:32 -0600241 */
Simon Glassd30c7202020-12-22 19:30:18 -0700242int ns16550_calc_divisor(struct ns16550 *port, int clock, int baudrate);
Simon Glass12e431b2014-09-04 16:27:34 -0600243
244/**
Simon Glassd1998a92020-12-03 16:55:21 -0700245 * ns16550_serial_of_to_plat() - convert DT to platform data
Simon Glass12e431b2014-09-04 16:27:34 -0600246 *
247 * Decode a device tree node for an ns16550 device. This includes the
248 * register base address and register shift properties. The caller must set
249 * up the clock frequency.
250 *
251 * @dev: dev to decode platform data for
252 * @return: 0 if OK, -EINVAL on error
253 */
Simon Glassd1998a92020-12-03 16:55:21 -0700254int ns16550_serial_of_to_plat(struct udevice *dev);
Simon Glass12e431b2014-09-04 16:27:34 -0600255
256/**
257 * ns16550_serial_probe() - probe a serial port
258 *
259 * This sets up the serial port ready for use, except for the baud rate
Heinrich Schuchardt185f8122022-01-19 18:05:50 +0100260 * Return: 0, or -ve on error
Simon Glass12e431b2014-09-04 16:27:34 -0600261 */
262int ns16550_serial_probe(struct udevice *dev);
263
264/**
265 * struct ns16550_serial_ops - ns16550 serial operations
266 *
267 * These should be used by the client driver for the driver's 'ops' member
268 */
269extern const struct dm_serial_ops ns16550_serial_ops;
Simon Glassd30c7202020-12-22 19:30:18 -0700270
271#endif /* __ns16550_h */