blob: 3be2f8ef33c77edf735297112559d9ca0d9091ff [file] [log] [blame]
Alison Wang186fc4d2012-10-18 19:25:52 +00001/*
2 * Configuation settings for the Freescale MCF54418 TWR board.
3 *
4 * Copyright 2010-2012 Freescale Semiconductor, Inc.
5 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
6 *
7 * See file CREDITS for list of people who contributed to this
8 * project.
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 * MA 02111-1307 USA
24 */
25
26/*
27 * board/config.h - configuration options, board specific
28 */
29
30#ifndef _M54418TWR_H
31#define _M54418TWR_H
32
33/*
34 * High Level Configuration Options
35 * (easy to change)
36 */
37#define CONFIG_MCF5441x /* define processor family */
38#define CONFIG_M54418 /* define processor type */
39#define CONFIG_M54418TWR /* M54418TWR board */
40
41#define CONFIG_MCFUART
42#define CONFIG_SYS_UART_PORT (0)
43#define CONFIG_BAUDRATE 115200
44#define CONFIG_SYS_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 }
45
46#undef CONFIG_WATCHDOG
47
48#define CONFIG_TIMESTAMP /* Print image info with timestamp */
49
50/*
51 * BOOTP options
52 */
53#define CONFIG_BOOTP_BOOTFILESIZE
54#define CONFIG_BOOTP_BOOTPATH
55#define CONFIG_BOOTP_GATEWAY
56#define CONFIG_BOOTP_HOSTNAME
57
58/* Command line configuration */
59#include <config_cmd_default.h>
60
61#define CONFIG_CMD_BOOTD
62#define CONFIG_CMD_CACHE
63#undef CONFIG_CMD_DATE
64#define CONFIG_CMD_DHCP
65#define CONFIG_CMD_ELF
66#undef CONFIG_CMD_FLASH
67#undef CONFIG_CMD_I2C
68#undef CONFIG_CMD_JFFS2
69#undef CONFIG_CMD_UBI
70#define CONFIG_CMD_MEMORY
71#define CONFIG_CMD_MISC
72#define CONFIG_CMD_MII
73#undef CONFIG_CMD_NAND
74#undef CONFIG_CMD_NAND_YAFFS
75#define CONFIG_CMD_NET
76#define CONFIG_CMD_NFS
77#define CONFIG_CMD_PING
78#define CONFIG_CMD_REGINFO
79#define CONFIG_CMD_SPI
80#define CONFIG_CMD_SF
81#undef CONFIG_CMD_IMLS
82
83#undef CONFIG_CMD_LOADB
84#undef CONFIG_CMD_LOADS
85
86/*
87 * NAND FLASH
88 */
89#ifdef CONFIG_CMD_NAND
90#define CONFIG_JFFS2_NAND
91#define CONFIG_NAND_FSL_NFC
92#define CONFIG_SYS_NAND_BASE 0xFC0FC000
93#define CONFIG_SYS_MAX_NAND_DEVICE 1
94#define NAND_MAX_CHIPS CONFIG_SYS_MAX_NAND_DEVICE
95#define CONFIG_SYS_NAND_SELECT_DEVICE
96#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
97#endif
98
99/* Network configuration */
100#define CONFIG_MCFFEC
101#ifdef CONFIG_MCFFEC
102#define CONFIG_NET_MULTI 1
103#define CONFIG_MII 1
104#define CONFIG_MII_INIT 1
105#define CONFIG_SYS_DISCOVER_PHY
106#define CONFIG_SYS_RX_ETH_BUFFER 2
107#define CONFIG_SYS_FAULT_ECCONFIG_SYS_NO_FLASHHO_LINK_DOWN
108#define CONFIG_SYS_TX_ETH_BUFFER 2
109#define CONFIG_HAS_ETH1
110
111#define CONFIG_SYS_FEC0_PINMUX 0
112#define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE
113#define CONFIG_SYS_FEC1_PINMUX 0
114#define CONFIG_SYS_FEC1_MIIBASE CONFIG_SYS_FEC0_MIIBASE
115#define MCFFEC_TOUT_LOOP 50000
116#define CONFIG_SYS_FEC0_PHYADDR 0
117#define CONFIG_SYS_FEC1_PHYADDR 1
118
119#define CONFIG_BOOTDELAY 2 /* autoboot after 5 seconds */
120
121#ifdef CONFIG_SYS_NAND_BOOT
122#define CONFIG_BOOTARGS "root=/dev/mtdblock2 rw rootfstype=jffs2 " \
123 "mtdparts=NAND:1M(u-boot)ro,7M(kernel)ro," \
124 "-(jffs2) console=ttyS0,115200"
125#else
126#define CONFIG_BOOTARGS "root=/dev/nfs rw nfsroot=" \
127 __stringify(CONFIG_SERVERIP) ":/tftpboot/" \
128 __stringify(CONFIG_IPADDR) " ip=" \
129 __stringify(CONFIG_IPADDR) ":" \
130 __stringify(CONFIG_SERVERIP)":" \
131 __stringify(CONFIG_GATEWAYIP)": " \
132 __stringify(CONFIG_NETMASK) \
133 "::eth0:off:rw console=ttyS0,115200"
134#endif
135
136#define CONFIG_ETHADDR 00:e0:0c:bc:e5:60
137#define CONFIG_ETH1ADDR 00:e0:0c:bc:e5:61
138#define CONFIG_ETHPRIME "FEC0"
139#define CONFIG_IPADDR 192.168.1.2
140#define CONFIG_NETMASK 255.255.255.0
141#define CONFIG_SERVERIP 192.168.1.1
142#define CONFIG_GATEWAYIP 192.168.1.1
143
144#define CONFIG_OVERWRITE_ETHADDR_ONCE
145#define CONFIG_SYS_FEC_BUF_USE_SRAM
146/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
147#ifndef CONFIG_SYS_DISCOVER_PHY
148#define FECDUPLEX FULL
149#define FECSPEED _100BASET
150#define LINKSTATUS 1
151#else
152#define LINKSTATUS 0
153#ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
154#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
155#endif
156#endif /* CONFIG_SYS_DISCOVER_PHY */
157#endif
158
159#define CONFIG_HOSTNAME M54418TWR
160
161#if defined(CONFIG_CF_SBF)
162/* ST Micro serial flash */
163#define CONFIG_SYS_LOAD_ADDR2 0x40010007
164#define CONFIG_EXTRA_ENV_SETTINGS \
165 "netdev=eth0\0" \
166 "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \
167 "loadaddr=0x40010000\0" \
168 "sbfhdr=sbfhdr.bin\0" \
169 "uboot=u-boot.bin\0" \
170 "load=tftp ${loadaddr} ${sbfhdr};" \
171 "tftp " __stringify(CONFIG_SYS_LOAD_ADDR2) " ${uboot} \0" \
172 "upd=run load; run prog\0" \
173 "prog=sf probe 0:1 1000000 3;" \
174 "sf erase 0 40000;" \
175 "sf write ${loadaddr} 0 40000;" \
176 "save\0" \
177 ""
178#elif defined(CONFIG_SYS_NAND_BOOT)
179#define CONFIG_EXTRA_ENV_SETTINGS \
180 "netdev=eth0\0" \
181 "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \
182 "loadaddr=0x40010000\0" \
183 "u-boot=u-boot.bin\0" \
184 "load=tftp ${loadaddr} ${u-boot};\0" \
185 "upd=run load; run prog\0" \
186 "prog=nand device 0;" \
187 "nand erase 0 40000;" \
188 "nb_update ${loadaddr} ${filesize};" \
189 "save\0" \
190 ""
191#else
192#define CONFIG_SYS_UBOOT_END 0x3FFFF
193#define CONFIG_EXTRA_ENV_SETTINGS \
194 "netdev=eth0\0" \
195 "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \
196 "loadaddr=40010000\0" \
197 "u-boot=u-boot.bin\0" \
198 "load=tftp ${loadaddr) ${u-boot}\0" \
199 "upd=run load; run prog\0" \
200 "prog=prot off mram" " ;" \
201 "cp.b ${loadaddr} 0 ${filesize};" \
202 "save\0" \
203 ""
204#endif
205
206/* Realtime clock */
207#undef CONFIG_MCFRTC
208#define CONFIG_RTC_MCFRRTC
209#define CONFIG_SYS_MCFRRTC_BASE 0xFC0A8000
210
211/* Timer */
212#define CONFIG_MCFTMR
213#undef CONFIG_MCFPIT
214
215/* I2c */
216#undef CONFIG_FSL_I2C
217#undef CONFIG_HARD_I2C /* I2C with hardware support */
218#undef CONFIG_SOFT_I2C /* I2C bit-banged */
219/* I2C speed and slave address */
220#define CONFIG_SYS_I2C_SPEED 80000
221#define CONFIG_SYS_I2C_SLAVE 0x7F
222#define CONFIG_SYS_I2C_OFFSET 0x58000
223#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
224
225/* DSPI and Serial Flash */
226#define CONFIG_CF_SPI
227#define CONFIG_CF_DSPI
228#define CONFIG_SERIAL_FLASH
229#define CONFIG_HARD_SPI
230#define CONFIG_SYS_SBFHDR_SIZE 0x7
231#ifdef CONFIG_CMD_SPI
232# define CONFIG_SPI_FLASH
233# define CONFIG_SPI_FLASH_ATMEL
234
235# define CONFIG_SYS_DSPI_CTAR0 (DSPI_CTAR_TRSZ(7) | \
236 DSPI_CTAR_PCSSCK_1CLK | \
237 DSPI_CTAR_PASC(0) | \
238 DSPI_CTAR_PDT(0) | \
239 DSPI_CTAR_CSSCK(0) | \
240 DSPI_CTAR_ASC(0) | \
241 DSPI_CTAR_DT(1))
242# define CONFIG_SYS_DSPI_CTAR1 (CONFIG_SYS_DSPI_CTAR0)
243# define CONFIG_SYS_DSPI_CTAR2 (CONFIG_SYS_DSPI_CTAR0)
244#endif
245
246/* Input, PCI, Flexbus, and VCO */
247#define CONFIG_EXTRA_CLOCK
248
249#define CONFIG_PRAM 2048 /* 2048 KB */
250
251/* HUSH */
252#define CONFIG_SYS_HUSH_PARSER 1
253#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
254
255#define CONFIG_SYS_PROMPT "-> "
256#define CONFIG_SYS_LONGHELP /* undef to save memory */
257
258#if defined(CONFIG_CMD_KGDB)
259#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
260#else
261#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
262#endif
263/* Print Buffer Size */
264#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
265 sizeof(CONFIG_SYS_PROMPT) + 16)
266#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
267/* Boot Argument Buffer Size */
268#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
269
270#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x10000)
271
272#define CONFIG_SYS_HZ 1000
273
274#define CONFIG_SYS_MBAR 0xFC000000
275
276/*
277 * Low Level Configuration Settings
278 * (address mappings, register initial values, etc.)
279 * You should know what you are doing if you make changes here.
280 */
281
282/*-----------------------------------------------------------------------
283 * Definitions for initial stack pointer and data area (in DPRAM)
284 */
285#define CONFIG_SYS_INIT_RAM_ADDR 0x80000000
286/* End of used area in internal SRAM */
287#define CONFIG_SYS_INIT_RAM_SIZE 0x10000
288#define CONFIG_SYS_INIT_RAM_CTRL 0x221
289/* size in bytes reserved for initial data */
290#define CONFIG_SYS_GBL_DATA_SIZE 256
291#define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - \
292 CONFIG_SYS_GBL_DATA_SIZE) - 32)
293#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
294#define CONFIG_SYS_SBFHDR_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - 32)
295
296/*-----------------------------------------------------------------------
297 * Start addresses for the final memory configuration
298 * (Set up by the startup code)
299 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
300 */
301#define CONFIG_SYS_SDRAM_BASE 0x40000000
302#define CONFIG_SYS_SDRAM_SIZE 128 /* SDRAM size in MB */
303
304#define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE + 0x400)
305#define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20)
306#define CONFIG_SYS_DRAM_TEST
307
308#if defined(CONFIG_CF_SBF) || defined(CONFIG_SYS_NAND_BOOT)
309#define CONFIG_SERIAL_BOOT
310#endif
311
312#if defined(CONFIG_SERIAL_BOOT)
313#define CONFIG_SYS_MONITOR_BASE (TEXT_BASE + 0x400)
314#else
315#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
316#endif
317
318#define CONFIG_SYS_BOOTPARAMS_LEN (64 * 1024)
319/* Reserve 256 kB for Monitor */
320#define CONFIG_SYS_MONITOR_LEN (256 << 10)
321/* Reserve 256 kB for malloc() */
322#define CONFIG_SYS_MALLOC_LEN (256 << 10)
323
324/*
325 * For booting Linux, the board info and command line data
326 * have to be in the first 8 MB of memory, since this is
327 * the maximum mapped by the Linux kernel during initialization ??
328 */
329/* Initial Memory map for Linux */
330#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + \
331 (CONFIG_SYS_SDRAM_SIZE << 20))
332
333/* Configuration for environment
334 * Environment is embedded in u-boot in the second sector of the flash
335 */
336#if !defined(CONFIG_SERIAL_BOOT) /*MRAM boot*/
337#define CONFIG_SYS_NO_FLASH
338#define CONFIG_ENV_IS_IN_MRAM 1
339#define CONFIG_ENV_ADDR (0x40000 - 0x1000) /*MRAM size 40000*/
340#define CONFIG_ENV_SIZE 0x1000
341#endif
342
343#if defined(CONFIG_CF_SBF)
344#define CONFIG_SYS_NO_FLASH
345#define CONFIG_ENV_IS_IN_SPI_FLASH 1
346#define CONFIG_ENV_SPI_CS 1
347#define CONFIG_ENV_OFFSET 0x40000
348#define CONFIG_ENV_SIZE 0x2000
349#define CONFIG_ENV_SECT_SIZE 0x10000
350#endif
351#if defined(CONFIG_SYS_NAND_BOOT)
352#define CONFIG_SYS_NO_FLASH
Jason Jinb765fce2012-10-25 15:27:37 +0800353#define CONFIG_ENV_IS_NOWHERE
Alison Wang186fc4d2012-10-18 19:25:52 +0000354#define CONFIG_ENV_OFFSET 0x80000
355#define CONFIG_ENV_SIZE 0x20000
356#define CONFIG_ENV_SECT_SIZE 0x20000
357#endif
358#undef CONFIG_ENV_OVERWRITE
359
360/* FLASH organization */
361#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE
362
363#undef CONFIG_SYS_FLASH_CFI
364#ifdef CONFIG_SYS_FLASH_CFI
365
366#define CONFIG_FLASH_CFI_DRIVER 1
367/* Max size that the board might have */
368#define CONFIG_SYS_FLASH_SIZE 0x1000000
369#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
370/* max number of memory banks */
371#define CONFIG_SYS_MAX_FLASH_BANKS 1
372/* max number of sectors on one chip */
373#define CONFIG_SYS_MAX_FLASH_SECT 270
374/* "Real" (hardware) sectors protection */
375#define CONFIG_SYS_FLASH_PROTECTION
376#define CONFIG_SYS_FLASH_CHECKSUM
377#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_CS0_BASE }
378#else
379/* max number of sectors on one chip */
380#define CONFIG_SYS_MAX_FLASH_SECT 270
381/* max number of sectors on one chip */
382#define CONFIG_SYS_MAX_FLASH_BANKS 0
383#endif
384
385/*
386 * This is setting for JFFS2 support in u-boot.
387 * NOTE: Enable CONFIG_CMD_JFFS2 for JFFS2 support.
388 */
389#ifdef CONFIG_CMD_JFFS2
390#define CONFIG_JFFS2_DEV "nand0"
391#define CONFIG_JFFS2_PART_OFFSET (0x800000)
392#define CONFIG_CMD_MTDPARTS
393#define CONFIG_MTD_DEVICE
394#define MTDIDS_DEFAULT "nand0=m54418twr.nand"
395
396#define MTDPARTS_DEFAULT "mtdparts=m54418twr.nand:1m(data)," \
397 "7m(kernel)," \
398 "-(rootfs)"
399
400#endif
401
402#ifdef CONFIG_CMD_UBI
403#define CONFIG_CMD_MTDPARTS
404#define CONFIG_MTD_DEVICE /* needed for mtdparts command */
405#define CONFIG_MTD_PARTITIONS /* mtdparts and UBI support */
406#define CONFIG_RBTREE
407#define MTDIDS_DEFAULT "nand0=NAND"
408#define MTDPARTS_DEFAULT "mtdparts=NAND:1m(u-boot)," \
409 "-(ubi)"
410#endif
411/* Cache Configuration */
412#define CONFIG_SYS_CACHELINE_SIZE 16
413#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
414 CONFIG_SYS_INIT_RAM_SIZE - 8)
415#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
416 CONFIG_SYS_INIT_RAM_SIZE - 4)
417#define CONFIG_SYS_ICACHE_INV (CF_CACR_BCINVA + CF_CACR_ICINVA)
418#define CONFIG_SYS_DCACHE_INV (CF_CACR_DCINVA)
419#define CONFIG_SYS_CACHE_ACR2 (CONFIG_SYS_SDRAM_BASE | \
420 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
421 CF_ACR_EN | CF_ACR_SM_ALL)
422#define CONFIG_SYS_CACHE_ICACR (CF_CACR_BEC | CF_CACR_IEC | \
423 CF_CACR_ICINVA | CF_CACR_EUSP)
424#define CONFIG_SYS_CACHE_DCACR ((CONFIG_SYS_CACHE_ICACR | \
425 CF_CACR_DEC | CF_CACR_DDCM_P | \
426 CF_CACR_DCINVA) & ~CF_CACR_ICINVA)
427
428#define CACR_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
429 CONFIG_SYS_INIT_RAM_SIZE - 12)
430
431/*-----------------------------------------------------------------------
432 * Memory bank definitions
433 */
434/*
435 * CS0 - NOR Flash 16MB
436 * CS1 - Available
437 * CS2 - Available
438 * CS3 - Available
439 * CS4 - Available
440 * CS5 - Available
441 */
442
443 /* Flash */
444#define CONFIG_SYS_CS0_BASE 0x00000000
445#define CONFIG_SYS_CS0_MASK 0x000F0101
446#define CONFIG_SYS_CS0_CTRL 0x00001D60
447
448#endif /* _M54418TWR_H */