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wdenk79fa88f2004-06-07 23:46:25 +00001/*
2 * (C) Copyright 2000-2004
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/*
25 * Pantelis Antoniou, Intracom S.A., panto@intracom.gr
26 * U-Boot port on NetTA4 board
27 */
28
29#ifndef __CONFIG_H
30#define __CONFIG_H
31
32#if !defined(CONFIG_NETTA2_VERSION) || CONFIG_NETTA2_VERSION > 2
33#error Unsupported CONFIG_NETTA2 version
34#endif
35
36/*
37 * High Level Configuration Options
38 * (easy to change)
39 */
40
41#define CONFIG_MPC870 1 /* This is a MPC885 CPU */
42#define CONFIG_NETTA2 1 /* ...on a NetTA2 board */
43
44#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
45#undef CONFIG_8xx_CONS_SMC2
46#undef CONFIG_8xx_CONS_NONE
47
48#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */
49
50/* #define CONFIG_XIN 10000000 */
51#define CONFIG_XIN 50000000
52/* #define MPC8XX_HZ 120000000 */
53#define MPC8XX_HZ 66666666
54
55#define CONFIG_8xx_GCLK_FREQ MPC8XX_HZ
56
57#if 0
58#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
59#else
60#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
61#endif
62
63#undef CONFIG_CLOCKS_IN_MHZ /* clocks NOT passsed to Linux in MHz */
64
65#define CONFIG_PREBOOT "echo;"
66
67#undef CONFIG_BOOTARGS
68#define CONFIG_BOOTCOMMAND \
Wolfgang Denk53677ef2008-05-20 16:00:29 +020069 "tftpboot; " \
70 "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
71 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \
wdenk79fa88f2004-06-07 23:46:25 +000072 "bootm"
73
Wolfgang Denk74de7ae2009-04-01 23:34:12 +020074#define CONFIG_SOURCE
wdenk79fa88f2004-06-07 23:46:25 +000075#define CONFIG_LOADS_ECHO 0 /* echo off for serial download */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020076#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */
wdenk79fa88f2004-06-07 23:46:25 +000077
78#undef CONFIG_WATCHDOG /* watchdog disabled */
79
80#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */
81
82#define CONFIG_STATUS_LED 1 /* Status LED enabled */
83#define CONFIG_BOARD_SPECIFIC_LED /* version has board specific leds */
84
Jon Loeliger7be044e2007-07-09 21:24:19 -050085/*
86 * BOOTP options
87 */
88#define CONFIG_BOOTP_SUBNETMASK
89#define CONFIG_BOOTP_GATEWAY
90#define CONFIG_BOOTP_HOSTNAME
91#define CONFIG_BOOTP_BOOTPATH
92#define CONFIG_BOOTP_BOOTFILESIZE
93#define CONFIG_BOOTP_NISDOMAIN
94
wdenk79fa88f2004-06-07 23:46:25 +000095
96#undef CONFIG_MAC_PARTITION
97#undef CONFIG_DOS_PARTITION
98
99#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
100
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200101#define CONFIG_NET_MULTI 1 /* the only way to get the FEC in */
wdenk79fa88f2004-06-07 23:46:25 +0000102#define FEC_ENET 1 /* eth.c needs it that way... */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200103#undef CONFIG_SYS_DISCOVER_PHY
wdenk79fa88f2004-06-07 23:46:25 +0000104#define CONFIG_MII 1
TsiChung Liew0f3ba7e2008-03-30 01:22:13 -0500105#define CONFIG_MII_INIT 1
wdenk79fa88f2004-06-07 23:46:25 +0000106#define CONFIG_RMII 1 /* use RMII interface */
107
108#define CONFIG_ETHER_ON_FEC1 1
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200109#define CONFIG_FEC1_PHY 8 /* phy address of FEC */
wdenk79fa88f2004-06-07 23:46:25 +0000110#define CONFIG_FEC1_PHY_NORXERR 1
111
112#define CONFIG_ETHER_ON_FEC2 1
113#define CONFIG_FEC2_PHY 4
114#define CONFIG_FEC2_PHY_NORXERR 1
115
116#define CONFIG_ENV_OVERWRITE 1 /* allow modification of vendor params */
117
Jon Loeligere18a1062007-07-08 14:21:43 -0500118
119/*
120 * Command line configuration.
121 */
122#include <config_cmd_default.h>
123
124#define CONFIG_CMD_NAND
125#define CONFIG_CMD_DHCP
126#define CONFIG_CMD_PING
127#define CONFIG_CMD_MII
128#define CONFIG_CMD_CDP
129
wdenk79fa88f2004-06-07 23:46:25 +0000130
131#define CONFIG_BOARD_EARLY_INIT_F 1
132#define CONFIG_MISC_INIT_R
133
wdenk79fa88f2004-06-07 23:46:25 +0000134/*
135 * Miscellaneous configurable options
136 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200137#define CONFIG_SYS_LONGHELP /* undef to save memory */
138#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
wdenk79fa88f2004-06-07 23:46:25 +0000139
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200140#define CONFIG_SYS_HUSH_PARSER 1
141#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
wdenk79fa88f2004-06-07 23:46:25 +0000142
Jon Loeligere18a1062007-07-08 14:21:43 -0500143#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200144#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
wdenk79fa88f2004-06-07 23:46:25 +0000145#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200146#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
wdenk79fa88f2004-06-07 23:46:25 +0000147#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200148#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
149#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
150#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
wdenk79fa88f2004-06-07 23:46:25 +0000151
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200152#define CONFIG_SYS_MEMTEST_START 0x0300000 /* memtest works on */
153#define CONFIG_SYS_MEMTEST_END 0x0700000 /* 3 ... 7 MB in DRAM */
wdenk79fa88f2004-06-07 23:46:25 +0000154
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200155#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
wdenk79fa88f2004-06-07 23:46:25 +0000156
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200157#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
wdenk79fa88f2004-06-07 23:46:25 +0000158
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200159#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
wdenk79fa88f2004-06-07 23:46:25 +0000160
161/*
162 * Low Level Configuration Settings
163 * (address mappings, register initial values, etc.)
164 * You should know what you are doing if you make changes here.
165 */
166/*-----------------------------------------------------------------------
167 * Internal Memory Mapped Register
168 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200169#define CONFIG_SYS_IMMR 0xFF000000
wdenk79fa88f2004-06-07 23:46:25 +0000170
171/*-----------------------------------------------------------------------
172 * Definitions for initial stack pointer and data area (in DPRAM)
173 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200174#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
175#define CONFIG_SYS_INIT_RAM_END 0x3000 /* End of used area in DPRAM */
176#define CONFIG_SYS_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
177#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
178#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
wdenk79fa88f2004-06-07 23:46:25 +0000179
180/*-----------------------------------------------------------------------
181 * Start addresses for the final memory configuration
182 * (Set up by the startup code)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200183 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
wdenk79fa88f2004-06-07 23:46:25 +0000184 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200185#define CONFIG_SYS_SDRAM_BASE 0x00000000
186#define CONFIG_SYS_FLASH_BASE 0x40000000
wdenk79fa88f2004-06-07 23:46:25 +0000187#if defined(DEBUG)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200188#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
wdenk79fa88f2004-06-07 23:46:25 +0000189#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200190#define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
wdenk79fa88f2004-06-07 23:46:25 +0000191#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200192#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
193#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
wdenk79fa88f2004-06-07 23:46:25 +0000194#if CONFIG_NETTA2_VERSION == 2
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200195#define CONFIG_SYS_FLASH_BASE4 0x40080000
wdenk79fa88f2004-06-07 23:46:25 +0000196#endif
197
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200198#define CONFIG_SYS_RESET_ADDRESS 0x80000000
wdenk79fa88f2004-06-07 23:46:25 +0000199
200/*
201 * For booting Linux, the board info and command line data
202 * have to be in the first 8 MB of memory, since this is
203 * the maximum mapped by the Linux kernel during initialization.
204 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200205#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
wdenk79fa88f2004-06-07 23:46:25 +0000206
207/*-----------------------------------------------------------------------
208 * FLASH organization
209 */
210#if CONFIG_NETTA2_VERSION == 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200211#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
wdenk79fa88f2004-06-07 23:46:25 +0000212#elif CONFIG_NETTA2_VERSION == 2
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200213#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
wdenk79fa88f2004-06-07 23:46:25 +0000214#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200215#define CONFIG_SYS_MAX_FLASH_SECT 8 /* max number of sectors on one chip */
wdenk79fa88f2004-06-07 23:46:25 +0000216
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200217#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
218#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
wdenk79fa88f2004-06-07 23:46:25 +0000219
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200220#define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200221#define CONFIG_ENV_SECT_SIZE 0x10000
wdenk79fa88f2004-06-07 23:46:25 +0000222
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200223#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x60000)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200224#define CONFIG_ENV_OFFSET 0
225#define CONFIG_ENV_SIZE 0x4000
wdenk79fa88f2004-06-07 23:46:25 +0000226
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200227#define CONFIG_ENV_ADDR_REDUND (CONFIG_SYS_FLASH_BASE + 0x70000)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200228#define CONFIG_ENV_OFFSET_REDUND 0
229#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
wdenk79fa88f2004-06-07 23:46:25 +0000230
231/*-----------------------------------------------------------------------
232 * Cache Configuration
233 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200234#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
Jon Loeligere18a1062007-07-08 14:21:43 -0500235#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200236#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */
wdenk79fa88f2004-06-07 23:46:25 +0000237#endif
238
239/*-----------------------------------------------------------------------
240 * SYPCR - System Protection Control 11-9
241 * SYPCR can only be written once after reset!
242 *-----------------------------------------------------------------------
243 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
244 */
245#if defined(CONFIG_WATCHDOG)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200246#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
wdenk79fa88f2004-06-07 23:46:25 +0000247 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
248#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200249#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
wdenk79fa88f2004-06-07 23:46:25 +0000250#endif
251
252/*-----------------------------------------------------------------------
253 * SIUMCR - SIU Module Configuration 11-6
254 *-----------------------------------------------------------------------
255 * PCMCIA config., multi-function pin tri-state
256 */
257#ifndef CONFIG_CAN_DRIVER
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200258#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01 | SIUMCR_FRC)
wdenk79fa88f2004-06-07 23:46:25 +0000259#else /* we must activate GPL5 in the SIUMCR for CAN */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200260#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01 | SIUMCR_FRC)
wdenk79fa88f2004-06-07 23:46:25 +0000261#endif /* CONFIG_CAN_DRIVER */
262
263/*-----------------------------------------------------------------------
264 * TBSCR - Time Base Status and Control 11-26
265 *-----------------------------------------------------------------------
266 * Clear Reference Interrupt Status, Timebase freezing enabled
267 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200268#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
wdenk79fa88f2004-06-07 23:46:25 +0000269
270/*-----------------------------------------------------------------------
271 * RTCSC - Real-Time Clock Status and Control Register 11-27
272 *-----------------------------------------------------------------------
273 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200274#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
wdenk79fa88f2004-06-07 23:46:25 +0000275
276/*-----------------------------------------------------------------------
277 * PISCR - Periodic Interrupt Status and Control 11-31
278 *-----------------------------------------------------------------------
279 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
280 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200281#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF)
wdenk79fa88f2004-06-07 23:46:25 +0000282
283/*-----------------------------------------------------------------------
284 * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
285 *-----------------------------------------------------------------------
286 * Reset PLL lock status sticky bit, timer expired status bit and timer
287 * interrupt status bit
288 *
289 */
290
291#if CONFIG_XIN == 10000000
292
293#if MPC8XX_HZ == 120000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200294#define CONFIG_SYS_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
wdenk79fa88f2004-06-07 23:46:25 +0000295 (0 << PLPRCR_S_SHIFT) | (12 << PLPRCR_MFI_SHIFT) | (0 << PLPRCR_PDF_SHIFT) | \
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200296 PLPRCR_TEXPS)
wdenk79fa88f2004-06-07 23:46:25 +0000297#elif MPC8XX_HZ == 100000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200298#define CONFIG_SYS_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
wdenk79fa88f2004-06-07 23:46:25 +0000299 (0 << PLPRCR_S_SHIFT) | (10 << PLPRCR_MFI_SHIFT) | (0 << PLPRCR_PDF_SHIFT) | \
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200300 PLPRCR_TEXPS)
wdenk79fa88f2004-06-07 23:46:25 +0000301#elif MPC8XX_HZ == 50000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200302#define CONFIG_SYS_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
wdenk79fa88f2004-06-07 23:46:25 +0000303 (1 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (3 << PLPRCR_PDF_SHIFT) | \
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200304 PLPRCR_TEXPS)
wdenk79fa88f2004-06-07 23:46:25 +0000305#elif MPC8XX_HZ == 25000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200306#define CONFIG_SYS_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
wdenk79fa88f2004-06-07 23:46:25 +0000307 (2 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (3 << PLPRCR_PDF_SHIFT) | \
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200308 PLPRCR_TEXPS)
wdenk79fa88f2004-06-07 23:46:25 +0000309#elif MPC8XX_HZ == 40000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200310#define CONFIG_SYS_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
wdenk79fa88f2004-06-07 23:46:25 +0000311 (1 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (4 << PLPRCR_PDF_SHIFT) | \
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200312 PLPRCR_TEXPS)
wdenk79fa88f2004-06-07 23:46:25 +0000313#elif MPC8XX_HZ == 75000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200314#define CONFIG_SYS_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
wdenk79fa88f2004-06-07 23:46:25 +0000315 (1 << PLPRCR_S_SHIFT) | (15 << PLPRCR_MFI_SHIFT) | (0 << PLPRCR_PDF_SHIFT) | \
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200316 PLPRCR_TEXPS)
wdenk79fa88f2004-06-07 23:46:25 +0000317#else
318#error unsupported CPU freq for XIN = 10MHz
319#endif
320
321#elif CONFIG_XIN == 50000000
322
323#if MPC8XX_HZ == 120000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200324#define CONFIG_SYS_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
wdenk79fa88f2004-06-07 23:46:25 +0000325 (0 << PLPRCR_S_SHIFT) | (12 << PLPRCR_MFI_SHIFT) | (4 << PLPRCR_PDF_SHIFT) | \
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200326 PLPRCR_TEXPS)
wdenk79fa88f2004-06-07 23:46:25 +0000327#elif MPC8XX_HZ == 100000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200328#define CONFIG_SYS_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
wdenk79fa88f2004-06-07 23:46:25 +0000329 (0 << PLPRCR_S_SHIFT) | (6 << PLPRCR_MFI_SHIFT) | (2 << PLPRCR_PDF_SHIFT) | \
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200330 PLPRCR_TEXPS)
wdenk79fa88f2004-06-07 23:46:25 +0000331#elif MPC8XX_HZ == 66666666
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200332#define CONFIG_SYS_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
wdenk79fa88f2004-06-07 23:46:25 +0000333 (1 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (2 << PLPRCR_PDF_SHIFT) | \
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200334 PLPRCR_TEXPS)
wdenk79fa88f2004-06-07 23:46:25 +0000335#else
336#error unsupported CPU freq for XIN = 50MHz
337#endif
338
339#else
340
341#error unsupported XIN freq
342#endif
343
344
345/*
346 *-----------------------------------------------------------------------
347 * SCCR - System Clock and reset Control Register 15-27
348 *-----------------------------------------------------------------------
349 * Set clock output, timebase and RTC source and divider,
350 * power management and some other internal clocks
351 *
352 * Note: When TBS == 0 the timebase is independent of current cpu clock.
353 */
354
355#define SCCR_MASK SCCR_EBDF11
356#if MPC8XX_HZ > 66666666
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200357#define CONFIG_SYS_SCCR (/* SCCR_TBS | */ SCCR_CRQEN | \
wdenk79fa88f2004-06-07 23:46:25 +0000358 SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
359 SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
360 SCCR_DFALCD00 | SCCR_EBDF01)
361#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200362#define CONFIG_SYS_SCCR (/* SCCR_TBS | */ SCCR_CRQEN | \
wdenk79fa88f2004-06-07 23:46:25 +0000363 SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
364 SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
365 SCCR_DFALCD00)
366#endif
367
368/*-----------------------------------------------------------------------
369 *
370 *-----------------------------------------------------------------------
371 *
372 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200373/*#define CONFIG_SYS_DER 0x2002000F*/
374#define CONFIG_SYS_DER 0
wdenk79fa88f2004-06-07 23:46:25 +0000375
376/*
377 * Init Memory Controller:
378 *
379 * BR0/1 and OR0/1 (FLASH)
380 */
381
382#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
383
384/* used to re-map FLASH both when starting from SRAM or FLASH:
385 * restrict access enough to keep SRAM working (if any)
386 * but not too much to meddle with FLASH accesses
387 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200388#define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */
389#define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */
wdenk79fa88f2004-06-07 23:46:25 +0000390
391/* FLASH timing: ACS = 11, TRLX = 0, CSNT = 1, SCY = 5, EHTR = 1 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200392#define CONFIG_SYS_OR_TIMING_FLASH (OR_CSNT_SAM | OR_BI | OR_SCY_5_CLK | OR_TRLX)
wdenk79fa88f2004-06-07 23:46:25 +0000393
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200394#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
395#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
396#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_8 | BR_V )
wdenk79fa88f2004-06-07 23:46:25 +0000397
398#if CONFIG_NETTA2_VERSION == 2
399
400#define FLASH_BASE4_PRELIM 0x40080000 /* FLASH bank #1 */
401
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200402#define CONFIG_SYS_OR4_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
403#define CONFIG_SYS_OR4_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
404#define CONFIG_SYS_BR4_PRELIM ((FLASH_BASE4_PRELIM & BR_BA_MSK) | BR_PS_8 | BR_V )
wdenk79fa88f2004-06-07 23:46:25 +0000405
406#endif
407
408/*
409 * BR3 and OR3 (SDRAM)
410 *
411 */
412#define SDRAM_BASE3_PRELIM 0x00000000 /* SDRAM bank #0 */
413#define SDRAM_MAX_SIZE (256 << 20) /* max 256MB per bank */
414
415/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200416#define CONFIG_SYS_OR_TIMING_SDRAM (OR_CSNT_SAM | OR_G5LS)
wdenk79fa88f2004-06-07 23:46:25 +0000417
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200418#define CONFIG_SYS_OR3_PRELIM ((0xFFFFFFFFLU & ~(SDRAM_MAX_SIZE - 1)) | CONFIG_SYS_OR_TIMING_SDRAM)
419#define CONFIG_SYS_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMB | BR_PS_32 | BR_V)
wdenk79fa88f2004-06-07 23:46:25 +0000420
421/*
422 * Memory Periodic Timer Prescaler
423 */
424
425/*
426 * Memory Periodic Timer Prescaler
427 *
428 * The Divider for PTA (refresh timer) configuration is based on an
429 * example SDRAM configuration (64 MBit, one bank). The adjustment to
430 * the number of chip selects (NCS) and the actually needed refresh
431 * rate is done by setting MPTPR.
432 *
433 * PTA is calculated from
434 * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS)
435 *
436 * gclk CPU clock (not bus clock!)
437 * Trefresh Refresh cycle * 4 (four word bursts used)
438 *
439 * 4096 Rows from SDRAM example configuration
440 * 1000 factor s -> ms
441 * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration
442 * 4 Number of refresh cycles per period
443 * 64 Refresh cycle in ms per number of rows
444 * --------------------------------------------
445 * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000
446 *
447 * 50 MHz => 50.000.000 / Divider = 98
448 * 66 Mhz => 66.000.000 / Divider = 129
449 * 80 Mhz => 80.000.000 / Divider = 156
450 */
451
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200452#define CONFIG_SYS_MAMR_PTA 234
wdenk79fa88f2004-06-07 23:46:25 +0000453
454/*
455 * For 16 MBit, refresh rates could be 31.3 us
456 * (= 64 ms / 2K = 125 / quad bursts).
457 * For a simpler initialization, 15.6 us is used instead.
458 *
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200459 * #define CONFIG_SYS_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks
460 * #define CONFIG_SYS_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank
wdenk79fa88f2004-06-07 23:46:25 +0000461 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200462#define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
463#define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */
wdenk79fa88f2004-06-07 23:46:25 +0000464
465/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200466#define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */
467#define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
wdenk79fa88f2004-06-07 23:46:25 +0000468
469/*
470 * MAMR settings for SDRAM
471 */
472
473/* 8 column SDRAM */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200474#define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
wdenk79fa88f2004-06-07 23:46:25 +0000475 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
476 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
477
478/* 9 column SDRAM */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200479#define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
wdenk79fa88f2004-06-07 23:46:25 +0000480 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
481 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
482
483/*
484 * Internal Definitions
485 *
486 * Boot Flags
487 */
488#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
489#define BOOTFLAG_WARM 0x02 /* Software reboot */
490
wdenk79fa88f2004-06-07 23:46:25 +0000491#define CONFIG_LAST_STAGE_INIT /* needed to reset the damn phys */
492
493/****************************************************************/
494
495#define DSP_SIZE 0x00010000 /* 64K */
496#define NAND_SIZE 0x00010000 /* 64K */
497
498#define DSP_BASE 0xF1000000
499#define NAND_BASE 0xF1010000
500
501/****************************************************************/
502
503/* NAND */
Jean-Christophe PLAGNIOL-VILLARDcc4a0ce2008-08-13 01:40:43 +0200504#define CONFIG_NAND_LEGACY
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200505#define CONFIG_SYS_NAND_BASE NAND_BASE
wdenk79fa88f2004-06-07 23:46:25 +0000506#define CONFIG_MTD_NAND_ECC_JFFS2
507#define CONFIG_MTD_NAND_VERIFY_WRITE
508#define CONFIG_MTD_NAND_UNSAFE
509
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200510#define CONFIG_SYS_MAX_NAND_DEVICE 1
wdenk79fa88f2004-06-07 23:46:25 +0000511
512#define SECTORSIZE 512
513#define ADDR_COLUMN 1
514#define ADDR_PAGE 2
515#define ADDR_COLUMN_PAGE 3
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200516#define NAND_ChipID_UNKNOWN 0x00
wdenk79fa88f2004-06-07 23:46:25 +0000517#define NAND_MAX_FLOORS 1
wdenk79fa88f2004-06-07 23:46:25 +0000518
519/* ALE = PD17, CLE = PE18, CE = PE20, F_RY_BY = PE31 */
520#define NAND_DISABLE_CE(nand) \
521 do { \
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200522 (((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pedat) |= (1 << (31 - 20)); \
wdenk79fa88f2004-06-07 23:46:25 +0000523 } while(0)
524
525#define NAND_ENABLE_CE(nand) \
526 do { \
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200527 (((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pedat) &= ~(1 << (31 - 20)); \
wdenk79fa88f2004-06-07 23:46:25 +0000528 } while(0)
529
530#define NAND_CTL_CLRALE(nandptr) \
531 do { \
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200532 (((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pedat) &= ~(1 << (31 - 17)); \
wdenk79fa88f2004-06-07 23:46:25 +0000533 } while(0)
534
535#define NAND_CTL_SETALE(nandptr) \
536 do { \
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200537 (((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pedat) |= (1 << (31 - 17)); \
wdenk79fa88f2004-06-07 23:46:25 +0000538 } while(0)
539
540#define NAND_CTL_CLRCLE(nandptr) \
541 do { \
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200542 (((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pedat) &= ~(1 << (31 - 18)); \
wdenk79fa88f2004-06-07 23:46:25 +0000543 } while(0)
544
545#define NAND_CTL_SETCLE(nandptr) \
546 do { \
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200547 (((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pedat) |= (1 << (31 - 18)); \
wdenk79fa88f2004-06-07 23:46:25 +0000548 } while(0)
549
550#if CONFIG_NETTA2_VERSION == 1
551#define NAND_WAIT_READY(nand) \
552 do { \
553 int _tries = 0; \
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200554 while ((((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pedat & (1 << (31 - 31))) == 0) \
wdenk79fa88f2004-06-07 23:46:25 +0000555 if (++_tries > 100000) \
556 break; \
557 } while (0)
558#elif CONFIG_NETTA2_VERSION == 2
559#define NAND_WAIT_READY(nand) \
560 do { \
561 int _tries = 0; \
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200562 while ((((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcdat & (1 << (15 - 15))) == 0) \
wdenk79fa88f2004-06-07 23:46:25 +0000563 if (++_tries > 100000) \
564 break; \
565 } while (0)
566#endif
567
568#define WRITE_NAND_COMMAND(d, adr) \
569 do { \
570 *(volatile unsigned char *)((unsigned long)(adr)) = (unsigned char)(d); \
571 } while(0)
572
573#define WRITE_NAND_ADDRESS(d, adr) \
574 do { \
575 *(volatile unsigned char *)((unsigned long)(adr)) = (unsigned char)(d); \
576 } while(0)
577
578#define WRITE_NAND(d, adr) \
579 do { \
580 *(volatile unsigned char *)((unsigned long)(adr)) = (unsigned char)(d); \
581 } while(0)
582
583#define READ_NAND(adr) \
584 ((unsigned char)(*(volatile unsigned char *)(unsigned long)(adr)))
585
586/*****************************************************************************/
587
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200588#define CONFIG_SYS_DIRECT_FLASH_TFTP
589#define CONFIG_SYS_DIRECT_NAND_TFTP
wdenk79fa88f2004-06-07 23:46:25 +0000590
591/*****************************************************************************/
592
593#if CONFIG_NETTA2_VERSION == 1
594#define STATUS_LED_BIT 0x00000008 /* bit 28 */
595#elif CONFIG_NETTA2_VERSION == 2
596#define STATUS_LED_BIT 0x00000080 /* bit 24 */
597#endif
598
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200599#define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 2)
wdenk79fa88f2004-06-07 23:46:25 +0000600#define STATUS_LED_STATE STATUS_LED_BLINKING
601
602#define STATUS_LED_ACTIVE 0 /* LED on for bit == 0 */
603#define STATUS_LED_BOOT 0 /* LED 0 used for boot status */
604
605#ifndef __ASSEMBLY__
606
607/* LEDs */
608
609/* led_id_t is unsigned int mask */
610typedef unsigned int led_id_t;
611
612#define __led_toggle(_msk) \
613 do { \
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200614 ((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pedat ^= (_msk); \
wdenk79fa88f2004-06-07 23:46:25 +0000615 } while(0)
616
617#define __led_set(_msk, _st) \
618 do { \
619 if ((_st)) \
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200620 ((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pedat |= (_msk); \
wdenk79fa88f2004-06-07 23:46:25 +0000621 else \
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200622 ((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pedat &= ~(_msk); \
wdenk79fa88f2004-06-07 23:46:25 +0000623 } while(0)
624
625#define __led_init(msk, st) __led_set(msk, st)
626
627#endif
628
629/***********************************************************************************************************
630
631 ----------------------------------------------------------------------------------------------
632
633 (V1) version 1 of the board
634 (V2) version 2 of the board
635
636 ----------------------------------------------------------------------------------------------
637
638 Pin definitions:
639
640 +------+----------------+--------+------------------------------------------------------------
641 | # | Name | Type | Comment
642 +------+----------------+--------+------------------------------------------------------------
643 | PA3 | SPIEN_MAX | Output | MAX serial to uart chip select
644 | PA7 | DSP_INT | Output | DSP interrupt
645 | PA10 | DSP_RESET | Output | DSP reset
646 | PA14 | USBOE | Output | USB (1)
647 | PA15 | USBRXD | Output | USB (1)
648 | PB19 | BT_RTS | Output | Bluetooth (0)
649 | PB23 | BT_CTS | Output | Bluetooth (0)
650 | PB26 | SPIEN_SEP | Output | Serial EEPROM chip select
651 | PB27 | SPICS_DISP | Output | Display chip select
652 | PB28 | SPI_RXD_3V | Input | SPI Data Rx
653 | PB29 | SPI_TXD | Output | SPI Data Tx
654 | PB30 | SPI_CLK | Output | SPI Clock
655 | PC10 | DISPA0 | Output | Display A0
656 | PC11 | BACKLIGHT | Output | Display backlit
657 | PC12 | SPI2RXD | Input | (V1) 2nd SPI RXD
658 | | IO_RESET | Output | (V2) General I/O reset
659 | PC13 | SPI2TXD | Output | (V1) 2nd SPI TXD (V1)
660 | | HOOK | Input | (V2) Hook input interrupt
661 | PC15 | SPI2CLK | Output | (V1) 2nd SPI CLK
662 | | F_RY_BY | Input | (V2) NAND F_RY_BY
663 | PE17 | F_ALE | Output | NAND F_ALE
664 | PE18 | F_CLE | Output | NAND F_CLE
665 | PE20 | F_CE | Output | NAND F_CE
666 | PE24 | SPICS_SCOUT | Output | (V1) Codec chip select
667 | | LED | Output | (V2) LED
668 | PE27 | SPICS_ER | Output | External serial register CS
669 | PE28 | LEDIO1 | Output | (V1) LED
670 | | BKBR1 | Input | (V2) Keyboard input scan
671 | PE29 | LEDIO2 | Output | (V1) LED hook for A (TA2)
672 | | BKBR2 | Input | (V2) Keyboard input scan
673 | PE30 | LEDIO3 | Output | (V1) LED hook for A (TA2)
674 | | BKBR3 | Input | (V2) Keyboard input scan
675 | PE31 | F_RY_BY | Input | (V1) NAND F_RY_BY
676 | | BKBR4 | Input | (V2) Keyboard input scan
677 +------+----------------+--------+---------------------------------------------------
678
679 ----------------------------------------------------------------------------------------------
680
681 Serial register input:
682
683 +------+----------------+------------------------------------------------------------
684 | # | Name | Comment
685 +------+----------------+------------------------------------------------------------
686 | 4 | HOOK | Hook switch
687 | 5 | BT_LINK | Bluetooth link status
688 | 6 | HOST_WAKE | Bluetooth host wake up
689 | 7 | OK_ETH | Cisco inline power OK status
690 +------+----------------+------------------------------------------------------------
691
692 ----------------------------------------------------------------------------------------------
693
694 Chip selects:
695
696 +------+----------------+------------------------------------------------------------
697 | # | Name | Comment
698 +------+----------------+------------------------------------------------------------
699 | CS0 | CS0 | Boot flash
700 | CS1 | CS_FLASH | NAND flash
701 | CS2 | CS_DSP | DSP
702 | CS3 | DCS_DRAM | DRAM
703 | CS4 | CS_FLASH2 | (V2) 2nd flash
704 +------+----------------+------------------------------------------------------------
705
706 ----------------------------------------------------------------------------------------------
707
708 Interrupts:
709
710 +------+----------------+------------------------------------------------------------
711 | # | Name | Comment
712 +------+----------------+------------------------------------------------------------
713 | IRQ1 | IRQ_DSP | DSP interrupt
714 | IRQ3 | S_INTER | DUSLIC ???
715 | IRQ4 | F_RY_BY | NAND
716 | IRQ7 | IRQ_MAX | MAX 3100 interrupt
717 +------+----------------+------------------------------------------------------------
718
719 ----------------------------------------------------------------------------------------------
720
721 Interrupts on PCMCIA pins:
722
723 +------+----------------+------------------------------------------------------------
724 | # | Name | Comment
725 +------+----------------+------------------------------------------------------------
726 | IP_A0| PHY1_LINK | Link status changed for #1 Ethernet interface
727 | IP_A1| PHY2_LINK | Link status changed for #2 Ethernet interface
728 | IP_A2| RMII1_MDINT | PHY interrupt for #1
729 | IP_A3| RMII2_MDINT | PHY interrupt for #2
730 | IP_A5| HOST_WAKE | (V2) Bluetooth host wake
731 | IP_A6| OK_ETH | (V2) Cisco inline power OK
732 +------+----------------+------------------------------------------------------------
733
734**************************************************************************************************/
735
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200736#define CONFIG_SYS_CONSOLE_IS_IN_ENV 1
737#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE 1
738#define CONFIG_SYS_CONSOLE_ENV_OVERWRITE 1
wdenk79fa88f2004-06-07 23:46:25 +0000739
740/*************************************************************************************************/
741
742/* use board specific hardware */
743#undef CONFIG_WATCHDOG /* watchdog disabled */
744#define CONFIG_HW_WATCHDOG
wdenk79fa88f2004-06-07 23:46:25 +0000745
746/*************************************************************************************************/
747
748#define CONFIG_CDP_DEVICE_ID 20
749#define CONFIG_CDP_DEVICE_ID_PREFIX "NT" /* netta2 */
750#define CONFIG_CDP_PORT_ID "eth%d"
751#define CONFIG_CDP_CAPABILITIES 0x00000010
Peter Tyser561858e2008-11-03 09:30:59 -0600752#define CONFIG_CDP_VERSION "u-boot" " " U_BOOT_DATE " " U_BOOT_TIME
wdenk79fa88f2004-06-07 23:46:25 +0000753#define CONFIG_CDP_PLATFORM "Intracom NetTA2"
754#define CONFIG_CDP_TRIGGER 0x20020001
755#define CONFIG_CDP_POWER_CONSUMPTION 4300 /* 90 mA @ 48V */
756#define CONFIG_CDP_APPLIANCE_VLAN_TYPE 0x01 /* ipphone ? */
757
758/*************************************************************************************************/
759
760#define CONFIG_AUTO_COMPLETE 1
761
762/*************************************************************************************************/
763
764#define CONFIG_CRC32_VERIFY 1
765
766/*************************************************************************************************/
767
768#define CONFIG_HUSH_OLD_PARSER_COMPATIBLE 1
769
770/*************************************************************************************************/
771#endif /* __CONFIG_H */