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stroese13fdf8a2003-09-12 08:55:18 +00001/*
2 * (C) Copyright 2001-2003
3 * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/*
25 * board/config.h - configuration options, board specific
26 */
27
28#ifndef __CONFIG_H
29#define __CONFIG_H
30
31/*
32 * High Level Configuration Options
33 * (easy to change)
34 */
35
36#define CONFIG_405EP 1 /* This is a PPC405 CPU */
wdenkc837dcb2004-01-20 23:12:12 +000037#define CONFIG_4xx 1 /* ...member of PPC4xx family */
38#define CONFIG_PLU405 1 /* ...on a PLU405 board */
stroese13fdf8a2003-09-12 08:55:18 +000039
wdenkc837dcb2004-01-20 23:12:12 +000040#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */
41#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */
stroese13fdf8a2003-09-12 08:55:18 +000042
stroesea20b27a2004-12-16 18:05:42 +000043#define CONFIG_SYS_CLK_FREQ 33333400 /* external frequency to pll */
stroese13fdf8a2003-09-12 08:55:18 +000044
45#define CONFIG_BAUDRATE 9600
stroese13fdf8a2003-09-12 08:55:18 +000046
47#undef CONFIG_BOOTARGS
stroesea20b27a2004-12-16 18:05:42 +000048#undef CONFIG_BOOTCOMMAND
stroese13fdf8a2003-09-12 08:55:18 +000049
stroesea20b27a2004-12-16 18:05:42 +000050#define CONFIG_PREBOOT /* enable preboot variable */
51
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020052#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
stroese13fdf8a2003-09-12 08:55:18 +000053
stroesea20b27a2004-12-16 18:05:42 +000054#define CONFIG_NET_MULTI 1
Matthias Fuchsf9fc6a52007-03-07 15:32:01 +010055#undef CONFIG_HAS_ETH1
stroesea20b27a2004-12-16 18:05:42 +000056
Ben Warren96e21f82008-10-27 23:50:15 -070057#define CONFIG_PPC4xx_EMAC
stroese13fdf8a2003-09-12 08:55:18 +000058#define CONFIG_MII 1 /* MII PHY management */
wdenkc837dcb2004-01-20 23:12:12 +000059#define CONFIG_PHY_ADDR 0 /* PHY address */
stroesea20b27a2004-12-16 18:05:42 +000060#define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */
Matthias Fuchs9ec367a2008-09-02 11:36:14 +020061#define CONFIG_RESET_PHY_R 1 /* use reset_phy() */
stroesea20b27a2004-12-16 18:05:42 +000062
63#define CONFIG_PHY_CLK_FREQ EMAC_STACR_CLK_66MHZ /* 66 MHz OPB clock*/
stroese13fdf8a2003-09-12 08:55:18 +000064
Jon Loeligeracf02692007-07-08 14:49:44 -050065
66/*
Jon Loeligera1aa0bb2007-07-10 09:22:23 -050067 * BOOTP options
68 */
69#define CONFIG_BOOTP_BOOTFILESIZE
70#define CONFIG_BOOTP_BOOTPATH
71#define CONFIG_BOOTP_GATEWAY
72#define CONFIG_BOOTP_HOSTNAME
73
74
75/*
Jon Loeligeracf02692007-07-08 14:49:44 -050076 * Command line configuration.
77 */
78#include <config_cmd_default.h>
79
80#define CONFIG_CMD_DHCP
81#define CONFIG_CMD_PCI
82#define CONFIG_CMD_IRQ
83#define CONFIG_CMD_IDE
84#define CONFIG_CMD_FAT
85#define CONFIG_CMD_ELF
86#define CONFIG_CMD_NAND
87#define CONFIG_CMD_DATE
88#define CONFIG_CMD_I2C
89#define CONFIG_CMD_MII
90#define CONFIG_CMD_PING
91#define CONFIG_CMD_EEPROM
Matthias Fuchs17e65c22008-09-02 11:35:56 +020092#define CONFIG_CMD_USB
Jon Loeligeracf02692007-07-08 14:49:44 -050093
Matthias Fuchs3bc10542008-09-02 11:34:36 +020094#define CONFIG_OF_LIBFDT
95#define CONFIG_OF_BOARD_SETUP
stroese13fdf8a2003-09-12 08:55:18 +000096
97#define CONFIG_MAC_PARTITION
98#define CONFIG_DOS_PARTITION
99
stroesea20b27a2004-12-16 18:05:42 +0000100#define CONFIG_SUPPORT_VFAT
101
102#define CONFIG_AUTO_UPDATE 1 /* autoupdate via compactflash */
stroesea20b27a2004-12-16 18:05:42 +0000103
wdenkc837dcb2004-01-20 23:12:12 +0000104#undef CONFIG_WATCHDOG /* watchdog disabled */
stroese13fdf8a2003-09-12 08:55:18 +0000105
wdenkc837dcb2004-01-20 23:12:12 +0000106#define CONFIG_RTC_MC146818 /* DS1685 is MC146818 compatible*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200107#define CONFIG_SYS_RTC_REG_BASE_ADDR 0xF0000500 /* RTC Base Address */
stroese13fdf8a2003-09-12 08:55:18 +0000108
wdenkc837dcb2004-01-20 23:12:12 +0000109#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
stroese13fdf8a2003-09-12 08:55:18 +0000110
111/*
112 * Miscellaneous configurable options
113 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200114#define CONFIG_SYS_LONGHELP /* undef to save memory */
115#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
stroese13fdf8a2003-09-12 08:55:18 +0000116
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200117#undef CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
118#ifdef CONFIG_SYS_HUSH_PARSER
119#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
stroese13fdf8a2003-09-12 08:55:18 +0000120#endif
121
Jon Loeligeracf02692007-07-08 14:49:44 -0500122#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200123#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
stroese13fdf8a2003-09-12 08:55:18 +0000124#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200125#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
stroese13fdf8a2003-09-12 08:55:18 +0000126#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200127#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
128#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
129#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
stroese13fdf8a2003-09-12 08:55:18 +0000130
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200131#define CONFIG_SYS_DEVICE_NULLDEV 1 /* include nulldev device */
stroese13fdf8a2003-09-12 08:55:18 +0000132
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200133#define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/
stroese13fdf8a2003-09-12 08:55:18 +0000134
stroesea20b27a2004-12-16 18:05:42 +0000135#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */
136
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200137#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
138#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
stroese13fdf8a2003-09-12 08:55:18 +0000139
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200140#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200141#define CONFIG_SYS_BASE_BAUD 691200
wdenkc837dcb2004-01-20 23:12:12 +0000142#undef CONFIG_UART1_CONSOLE /* define for uart1 as console */
stroese13fdf8a2003-09-12 08:55:18 +0000143
144/* The following table includes the supported baudrates */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200145#define CONFIG_SYS_BAUDRATE_TABLE \
stroese13fdf8a2003-09-12 08:55:18 +0000146 { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \
147 57600, 115200, 230400, 460800, 921600 }
148
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200149#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
150#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */
stroese13fdf8a2003-09-12 08:55:18 +0000151
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200152#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
stroese13fdf8a2003-09-12 08:55:18 +0000153
Matthias Fuchs17e65c22008-09-02 11:35:56 +0200154#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
stroese13fdf8a2003-09-12 08:55:18 +0000155#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
stroesea20b27a2004-12-16 18:05:42 +0000156#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */
157
158/* Only interrupt boot if space is pressed */
159/* If a long serial cable is connected but */
160/* other end is dead, garbage will be read */
Stefan Roesef2302d42008-08-06 14:05:38 +0200161#define CONFIG_AUTOBOOT_KEYED 1
162#define CONFIG_AUTOBOOT_PROMPT \
163 "Press SPACE to abort autoboot in %d seconds\n", bootdelay
stroesea20b27a2004-12-16 18:05:42 +0000164#undef CONFIG_AUTOBOOT_DELAY_STR
165#define CONFIG_AUTOBOOT_STOP_STR " "
stroese13fdf8a2003-09-12 08:55:18 +0000166
wdenkc837dcb2004-01-20 23:12:12 +0000167#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
stroese13fdf8a2003-09-12 08:55:18 +0000168
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200169#define CONFIG_SYS_RX_ETH_BUFFER 16 /* use 16 rx buffer on 405 emac */
stroese13fdf8a2003-09-12 08:55:18 +0000170
Matthias Fuchs9ec367a2008-09-02 11:36:14 +0200171/*
stroese13fdf8a2003-09-12 08:55:18 +0000172 * NAND-FLASH stuff
stroese13fdf8a2003-09-12 08:55:18 +0000173 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200174#define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE}
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200175#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
Matthias Fuchsbd84ee42007-07-09 10:10:06 +0200176#define NAND_BIG_DELAY_US 25
Bartlomiej Siekaaddb2e12006-03-05 18:57:33 +0100177
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200178#define CONFIG_SYS_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */
179#define CONFIG_SYS_NAND_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */
180#define CONFIG_SYS_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */
181#define CONFIG_SYS_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */
stroese13fdf8a2003-09-12 08:55:18 +0000182
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200183#define CONFIG_SYS_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */
184#define CONFIG_SYS_NAND_QUIET 1
stroesea20b27a2004-12-16 18:05:42 +0000185
Matthias Fuchs9ec367a2008-09-02 11:36:14 +0200186/*
stroese13fdf8a2003-09-12 08:55:18 +0000187 * PCI stuff
stroese13fdf8a2003-09-12 08:55:18 +0000188 */
stroesea20b27a2004-12-16 18:05:42 +0000189#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */
190#define PCI_HOST_FORCE 1 /* configure as pci host */
191#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
stroese13fdf8a2003-09-12 08:55:18 +0000192
stroesea20b27a2004-12-16 18:05:42 +0000193#define CONFIG_PCI /* include pci support */
Matthias Fuchs17e65c22008-09-02 11:35:56 +0200194#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */
stroesea20b27a2004-12-16 18:05:42 +0000195#define CONFIG_PCI_PNP /* do pci plug-and-play */
196 /* resource configuration */
stroese13fdf8a2003-09-12 08:55:18 +0000197
stroesea20b27a2004-12-16 18:05:42 +0000198#define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */
stroese13fdf8a2003-09-12 08:55:18 +0000199
stroesea20b27a2004-12-16 18:05:42 +0000200#define CONFIG_PCI_CONFIG_HOST_BRIDGE 1 /* don't skip host bridge config*/
201
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200202#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */
203#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0405 /* PCI Device ID: CPCI-405 */
204#define CONFIG_SYS_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/
205#define CONFIG_SYS_PCI_PTM1LA 0x00000000 /* point to sdram */
206#define CONFIG_SYS_PCI_PTM1MS 0xf8000001 /* 128MB, enable hard-wired to 1 */
207#define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
208#define CONFIG_SYS_PCI_PTM2LA 0xffc00000 /* point to flash */
209#define CONFIG_SYS_PCI_PTM2MS 0xffc00001 /* 4MB, enable */
210#define CONFIG_SYS_PCI_PTM2PCI 0x08000000 /* Host: use this pci address */
stroese13fdf8a2003-09-12 08:55:18 +0000211
Matthias Fuchs9ec367a2008-09-02 11:36:14 +0200212/*
stroese13fdf8a2003-09-12 08:55:18 +0000213 * IDE/ATA stuff
stroese13fdf8a2003-09-12 08:55:18 +0000214 */
wdenkc837dcb2004-01-20 23:12:12 +0000215#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */
216#undef CONFIG_IDE_LED /* no led for ide supported */
stroese13fdf8a2003-09-12 08:55:18 +0000217#define CONFIG_IDE_RESET 1 /* reset for ide supported */
218
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200219#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE busses */
Matthias Fuchs9ec367a2008-09-02 11:36:14 +0200220/* max. 1 drives per IDE bus */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200221#define CONFIG_SYS_IDE_MAXDEVICE (CONFIG_SYS_IDE_MAXBUS*1)
stroese13fdf8a2003-09-12 08:55:18 +0000222
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200223#define CONFIG_SYS_ATA_BASE_ADDR 0xF0100000
224#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
stroese13fdf8a2003-09-12 08:55:18 +0000225
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200226#define CONFIG_SYS_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O */
227#define CONFIG_SYS_ATA_REG_OFFSET 0x0000 /* Offset for normal register access */
228#define CONFIG_SYS_ATA_ALT_OFFSET 0x0000 /* Offset for alternate registers */
stroese13fdf8a2003-09-12 08:55:18 +0000229
230/*
231 * For booting Linux, the board info and command line data
232 * have to be in the first 8 MB of memory, since this is
233 * the maximum mapped by the Linux kernel during initialization.
234 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200235#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
Matthias Fuchs9ec367a2008-09-02 11:36:14 +0200236
237/*
stroese13fdf8a2003-09-12 08:55:18 +0000238 * FLASH organization
239 */
Matthias Fuchs9ec367a2008-09-02 11:36:14 +0200240#define FLASH_BASE0_PRELIM 0xFFC00000 /* FLASH bank #0 */
stroese13fdf8a2003-09-12 08:55:18 +0000241
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200242#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
243#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
stroese13fdf8a2003-09-12 08:55:18 +0000244
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200245#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
246#define CONFIG_SYS_FLASH_WRITE_TOUT 1000 /* Timeout for Flash Write (in ms) */
stroese13fdf8a2003-09-12 08:55:18 +0000247
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200248#define CONFIG_SYS_FLASH_WORD_SIZE unsigned short /* flash word size (width) */
249#define CONFIG_SYS_FLASH_ADDR0 0x5555 /* 1st addr for flash config cycles */
250#define CONFIG_SYS_FLASH_ADDR1 0x2AAA /* 2nd addr for flash config cycles */
stroese13fdf8a2003-09-12 08:55:18 +0000251/*
252 * The following defines are added for buggy IOP480 byte interface.
253 * All other boards should use the standard values (CPCI405 etc.)
254 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200255#define CONFIG_SYS_FLASH_READ0 0x0000 /* 0 is standard */
256#define CONFIG_SYS_FLASH_READ1 0x0001 /* 1 is standard */
257#define CONFIG_SYS_FLASH_READ2 0x0002 /* 2 is standard */
stroese13fdf8a2003-09-12 08:55:18 +0000258
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200259#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector */
stroese13fdf8a2003-09-12 08:55:18 +0000260
Matthias Fuchs9ec367a2008-09-02 11:36:14 +0200261/*
stroese13fdf8a2003-09-12 08:55:18 +0000262 * Start addresses for the final memory configuration
263 * (Set up by the startup code)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200264 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
stroese13fdf8a2003-09-12 08:55:18 +0000265 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200266#define CONFIG_SYS_SDRAM_BASE 0x00000000
267#define CONFIG_SYS_FLASH_BASE 0xFFFA0000
268#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
269#define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384kB for Monitor */
270#define CONFIG_SYS_MALLOC_LEN (384 * 1024) /* Reserve 384kB for malloc() */
stroese13fdf8a2003-09-12 08:55:18 +0000271
Matthias Fuchs9ec367a2008-09-02 11:36:14 +0200272/*
stroese13fdf8a2003-09-12 08:55:18 +0000273 * Environment Variable setup
274 */
Jean-Christophe PLAGNIOL-VILLARDbb1f8b42008-09-05 09:19:30 +0200275#define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200276#define CONFIG_ENV_OFFSET 0x100 /* reseve 0x100 bytes for strapping */
277#define CONFIG_ENV_SIZE 0x700
stroese13fdf8a2003-09-12 08:55:18 +0000278
Matthias Fuchs9ec367a2008-09-02 11:36:14 +0200279/*
280 * I2C EEPROM (24WC16) for environment
stroese13fdf8a2003-09-12 08:55:18 +0000281 */
282#define CONFIG_HARD_I2C /* I2c with hardware support */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200283#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
284#define CONFIG_SYS_I2C_SLAVE 0x7F
stroese13fdf8a2003-09-12 08:55:18 +0000285
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200286#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM 24WC16 */
287#define CONFIG_SYS_EEPROM_WREN 1
Matthias Fuchsbd84ee42007-07-09 10:10:06 +0200288
Matthias Fuchs9ec367a2008-09-02 11:36:14 +0200289/* 24WC16 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200290#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
Matthias Fuchs9ec367a2008-09-02 11:36:14 +0200291/* mask of address bits that overflow into the "EEPROM chip address" */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200292#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07
293#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* The 24WC16 has */
Matthias Fuchs9ec367a2008-09-02 11:36:14 +0200294 /* 16 byte page write mode using */
295 /* last 4 bits of the address */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200296#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
stroese13fdf8a2003-09-12 08:55:18 +0000297
Matthias Fuchs9ec367a2008-09-02 11:36:14 +0200298/*
stroese13fdf8a2003-09-12 08:55:18 +0000299 * External Bus Controller (EBC) Setup
300 */
Matthias Fuchs9ec367a2008-09-02 11:36:14 +0200301#define CAN_BA 0xF0000000 /* CAN Base Address */
302#define DUART0_BA 0xF0000400 /* DUART Base Address */
303#define DUART1_BA 0xF0000408 /* DUART Base Address */
304#define RTC_BA 0xF0000500 /* RTC Base Address */
305#define VGA_BA 0xF1000000 /* Epson VGA Base Address */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200306#define CONFIG_SYS_NAND_BASE 0xF4000000 /* NAND FLASH Base Address */
stroese13fdf8a2003-09-12 08:55:18 +0000307
Matthias Fuchs9ec367a2008-09-02 11:36:14 +0200308/* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization */
309/* TWT=16,CSN=1,OEN=1,WBN=1,WBF=1,TH=4,SOR=1 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200310#define CONFIG_SYS_EBC_PB0AP 0x92015480
Matthias Fuchs9ec367a2008-09-02 11:36:14 +0200311/* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200312#define CONFIG_SYS_EBC_PB0CR 0xFFC5A000
stroese13fdf8a2003-09-12 08:55:18 +0000313
Matthias Fuchs9ec367a2008-09-02 11:36:14 +0200314/* Memory Bank 1 (Flash Bank 1, NAND-FLASH) initialization */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200315#define CONFIG_SYS_EBC_PB1AP 0x92015480
Matthias Fuchs9ec367a2008-09-02 11:36:14 +0200316/* BAS=0xF40,BS=1MB,BU=R/W,BW=8bit */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200317#define CONFIG_SYS_EBC_PB1CR 0xF4018000
stroese13fdf8a2003-09-12 08:55:18 +0000318
Matthias Fuchs9ec367a2008-09-02 11:36:14 +0200319/* Memory Bank 2 (8 Bit Peripheral: CAN, UART, RTC) initialization */
320/* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200321#define CONFIG_SYS_EBC_PB2AP 0x010053C0
Matthias Fuchs9ec367a2008-09-02 11:36:14 +0200322/* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200323#define CONFIG_SYS_EBC_PB2CR 0xF0018000
stroese13fdf8a2003-09-12 08:55:18 +0000324
Matthias Fuchs9ec367a2008-09-02 11:36:14 +0200325/* Memory Bank 3 (16 Bit Peripheral: FPGA internal, dig. IO) initialization */
326/* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200327#define CONFIG_SYS_EBC_PB3AP 0x010053C0
Matthias Fuchs9ec367a2008-09-02 11:36:14 +0200328/* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200329#define CONFIG_SYS_EBC_PB3CR 0xF011A000
stroese13fdf8a2003-09-12 08:55:18 +0000330
Matthias Fuchs9ec367a2008-09-02 11:36:14 +0200331/*
stroese13fdf8a2003-09-12 08:55:18 +0000332 * FPGA stuff
333 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200334#define CONFIG_SYS_FPGA_BASE_ADDR 0xF0100100 /* FPGA internal Base Address */
stroese13fdf8a2003-09-12 08:55:18 +0000335
336/* FPGA internal regs */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200337#define CONFIG_SYS_FPGA_CTRL 0x000
stroese13fdf8a2003-09-12 08:55:18 +0000338
339/* FPGA Control Reg */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200340#define CONFIG_SYS_FPGA_CTRL_CF_RESET 0x0001
341#define CONFIG_SYS_FPGA_CTRL_WDI 0x0002
342#define CONFIG_SYS_FPGA_CTRL_PS2_RESET 0x0020
stroese13fdf8a2003-09-12 08:55:18 +0000343
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200344#define CONFIG_SYS_FPGA_SPARTAN2 1 /* using Xilinx Spartan 2 now */
345#define CONFIG_SYS_FPGA_MAX_SIZE 128*1024 /* 128kByte is enough for XC2S50E*/
stroese13fdf8a2003-09-12 08:55:18 +0000346
347/* FPGA program pin configuration */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200348#define CONFIG_SYS_FPGA_PRG 0x04000000 /* FPGA program pin (ppc output) */
349#define CONFIG_SYS_FPGA_CLK 0x02000000 /* FPGA clk pin (ppc output) */
350#define CONFIG_SYS_FPGA_DATA 0x01000000 /* FPGA data pin (ppc output) */
351#define CONFIG_SYS_FPGA_INIT 0x00010000 /* FPGA init pin (ppc input) */
352#define CONFIG_SYS_FPGA_DONE 0x00008000 /* FPGA done pin (ppc input) */
stroese13fdf8a2003-09-12 08:55:18 +0000353
Matthias Fuchs9ec367a2008-09-02 11:36:14 +0200354/*
stroese13fdf8a2003-09-12 08:55:18 +0000355 * Definitions for initial stack pointer and data area (in data cache)
356 */
357/* use on chip memory ( OCM ) for temperary stack until sdram is tested */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200358#define CONFIG_SYS_TEMP_STACK_OCM 1
stroese13fdf8a2003-09-12 08:55:18 +0000359
360/* On Chip Memory location */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200361#define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000
362#define CONFIG_SYS_OCM_DATA_SIZE 0x1000
363#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM */
364#define CONFIG_SYS_INIT_RAM_END CONFIG_SYS_OCM_DATA_SIZE /* End of used area in RAM */
stroese13fdf8a2003-09-12 08:55:18 +0000365
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200366#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
367#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
368#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
stroese13fdf8a2003-09-12 08:55:18 +0000369
Matthias Fuchs9ec367a2008-09-02 11:36:14 +0200370/*
stroese13fdf8a2003-09-12 08:55:18 +0000371 * Definitions for GPIO setup (PPC405EP specific)
372 *
wdenkc837dcb2004-01-20 23:12:12 +0000373 * GPIO0[0] - External Bus Controller BLAST output
374 * GPIO0[1-9] - Instruction trace outputs -> GPIO
stroese13fdf8a2003-09-12 08:55:18 +0000375 * GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs
376 * GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs -> GPIO
377 * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs
378 * GPIO0[24-27] - UART0 control signal inputs/outputs
379 * GPIO0[28-29] - UART1 data signal input/output
380 * GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs
381 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200382#define CONFIG_SYS_GPIO0_OSRH 0x00000550
383#define CONFIG_SYS_GPIO0_OSRL 0x00000110
384#define CONFIG_SYS_GPIO0_ISR1H 0x00000000
385#define CONFIG_SYS_GPIO0_ISR1L 0x15555445
386#define CONFIG_SYS_GPIO0_TSRH 0x00000000
387#define CONFIG_SYS_GPIO0_TSRL 0x00000000
388#define CONFIG_SYS_GPIO0_TCR 0x77FE0014
stroese13fdf8a2003-09-12 08:55:18 +0000389
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200390#define CONFIG_SYS_DUART_RST (0x80000000 >> 14)
391#define CONFIG_SYS_EEPROM_WP (0x80000000 >> 0)
stroese13fdf8a2003-09-12 08:55:18 +0000392
393/*
394 * Internal Definitions
395 *
396 * Boot Flags
397 */
Matthias Fuchs9ec367a2008-09-02 11:36:14 +0200398#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
399#define BOOTFLAG_WARM 0x02 /* Software reboot */
stroese13fdf8a2003-09-12 08:55:18 +0000400
401/*
Matthias Fuchs9ec367a2008-09-02 11:36:14 +0200402 * Default speed selection (cpu_plb_opb_ebc) in MHz.
stroese13fdf8a2003-09-12 08:55:18 +0000403 * This value will be set if iic boot eprom is disabled.
404 */
Matthias Fuchs17e65c22008-09-02 11:35:56 +0200405#if 1
wdenkc837dcb2004-01-20 23:12:12 +0000406#define PLLMR0_DEFAULT PLLMR0_266_133_66_33
407#define PLLMR1_DEFAULT PLLMR1_266_133_66_33
stroese13fdf8a2003-09-12 08:55:18 +0000408#endif
409#if 0
wdenkc837dcb2004-01-20 23:12:12 +0000410#define PLLMR0_DEFAULT PLLMR0_200_100_50_33
411#define PLLMR1_DEFAULT PLLMR1_200_100_50_33
stroese13fdf8a2003-09-12 08:55:18 +0000412#endif
Matthias Fuchs17e65c22008-09-02 11:35:56 +0200413#if 0
wdenkc837dcb2004-01-20 23:12:12 +0000414#define PLLMR0_DEFAULT PLLMR0_133_66_66_33
415#define PLLMR1_DEFAULT PLLMR1_133_66_66_33
stroese13fdf8a2003-09-12 08:55:18 +0000416#endif
417
Matthias Fuchs17e65c22008-09-02 11:35:56 +0200418/*
419 * PCI OHCI controller
420 */
421#define CONFIG_USB_OHCI_NEW 1
422#define CONFIG_PCI_OHCI 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200423#define CONFIG_SYS_OHCI_SWAP_REG_ACCESS 1
424#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15
425#define CONFIG_SYS_USB_OHCI_SLOT_NAME "ohci_pci"
Matthias Fuchs17e65c22008-09-02 11:35:56 +0200426#define CONFIG_USB_STORAGE 1
427
stroese13fdf8a2003-09-12 08:55:18 +0000428#endif /* __CONFIG_H */