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stroese071d8972003-05-23 11:35:47 +00001/*
stroesea20b27a2004-12-16 18:05:42 +00002 * (C) Copyright 2001-2004
stroese071d8972003-05-23 11:35:47 +00003 * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
Matthias Fuchsc553b5f2009-02-15 22:26:54 +010015 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
stroese071d8972003-05-23 11:35:47 +000016 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
stroese071d8972003-05-23 11:35:47 +000024#ifndef __CONFIG_H
25#define __CONFIG_H
26
27/*
28 * High Level Configuration Options
stroese071d8972003-05-23 11:35:47 +000029 */
30
31#define CONFIG_405GP 1 /* This is a PPC405 CPU */
wdenkc837dcb2004-01-20 23:12:12 +000032#define CONFIG_4xx 1 /* ...member of PPC4xx family */
33#define CONFIG_PMC405 1 /* ...on a PMC405 board */
stroese071d8972003-05-23 11:35:47 +000034
wdenkc837dcb2004-01-20 23:12:12 +000035#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */
36#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */
stroese071d8972003-05-23 11:35:47 +000037
stroesea20b27a2004-12-16 18:05:42 +000038#define CONFIG_SYS_CLK_FREQ 33330000 /* external frequency to pll */
stroese071d8972003-05-23 11:35:47 +000039
40#define CONFIG_BAUDRATE 9600
41#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */
42
Matthias Fuchs2f6eb912009-02-15 22:27:47 +010043/* Only interrupt boot if space is pressed. */
44#define CONFIG_AUTOBOOT_KEYED 1
45#define CONFIG_AUTOBOOT_PROMPT \
46 "Press SPACE to abort autoboot in %d seconds\n", bootdelay
47#undef CONFIG_AUTOBOOT_DELAY_STR
48#define CONFIG_AUTOBOOT_STOP_STR " "
49
Matthias Fuchsc553b5f2009-02-15 22:26:54 +010050#undef CONFIG_BOOTARGS
51#undef CONFIG_BOOTCOMMAND
stroesea20b27a2004-12-16 18:05:42 +000052
Matthias Fuchsc553b5f2009-02-15 22:26:54 +010053#define CONFIG_PREBOOT /* enable preboot variable */
stroese071d8972003-05-23 11:35:47 +000054
Matthias Fuchs2f6eb912009-02-15 22:27:47 +010055#define CFG_BOOTM_LEN 0x1000000 /* support booting of huge images */
56
stroese071d8972003-05-23 11:35:47 +000057#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Matthias Fuchsc553b5f2009-02-15 22:26:54 +010058#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
stroese071d8972003-05-23 11:35:47 +000059
Stefan Roese2076d0a2006-01-18 20:03:15 +010060#define CONFIG_NET_MULTI 1
61#undef CONFIG_HAS_ETH1
62
Ben Warren96e21f82008-10-27 23:50:15 -070063#define CONFIG_PPC4xx_EMAC
stroese071d8972003-05-23 11:35:47 +000064#define CONFIG_MII 1 /* MII PHY management */
wdenkc837dcb2004-01-20 23:12:12 +000065#define CONFIG_PHY_ADDR 0 /* PHY address */
Matthias Fuchsc553b5f2009-02-15 22:26:54 +010066#define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */
67#define CONFIG_RESET_PHY_R 1 /* use reset_phy() */
Jon Loeligeracf02692007-07-08 14:49:44 -050068
69/*
Jon Loeligera1aa0bb2007-07-10 09:22:23 -050070 * BOOTP options
71 */
72#define CONFIG_BOOTP_BOOTFILESIZE
73#define CONFIG_BOOTP_BOOTPATH
74#define CONFIG_BOOTP_GATEWAY
75#define CONFIG_BOOTP_HOSTNAME
76
Jon Loeligera1aa0bb2007-07-10 09:22:23 -050077/*
Jon Loeligeracf02692007-07-08 14:49:44 -050078 * Command line configuration.
79 */
80#include <config_cmd_default.h>
81
82#define CONFIG_CMD_BSP
83#define CONFIG_CMD_PCI
84#define CONFIG_CMD_IRQ
85#define CONFIG_CMD_ELF
86#define CONFIG_CMD_DATE
87#define CONFIG_CMD_JFFS2
88#define CONFIG_CMD_MII
89#define CONFIG_CMD_I2C
90#define CONFIG_CMD_PING
91#define CONFIG_CMD_UNIVERSE
92#define CONFIG_CMD_EEPROM
93
stroese071d8972003-05-23 11:35:47 +000094#define CONFIG_MAC_PARTITION
95#define CONFIG_DOS_PARTITION
96
Matthias Fuchsc553b5f2009-02-15 22:26:54 +010097#undef CONFIG_WATCHDOG /* watchdog disabled */
stroese071d8972003-05-23 11:35:47 +000098
Matthias Fuchsc553b5f2009-02-15 22:26:54 +010099#define CONFIG_RTC_MC146818 /* DS1685 is MC146818 compatible */
100#define CONFIG_SYS_RTC_REG_BASE_ADDR 0xF0000500 /* RTC Base Address */
stroese071d8972003-05-23 11:35:47 +0000101
wdenkc837dcb2004-01-20 23:12:12 +0000102#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
stroese071d8972003-05-23 11:35:47 +0000103
104/*
105 * Miscellaneous configurable options
106 */
Matthias Fuchsc553b5f2009-02-15 22:26:54 +0100107#define CONFIG_SYS_LONGHELP /* undef to save memory */
108#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
stroese071d8972003-05-23 11:35:47 +0000109
Matthias Fuchsc553b5f2009-02-15 22:26:54 +0100110#undef CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
111#ifdef CONFIG_SYS_HUSH_PARSER
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200112#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
stroese071d8972003-05-23 11:35:47 +0000113#endif
114
Jon Loeligeracf02692007-07-08 14:49:44 -0500115#if defined(CONFIG_CMD_KGDB)
Matthias Fuchsc553b5f2009-02-15 22:26:54 +0100116#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
stroese071d8972003-05-23 11:35:47 +0000117#else
Matthias Fuchs2f6eb912009-02-15 22:27:47 +0100118#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
stroese071d8972003-05-23 11:35:47 +0000119#endif
Matthias Fuchsc553b5f2009-02-15 22:26:54 +0100120#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
121#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
122#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Sz */
stroese071d8972003-05-23 11:35:47 +0000123
Matthias Fuchsc553b5f2009-02-15 22:26:54 +0100124#define CONFIG_SYS_DEVICE_NULLDEV 1 /* include nulldev device */
stroese071d8972003-05-23 11:35:47 +0000125
Matthias Fuchsc553b5f2009-02-15 22:26:54 +0100126#define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* don't print console info */
stroese071d8972003-05-23 11:35:47 +0000127
Matthias Fuchsc553b5f2009-02-15 22:26:54 +0100128#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */
stroesea20b27a2004-12-16 18:05:42 +0000129
Matthias Fuchsc553b5f2009-02-15 22:26:54 +0100130#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
131#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
stroese071d8972003-05-23 11:35:47 +0000132
Matthias Fuchsc553b5f2009-02-15 22:26:54 +0100133#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock */
Matthias Fuchs2f6eb912009-02-15 22:27:47 +0100134#define CONFIG_SYS_BASE_BAUD 806400
stroese071d8972003-05-23 11:35:47 +0000135
136/* The following table includes the supported baudrates */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200137#define CONFIG_SYS_BAUDRATE_TABLE \
Matthias Fuchs2f6eb912009-02-15 22:27:47 +0100138 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
stroese071d8972003-05-23 11:35:47 +0000139
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200140#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
Matthias Fuchsc553b5f2009-02-15 22:26:54 +0100141#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */
stroese071d8972003-05-23 11:35:47 +0000142
Matthias Fuchsc553b5f2009-02-15 22:26:54 +0100143#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
stroese071d8972003-05-23 11:35:47 +0000144
Matthias Fuchs2f6eb912009-02-15 22:27:47 +0100145#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
Matthias Fuchsc553b5f2009-02-15 22:26:54 +0100146#define CONFIG_LOOPW 1 /* enable loopw command */
stroesea20b27a2004-12-16 18:05:42 +0000147
stroese071d8972003-05-23 11:35:47 +0000148#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
149
wdenkc837dcb2004-01-20 23:12:12 +0000150#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
stroese53cf9432003-06-05 15:39:44 +0000151
Matthias Fuchsc553b5f2009-02-15 22:26:54 +0100152#define CONFIG_SYS_RX_ETH_BUFFER 16
stroese53cf9432003-06-05 15:39:44 +0000153
Matthias Fuchsc553b5f2009-02-15 22:26:54 +0100154/*
stroese071d8972003-05-23 11:35:47 +0000155 * PCI stuff
stroese071d8972003-05-23 11:35:47 +0000156 */
Matthias Fuchsc553b5f2009-02-15 22:26:54 +0100157#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */
158#define PCI_HOST_FORCE 1 /* configure as pci host */
159#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
stroese071d8972003-05-23 11:35:47 +0000160
Matthias Fuchsc553b5f2009-02-15 22:26:54 +0100161#define CONFIG_PCI /* include pci support */
162#define CONFIG_PCI_HOST PCI_HOST_AUTO /* select pci host function */
163#define CONFIG_PCI_PNP /* do pci plug-and-play */
164 /* resource configuration */
stroese071d8972003-05-23 11:35:47 +0000165
Matthias Fuchsc553b5f2009-02-15 22:26:54 +0100166#define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */
stroese071d8972003-05-23 11:35:47 +0000167
Matthias Fuchsc553b5f2009-02-15 22:26:54 +0100168#define CONFIG_PCI_CONFIG_HOST_BRIDGE 1 /* don't skip host bridge config */
stroesea20b27a2004-12-16 18:05:42 +0000169
Matthias Fuchsc553b5f2009-02-15 22:26:54 +0100170#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */
171#define CONFIG_SYS_PCI_SUBSYS_DEVICEID_NONMONARCH 0x0408 /* PCI Device ID */
172#define CONFIG_SYS_PCI_SUBSYS_DEVICEID_MONARCH 0x0409 /* PCI Device ID */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200173#define CONFIG_SYS_PCI_SUBSYS_DEVICEID pmc405_pci_subsys_deviceid()
Stefan Roese2076d0a2006-01-18 20:03:15 +0100174
Matthias Fuchsc553b5f2009-02-15 22:26:54 +0100175#define CONFIG_SYS_PCI_CLASSCODE 0x0b20 /* Processor/PPC */
Stefan Roese2076d0a2006-01-18 20:03:15 +0100176
Matthias Fuchsc553b5f2009-02-15 22:26:54 +0100177#define CONFIG_SYS_PCI_PTM1LA (bd->bi_memstart) /* point to sdram */
178#define CONFIG_SYS_PCI_PTM1MS (~(bd->bi_memsize - 1) | 1) /* memsize, enable */
179#define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
180#define CONFIG_SYS_PCI_PTM2LA 0xef000000 /* point to internal regs */
181#define CONFIG_SYS_PCI_PTM2MS 0xff000001 /* 16MB, enable */
182#define CONFIG_SYS_PCI_PTM2PCI 0x00000000 /* Host: use this pci address */
183
184/*
stroese071d8972003-05-23 11:35:47 +0000185 * Start addresses for the final memory configuration
186 * (Set up by the startup code)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200187 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
stroese071d8972003-05-23 11:35:47 +0000188 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200189#define CONFIG_SYS_SDRAM_BASE 0x00000000
Matthias Fuchs2f6eb912009-02-15 22:27:47 +0100190#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
191#define CONFIG_SYS_MONITOR_LEN (~(TEXT_BASE) + 1)
Matthias Fuchsc553b5f2009-02-15 22:26:54 +0100192#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* 128 kB for malloc() */
stroese071d8972003-05-23 11:35:47 +0000193
Matthias Fuchs2f6eb912009-02-15 22:27:47 +0100194#define CONFIG_PRAM 0 /* use pram variable to overwrite */
195
stroese071d8972003-05-23 11:35:47 +0000196/*
197 * For booting Linux, the board info and command line data
198 * have to be in the first 8 MB of memory, since this is
199 * the maximum mapped by the Linux kernel during initialization.
200 */
Matthias Fuchsc553b5f2009-02-15 22:26:54 +0100201#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
stroese071d8972003-05-23 11:35:47 +0000202
Matthias Fuchsc553b5f2009-02-15 22:26:54 +0100203/*
stroese071d8972003-05-23 11:35:47 +0000204 * FLASH organization
205 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200206#define CONFIG_SYS_FLASH_BASE 0xFE000000
207#define CONFIG_SYS_FLASH_INCREMENT 0x01000000
stroese071d8972003-05-23 11:35:47 +0000208
Matthias Fuchsc553b5f2009-02-15 22:26:54 +0100209#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */
210#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */
211#define CONFIG_SYS_FLASH_PROTECTION 1 /* don't use hardware protection */
Matthias Fuchs2f6eb912009-02-15 22:27:47 +0100212#define CONFIG_SYS_FLASH_AUTOPROTECT_LIST {{0xfff80000, 0x80000}}
Matthias Fuchsc553b5f2009-02-15 22:26:54 +0100213#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (faster) */
214#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max num of flash banks */
215#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, \
216 CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_INCREMENT}
217#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max num of sects on one chip */
218#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on fli */
stroese071d8972003-05-23 11:35:47 +0000219
Wolfgang Denk700a0c62005-08-08 01:03:24 +0200220/*
stroese071d8972003-05-23 11:35:47 +0000221 * Environment Variable setup
222 */
Jean-Christophe PLAGNIOL-VILLARDbb1f8b42008-09-05 09:19:30 +0200223#define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
stroese071d8972003-05-23 11:35:47 +0000224
Matthias Fuchsc553b5f2009-02-15 22:26:54 +0100225/* environment starts at the beginning of the EEPROM */
226#define CONFIG_ENV_OFFSET 0x000
227#define CONFIG_ENV_SIZE 0x800 /* 2048 bytes may be used for env vars */
stroese071d8972003-05-23 11:35:47 +0000228
Matthias Fuchsc553b5f2009-02-15 22:26:54 +0100229#define CONFIG_SYS_NVRAM_BASE_ADDR 0xF0000500 /* NVRAM base address */
230#define CONFIG_SYS_NVRAM_SIZE 242 /* NVRAM size */
231
232/*
stroese071d8972003-05-23 11:35:47 +0000233 * I2C EEPROM (CAT24WC16) for environment
234 */
235#define CONFIG_HARD_I2C /* I2c with hardware support */
Matthias Fuchs2f6eb912009-02-15 22:27:47 +0100236#define CONFIG_SYS_I2C_SPEED 100000 /* I2C speed and slave address */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200237#define CONFIG_SYS_I2C_SLAVE 0x7F
stroese071d8972003-05-23 11:35:47 +0000238
Matthias Fuchs2f6eb912009-02-15 22:27:47 +0100239#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT24W16 */
Matthias Fuchsc553b5f2009-02-15 22:26:54 +0100240#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
241/* mask of address bits that overflow into the "EEPROM chip address" */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200242#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07
Matthias Fuchs2f6eb912009-02-15 22:27:47 +0100243#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24W16 has */
244 /* 16 byte page write mode using*/
245 /* last 4 bits of the address */
246
Matthias Fuchsc553b5f2009-02-15 22:26:54 +0100247#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
stroese071d8972003-05-23 11:35:47 +0000248
Matthias Fuchsc553b5f2009-02-15 22:26:54 +0100249/*
stroese071d8972003-05-23 11:35:47 +0000250 * External Bus Controller (EBC) Setup
251 */
Matthias Fuchsc553b5f2009-02-15 22:26:54 +0100252#define FLASH0_BA 0xFF000000 /* FLASH 0 Base Address */
253#define FLASH1_BA 0xFE000000 /* FLASH 1 Base Address */
254#define CAN_BA 0xF0000000 /* CAN Base Addres */
255#define RTC_BA 0xF0000500 /* RTC Base Address */
256#define NVRAM_BA 0xF0200000 /* NVRAM Base Address */
stroese071d8972003-05-23 11:35:47 +0000257
Matthias Fuchsc553b5f2009-02-15 22:26:54 +0100258/* Memory Bank 0 (Flash Bank 0) initialization */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200259#define CONFIG_SYS_EBC_PB0AP 0x92015480
Matthias Fuchsc553b5f2009-02-15 22:26:54 +0100260/* BAS=0xFF0,BS=16MB,BU=R/W,BW=16bit */
261#define CONFIG_SYS_EBC_PB0CR (FLASH0_BA | 0x9A000)
stroese071d8972003-05-23 11:35:47 +0000262
Matthias Fuchsc553b5f2009-02-15 22:26:54 +0100263/* Memory Bank 1 (Flash Bank 1) initialization */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200264#define CONFIG_SYS_EBC_PB1AP 0x92015480
Matthias Fuchsc553b5f2009-02-15 22:26:54 +0100265/* BAS=0xFE0,BS=16MB,BU=R/W,BW=16bit*/
266#define CONFIG_SYS_EBC_PB1CR (FLASH1_BA | 0x9A000)
stroese071d8972003-05-23 11:35:47 +0000267
Matthias Fuchsc553b5f2009-02-15 22:26:54 +0100268/* Memory Bank 2 (CAN0, 1, RTC) initialization */
269/* TWT=5,TH=2,CSN=0,OEN=0,WBN=0,WBF=0 */
270#define CONFIG_SYS_EBC_PB2AP 0x03000440
271/* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */
272#define CONFIG_SYS_EBC_PB2CR (CAN_BA | 0x18000)
stroese071d8972003-05-23 11:35:47 +0000273
Stefan Roese2076d0a2006-01-18 20:03:15 +0100274/* Memory Bank 3 -> unused */
275
Matthias Fuchsc553b5f2009-02-15 22:26:54 +0100276/* Memory Bank 4 (NVRAM) initialization */
277/* TWT=5,TH=2,CSN=0,OEN=0,WBN=0,WBF=0 */
278#define CONFIG_SYS_EBC_PB4AP 0x03000440
279/* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */
280#define CONFIG_SYS_EBC_PB4CR (NVRAM_BA | 0x18000)
stroese071d8972003-05-23 11:35:47 +0000281
Matthias Fuchsc553b5f2009-02-15 22:26:54 +0100282/*
stroese2853d292003-09-12 08:53:54 +0000283 * FPGA stuff
284 */
Matthias Fuchsc553b5f2009-02-15 22:26:54 +0100285#define CONFIG_SYS_FPGA_XC95XL 1 /* using Xilinx XC95XL CPLD */
Matthias Fuchs2f6eb912009-02-15 22:27:47 +0100286#define CONFIG_SYS_FPGA_MAX_SIZE (32 * 1024) /* 32kByte for CPLD */
stroese2853d292003-09-12 08:53:54 +0000287
288/* FPGA program pin configuration */
Matthias Fuchsc553b5f2009-02-15 22:26:54 +0100289#define CONFIG_SYS_FPGA_PRG 0x04000000 /* JTAG TMS pin (output) */
290#define CONFIG_SYS_FPGA_CLK 0x02000000 /* JTAG TCK pin (output) */
291#define CONFIG_SYS_FPGA_DATA 0x01000000 /* JTAG TDO pin (output) */
292#define CONFIG_SYS_FPGA_INIT 0x00010000 /* unused (ppc input) */
293#define CONFIG_SYS_FPGA_DONE 0x00008000 /* JTAG TDI pin (input) */
stroese2853d292003-09-12 08:53:54 +0000294
Matthias Fuchsc553b5f2009-02-15 22:26:54 +0100295/* pass Ethernet MAC to VxWorks */
296#define CONFIG_SYS_VXWORKS_MAC_PTR 0x00000000
stroesea20b27a2004-12-16 18:05:42 +0000297
Matthias Fuchsc553b5f2009-02-15 22:26:54 +0100298/*
Stefan Roese2076d0a2006-01-18 20:03:15 +0100299 * GPIOs
300 */
Matthias Fuchs2f6eb912009-02-15 22:27:47 +0100301#define CONFIG_SYS_VPEN (0x80000000 >> 3) /* GPIO3 */
Matthias Fuchsc553b5f2009-02-15 22:26:54 +0100302#define CONFIG_SYS_NONMONARCH (0x80000000 >> 14) /* GPIO14 */
303#define CONFIG_SYS_XEREADY (0x80000000 >> 15) /* GPIO15 */
304#define CONFIG_SYS_INTA_FAKE (0x80000000 >> 19) /* GPIO19 */
305#define CONFIG_SYS_SELF_RST (0x80000000 >> 21) /* GPIO21 */
306#define CONFIG_SYS_REV1_2 (0x80000000 >> 23) /* GPIO23 */
Stefan Roese2076d0a2006-01-18 20:03:15 +0100307
Matthias Fuchsc553b5f2009-02-15 22:26:54 +0100308/*
stroese071d8972003-05-23 11:35:47 +0000309 * Definitions for initial stack pointer and data area (in data cache)
310 */
311
Matthias Fuchsc553b5f2009-02-15 22:26:54 +0100312/* use on chip memory (OCM) for temperary stack until sdram is tested */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200313#define CONFIG_SYS_TEMP_STACK_OCM 1
stroese071d8972003-05-23 11:35:47 +0000314
315/* On Chip Memory location */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200316#define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000
317#define CONFIG_SYS_OCM_DATA_SIZE 0x1000
stroese071d8972003-05-23 11:35:47 +0000318
Matthias Fuchsc553b5f2009-02-15 22:26:54 +0100319/* inside of SDRAM */
320#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR
321
322/* End of used area in RAM */
323#define CONFIG_SYS_INIT_RAM_END CONFIG_SYS_OCM_DATA_SIZE
324
325/* size in bytes reserved for initial data */
326#define CONFIG_SYS_GBL_DATA_SIZE 128
327#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - \
328 CONFIG_SYS_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200329#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
stroese071d8972003-05-23 11:35:47 +0000330
331/*
332 * Internal Definitions
333 *
334 * Boot Flags
335 */
Matthias Fuchsc553b5f2009-02-15 22:26:54 +0100336#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
337#define BOOTFLAG_WARM 0x02 /* Software reboot */
stroese071d8972003-05-23 11:35:47 +0000338
Matthias Fuchs2f6eb912009-02-15 22:27:47 +0100339#define CONFIG_OF_LIBFDT
340#define CONFIG_OF_BOARD_SETUP
341
Matthias Fuchsc553b5f2009-02-15 22:26:54 +0100342#endif /* __CONFIG_H */