blob: 4c80bad133e187af4a2109591d261537a27421d4 [file] [log] [blame]
Markus Klotzbuecher090eb732006-07-12 15:26:01 +02001/*
2 * (C) Copyright 2000-2005
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * (C) Copyright 2006
6 * Martin Krause, TQ-Systems GmBH, martin.krause@tqs.de
7 *
8 * See file CREDITS for list of people who contributed to this
9 * project.
10 *
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 * MA 02111-1307 USA
25 */
26
27/*
28 * board/config.h - configuration options, board specific
29 */
30
31#ifndef __CONFIG_H
32#define __CONFIG_H
33
34/*
35 * High Level Configuration Options
36 * (easy to change)
37 */
38
39#define CONFIG_MPC885 1 /* This is a MPC885 CPU */
40#define CONFIG_TQM885D 1 /* ...on a TQM88D module */
41
42#define CONFIG_8xx_OSCLK 10000000 /* 10 MHz - PLL input clock */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020043#define CONFIG_SYS_8xx_CPUCLK_MIN 15000000 /* 15 MHz - CPU minimum clock */
44#define CONFIG_SYS_8xx_CPUCLK_MAX 133000000 /* 133 MHz - CPU maximum clock */
Jens Gehrlein22d1a562007-09-26 17:55:54 +020045#define CONFIG_8xx_CPUCLK_DEFAULT 66000000 /* 66 MHz - CPU default clock */
Markus Klotzbuecher090eb732006-07-12 15:26:01 +020046 /* (it will be used if there is no */
47 /* 'cpuclk' variable with valid value) */
48
Markus Klotzbuecher090eb732006-07-12 15:26:01 +020049#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
50
51#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */
52
53#define CONFIG_BOOTCOUNT_LIMIT
54
55#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
56
57#define CONFIG_BOARD_TYPES 1 /* support board types */
58
59#define CONFIG_PREBOOT "echo;" \
Wolfgang Denk32bf3d12008-03-03 12:16:44 +010060 "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
Markus Klotzbuecher090eb732006-07-12 15:26:01 +020061 "echo"
62
63#undef CONFIG_BOOTARGS
64
65#define CONFIG_EXTRA_ENV_SETTINGS \
66 "netdev=eth0\0" \
67 "nfsargs=setenv bootargs root=/dev/nfs rw " \
68 "nfsroot=${serverip}:${rootpath}\0" \
69 "ramargs=setenv bootargs root=/dev/ram rw\0" \
70 "addip=setenv bootargs ${bootargs} " \
71 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
72 ":${hostname}:${netdev}:off panic=1\0" \
73 "flash_nfs=run nfsargs addip;" \
74 "bootm ${kernel_addr}\0" \
75 "flash_self=run ramargs addip;" \
76 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
77 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
78 "rootpath=/opt/eldk/ppc_8xx\0" \
Martin Krause11d9eec2007-09-26 17:55:56 +020079 "bootfile=/tftpboot/TQM885D/uImage\0" \
80 "fdt_addr=400C0000\0" \
81 "kernel_addr=40100000\0" \
82 "ramdisk_addr=40280000\0" \
83 "load=tftp 200000 ${u-boot}\0" \
84 "update=protect off 40000000 +${filesize};" \
85 "erase 40000000 +${filesize};" \
86 "cp.b 200000 40000000 ${filesize};" \
87 "protect on 40000000 +${filesize}\0" \
Markus Klotzbuecher090eb732006-07-12 15:26:01 +020088 ""
89#define CONFIG_BOOTCOMMAND "run flash_self"
90
91#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020092#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */
Markus Klotzbuecher090eb732006-07-12 15:26:01 +020093
94#undef CONFIG_WATCHDOG /* watchdog disabled */
95
96#define CONFIG_STATUS_LED 1 /* Status LED enabled */
97
98#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */
99
100/* enable I2C and select the hardware/software driver */
101#undef CONFIG_HARD_I2C /* I2C with hardware support */
102#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */
103
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200104#define CONFIG_SYS_I2C_SPEED 93000 /* 93 kHz is supposed to work */
105#define CONFIG_SYS_I2C_SLAVE 0xFE
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200106
107#ifdef CONFIG_SOFT_I2C
108/*
109 * Software (bit-bang) I2C driver configuration
110 */
111#define PB_SCL 0x00000020 /* PB 26 */
112#define PB_SDA 0x00000010 /* PB 27 */
113
114#define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL)
115#define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA)
116#define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA)
117#define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
118#define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SDA; \
119 else immr->im_cpm.cp_pbdat &= ~PB_SDA
120#define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \
121 else immr->im_cpm.cp_pbdat &= ~PB_SCL
122#define I2C_DELAY udelay(2) /* 1/4 I2C clock duration */
123#endif /* CONFIG_SOFT_I2C */
124
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200125#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM AT24C?? */
126#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* two byte address */
127#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4
128#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200129
130# define CONFIG_RTC_DS1337 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200131# define CONFIG_SYS_I2C_RTC_ADDR 0x68
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200132
Jon Loeliger37d4bb72007-07-09 21:38:02 -0500133/*
134 * BOOTP options
135 */
136#define CONFIG_BOOTP_SUBNETMASK
137#define CONFIG_BOOTP_GATEWAY
138#define CONFIG_BOOTP_HOSTNAME
139#define CONFIG_BOOTP_BOOTPATH
140#define CONFIG_BOOTP_BOOTFILESIZE
141
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200142
143#define CONFIG_MAC_PARTITION
144#define CONFIG_DOS_PARTITION
145
Martin Krause11d9eec2007-09-26 17:55:56 +0200146#undef CONFIG_RTC_MPC8xx /* MPC885 does not support RTC */
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200147
148#define CONFIG_TIMESTAMP /* but print image timestmps */
149
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200150
Jon Loeliger26946902007-07-04 22:30:50 -0500151/*
152 * Command line configuration.
153 */
154#include <config_cmd_default.h>
155
156#define CONFIG_CMD_ASKENV
157#define CONFIG_CMD_DATE
158#define CONFIG_CMD_DHCP
159#define CONFIG_CMD_EEPROM
Wolfgang Denk9a63b7f2009-02-21 21:51:21 +0100160#define CONFIG_CMD_EXT2
Jon Loeliger26946902007-07-04 22:30:50 -0500161#define CONFIG_CMD_I2C
162#define CONFIG_CMD_IDE
163#define CONFIG_CMD_MII
164#define CONFIG_CMD_NFS
165#define CONFIG_CMD_PING
166
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200167
168/*
169 * Miscellaneous configurable options
170 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200171#define CONFIG_SYS_LONGHELP /* undef to save memory */
172#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200173
Wolfgang Denk2751a952006-10-28 02:29:14 +0200174#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200175#define CONFIG_SYS_HUSH_PARSER 1 /* Use the HUSH parser */
176#ifdef CONFIG_SYS_HUSH_PARSER
177#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200178#endif
179
Jon Loeliger26946902007-07-04 22:30:50 -0500180#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200181#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200182#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200183#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200184#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200185#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
186#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
187#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200188
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200189#define CONFIG_SYS_MEMTEST_START 0x0100000 /* memtest works on */
190#define CONFIG_SYS_MEMTEST_END 0x0300000 /* 1 ... 3 MB in DRAM */
191#define CONFIG_SYS_ALT_MEMTEST /* alternate, more extensive
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200192 memory test.*/
193
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200194#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200195
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200196#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200197
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200198#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200199
200/*
Jon Loeligera1aa0bb2007-07-10 09:22:23 -0500201 * Enable loopw command.
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200202 */
203#define CONFIG_LOOPW
204
205/*
206 * Low Level Configuration Settings
207 * (address mappings, register initial values, etc.)
208 * You should know what you are doing if you make changes here.
209 */
210/*-----------------------------------------------------------------------
211 * Internal Memory Mapped Register
212 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200213#define CONFIG_SYS_IMMR 0xFFF00000
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200214
215/*-----------------------------------------------------------------------
216 * Definitions for initial stack pointer and data area (in DPRAM)
217 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200218#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
219#define CONFIG_SYS_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
220#define CONFIG_SYS_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
221#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
222#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200223
224/*-----------------------------------------------------------------------
225 * Start addresses for the final memory configuration
226 * (Set up by the startup code)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200227 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200228 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200229#define CONFIG_SYS_SDRAM_BASE 0x00000000
230#define CONFIG_SYS_FLASH_BASE 0x40000000
231#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
232#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
233#define CONFIG_SYS_MALLOC_LEN (256 << 10) /* Reserve 128 kB for malloc() */
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200234
235/*
236 * For booting Linux, the board info and command line data
237 * have to be in the first 8 MB of memory, since this is
238 * the maximum mapped by the Linux kernel during initialization.
239 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200240#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200241
242/*-----------------------------------------------------------------------
243 * FLASH organization
244 */
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200245
Martin Krausee318d9e2007-09-27 11:10:08 +0200246/* use CFI flash driver */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200247#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +0200248#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200249#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
250#define CONFIG_SYS_FLASH_EMPTY_INFO
251#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
252#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
253#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200254
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200255#define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200256#define CONFIG_ENV_OFFSET 0x40000 /* Offset of Environment Sector */
257#define CONFIG_ENV_SIZE 0x08000 /* Total Size of Environment */
258#define CONFIG_ENV_SECT_SIZE 0x40000 /* Total Size of Environment Sector */
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200259
260/* Address and size of Redundant Environment Sector */
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200261#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SECT_SIZE)
262#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200263
264/*-----------------------------------------------------------------------
265 * Hardware Information Block
266 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200267#define CONFIG_SYS_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */
268#define CONFIG_SYS_HWINFO_SIZE 0x00000040 /* size of HW Info block */
269#define CONFIG_SYS_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200270
271/*-----------------------------------------------------------------------
272 * Cache Configuration
273 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200274#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
Jon Loeliger26946902007-07-04 22:30:50 -0500275#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200276#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200277#endif
278
279/*-----------------------------------------------------------------------
280 * SYPCR - System Protection Control 11-9
281 * SYPCR can only be written once after reset!
282 *-----------------------------------------------------------------------
283 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
284 */
285#if defined(CONFIG_WATCHDOG)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200286#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200287 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
288#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200289#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200290#endif
291
292/*-----------------------------------------------------------------------
293 * SIUMCR - SIU Module Configuration 11-6
294 *-----------------------------------------------------------------------
295 * PCMCIA config., multi-function pin tri-state
296 */
297#ifndef CONFIG_CAN_DRIVER
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200298#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200299#else /* we must activate GPL5 in the SIUMCR for CAN */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200300#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200301#endif /* CONFIG_CAN_DRIVER */
302
303/*-----------------------------------------------------------------------
304 * TBSCR - Time Base Status and Control 11-26
305 *-----------------------------------------------------------------------
306 * Clear Reference Interrupt Status, Timebase freezing enabled
307 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200308#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200309
310/*-----------------------------------------------------------------------
311 * PISCR - Periodic Interrupt Status and Control 11-31
312 *-----------------------------------------------------------------------
313 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
314 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200315#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF)
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200316
317/*-----------------------------------------------------------------------
318 * SCCR - System Clock and reset Control Register 15-27
319 *-----------------------------------------------------------------------
320 * Set clock output, timebase and RTC source and divider,
321 * power management and some other internal clocks
322 */
323#define SCCR_MASK SCCR_EBDF11
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200324#define CONFIG_SYS_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200325 SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
326 SCCR_DFALCD00)
327
328/*-----------------------------------------------------------------------
329 * PCMCIA stuff
330 *-----------------------------------------------------------------------
331 *
332 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200333#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000)
334#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 )
335#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000)
336#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 )
337#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000)
338#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 )
339#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000)
340#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 )
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200341
342/*-----------------------------------------------------------------------
343 * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
344 *-----------------------------------------------------------------------
345 */
346
347#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
348
349#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
350#undef CONFIG_IDE_LED /* LED for ide not supported */
351#undef CONFIG_IDE_RESET /* reset for ide not supported */
352
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200353#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
354#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200355
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200356#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200357
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200358#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200359
360/* Offset for data I/O */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200361#define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200362
363/* Offset for normal register accesses */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200364#define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200365
366/* Offset for alternate registers */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200367#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200368
369/*-----------------------------------------------------------------------
370 *
371 *-----------------------------------------------------------------------
372 *
373 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200374#define CONFIG_SYS_DER 0
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200375
376/*
377 * Init Memory Controller:
378 *
379 * BR0/1 and OR0/1 (FLASH)
380 */
381
382#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
383#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */
384
385/* used to re-map FLASH both when starting from SRAM or FLASH:
386 * restrict access enough to keep SRAM working (if any)
387 * but not too much to meddle with FLASH accesses
388 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200389#define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */
390#define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200391
392/*
393 * FLASH timing: Default value of OR0 after reset
394 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200395#define CONFIG_SYS_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_MSK | OR_BI | \
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200396 OR_SCY_6_CLK | OR_TRLX)
397
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200398#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
399#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
400#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200401
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200402#define CONFIG_SYS_OR1_REMAP CONFIG_SYS_OR0_REMAP
403#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM
404#define CONFIG_SYS_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V )
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200405
406/*
407 * BR2/3 and OR2/3 (SDRAM)
408 *
409 */
410#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */
411#define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */
412#define SDRAM_MAX_SIZE (256 << 20) /* max 256 MB per bank */
413
414/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200415#define CONFIG_SYS_OR_TIMING_SDRAM 0x00000A00
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200416
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200417#define CONFIG_SYS_OR2_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM )
418#define CONFIG_SYS_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200419
420#ifndef CONFIG_CAN_DRIVER
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200421#define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM
422#define CONFIG_SYS_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200423#else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200424#define CONFIG_SYS_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */
425#define CONFIG_SYS_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */
426#define CONFIG_SYS_OR3_CAN (CONFIG_SYS_CAN_OR_AM | OR_G5LA | OR_BI)
427#define CONFIG_SYS_BR3_CAN ((CONFIG_SYS_CAN_BASE & BR_BA_MSK) | \
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200428 BR_PS_8 | BR_MS_UPMB | BR_V )
429#endif /* CONFIG_CAN_DRIVER */
430
431/*
432 * 4096 Rows from SDRAM example configuration
433 * 1000 factor s -> ms
434 * 64 PTP (pre-divider from MPTPR) from SDRAM example configuration
435 * 4 Number of refresh cycles per period
436 * 64 Refresh cycle in ms per number of rows
437 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200438#define CONFIG_SYS_PTA_PER_CLK ((4096 * 64 * 1000) / (4 * 64))
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200439
440/*
Jens Gehrlein492c7042007-09-27 14:54:46 +0200441 * Periodic timer (MAMR[PTx]) for 4 * 7.8 us refresh (= 31.2 us per quad)
442 *
443 * CPUclock(MHz) * 31.2
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200444 * CONFIG_SYS_MAMR_PTA = ----------------------------------- with DFBRG = 0
Jens Gehrlein492c7042007-09-27 14:54:46 +0200445 * 2^(2*SCCR[DFBRG]) * MPTPR_PTP_DIV16
446 *
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200447 * CPU clock = 15 MHz: CONFIG_SYS_MAMR_PTA = 29 -> 4 * 7.73 us
448 * CPU clock = 50 MHz: CONFIG_SYS_MAMR_PTA = 97 -> 4 * 7.76 us
449 * CPU clock = 66 MHz: CONFIG_SYS_MAMR_PTA = 128 -> 4 * 7.75 us
450 * CPU clock = 133 MHz: CONFIG_SYS_MAMR_PTA = 255 -> 4 * 7.67 us
Jens Gehrlein492c7042007-09-27 14:54:46 +0200451 *
452 * Value 97 is for 4 * 7.8 us at 50 MHz. So the refresh cycle requirement will
453 * be met also in the default configuration, i.e. if environment variable
454 * 'cpuclk' is not set.
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200455 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200456#define CONFIG_SYS_MAMR_PTA 128
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200457
458/*
Jens Gehrlein492c7042007-09-27 14:54:46 +0200459 * Memory Periodic Timer Prescaler Register (MPTPR) values.
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200460 */
Jens Gehrlein492c7042007-09-27 14:54:46 +0200461/* 4 * 7.8 us refresh (= 31.2 us per quad) at 50 MHz and PTA = 97 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200462#define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16
Jens Gehrlein492c7042007-09-27 14:54:46 +0200463/* 4 * 3.9 us refresh (= 15.6 us per quad) at 50 MHz and PTA = 97 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200464#define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200465
466/*
467 * MAMR settings for SDRAM
468 */
469
470/* 8 column SDRAM */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200471#define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200472 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
473 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
474/* 9 column SDRAM */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200475#define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200476 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
477 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
478/* 10 column SDRAM */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200479#define CONFIG_SYS_MAMR_10COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200480 MAMR_AMA_TYPE_2 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A9 | \
481 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
482
483/*
484 * Internal Definitions
485 *
486 * Boot Flags
487 */
488#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
489#define BOOTFLAG_WARM 0x02 /* Software reboot */
490
491/*
492 * Network configuration
493 */
494#define CONFIG_SCC2_ENET /* enable ethernet on SCC2 */
495#define CONFIG_FEC_ENET /* enable ethernet on FEC */
496#define CONFIG_ETHER_ON_FEC1 /* ... for FEC1 */
497#define CONFIG_ETHER_ON_FEC2 /* ... for FEC2 */
498
Jon Loeliger26946902007-07-04 22:30:50 -0500499#if defined(CONFIG_CMD_MII)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200500#define CONFIG_SYS_DISCOVER_PHY
TsiChung Liew0f3ba7e2008-03-30 01:22:13 -0500501#define CONFIG_MII_INIT 1
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200502#endif
503
504#define CONFIG_NET_RETRY_COUNT 1 /* reduce max. timeout before
505 switching to another netwok (if the
506 tried network is unreachable) */
507
508#define CONFIG_ETHPRIME "SCC ETHERNET"
509
510#endif /* __CONFIG_H */