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Stefan Roese8b7d1f02007-01-31 16:37:34 +01001/*
2 * (C) Copyright 2003-2004
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24
25/*************************************************************************
26 * (c) 2005 esd gmbh Hannover
27 *
28 *
29 * from IceCube.h file
30 * by Reinhard Arlt reinhard.arlt@esd-electronics.com
31 *
32 *************************************************************************/
33
34#ifndef __CONFIG_H
35#define __CONFIG_H
36
37/*
38 * High Level Configuration Options
39 * (easy to change)
40 */
41
42#define CONFIG_MPC5200 1 /* This is an MPC5xxx CPU */
43#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */
44#define CONFIG_ICECUBE 1 /* ... on IceCube board */
45#define CONFIG_MECP5200 1 /* ... on MECP5200 board */
46#define CONFIG_MPC5200_DDR 1 /* ... use DDR RAM */
47
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020048#define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */
Stefan Roese8b7d1f02007-01-31 16:37:34 +010049
50#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
51#define BOOTFLAG_WARM 0x02 /* Software reboot */
52
Becky Bruce31d82672008-05-08 19:02:12 -050053#define CONFIG_HIGH_BATS 1 /* High BATs supported */
54
Stefan Roese8b7d1f02007-01-31 16:37:34 +010055/*
56 * Serial console configuration
57 */
58#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */
59#if 0 /* test-only */
60#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
61#else
62#define CONFIG_BAUDRATE 9600 /* ... at 115200 bps */
63#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020064#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
Stefan Roese8b7d1f02007-01-31 16:37:34 +010065
66
67#ifdef CONFIG_MPC5200 /* MPC5100 PCI is not supported yet. */
68
69#define CONFIG_MII
70#if 0 /* test-only !!! */
71#define CONFIG_NET_MULTI 1
72#define CONFIG_EEPRO100 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020073#define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
Stefan Roese8b7d1f02007-01-31 16:37:34 +010074#define CONFIG_NS8382X 1
75#endif
76
77#else /* MPC5100 */
78
79#endif
80
81/* Partitions */
82#define CONFIG_MAC_PARTITION
83#define CONFIG_DOS_PARTITION
84
85/* USB */
86#if 0
87#define CONFIG_USB_OHCI
Stefan Roese8b7d1f02007-01-31 16:37:34 +010088#define CONFIG_USB_STORAGE
Stefan Roese8b7d1f02007-01-31 16:37:34 +010089#endif
90
Stefan Roese8b7d1f02007-01-31 16:37:34 +010091
Jon Loeligerd794cfe2007-07-04 22:31:15 -050092/*
Jon Loeliger7f5c0152007-07-10 09:38:02 -050093 * BOOTP options
94 */
95#define CONFIG_BOOTP_BOOTFILESIZE
96#define CONFIG_BOOTP_BOOTPATH
97#define CONFIG_BOOTP_GATEWAY
98#define CONFIG_BOOTP_HOSTNAME
99
100
101/*
Jon Loeligerd794cfe2007-07-04 22:31:15 -0500102 * Command line configuration.
103 */
104#include <config_cmd_default.h>
105
106#define CONFIG_CMD_EEPROM
107#define CONFIG_CMD_FAT
108#define CONFIG_CMD_EXT2
109#define CONFIG_CMD_I2C
110#define CONFIG_CMD_IDE
111#define CONFIG_CMD_BSP
112#define CONFIG_CMD_ELF
113
Stefan Roese8b7d1f02007-01-31 16:37:34 +0100114
115#if (TEXT_BASE == 0xFF000000) /* Boot low with 16 MB Flash */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200116# define CONFIG_SYS_LOWBOOT 1
117# define CONFIG_SYS_LOWBOOT16 1
Stefan Roese8b7d1f02007-01-31 16:37:34 +0100118#endif
119#if (TEXT_BASE == 0xFF800000) /* Boot low with 8 MB Flash */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200120# define CONFIG_SYS_LOWBOOT 1
121# define CONFIG_SYS_LOWBOOT08 1
Stefan Roese8b7d1f02007-01-31 16:37:34 +0100122#endif
123
124/*
125 * Autobooting
126 */
127#define CONFIG_BOOTDELAY 3 /* autoboot after 5 seconds */
128
129#define CONFIG_PREBOOT "echo;" \
130 "echo Welcome to CBX-CPU5200 (mecp5200);" \
131 "echo"
132
133#undef CONFIG_BOOTARGS
134
135#define CONFIG_EXTRA_ENV_SETTINGS \
136 "netdev=eth0\0" \
Wolfgang Denk74357112007-02-27 14:26:04 +0100137 "flash_vxworks0=run ata_vxworks_args;setenv loadaddr ff000000;bootvx\0" \
138 "flash_vxworks1=run ata_vxworks_args;setenv loadaddr ff200000:bootvx\0" \
139 "net_vxworks=tftp $(loadaddr) $(image);run vxworks_args;bootvx\0" \
140 "vxworks_args=setenv bootargs fec(0,0)$(host):$(image) h=$(serverip) e=$(ipaddr) g=$(gatewayip) u=$(user) $(pass) tn=$(target) s=$(script)\0" \
141 "ata_vxworks_args=setenv bootargs /ata0/vxWorks h=$(serverip) e=$(ipaddr) g=$(gatewayip) u=$(user) $(pass) tn=$(target) s=$(script) o=fec0 \0" \
142 "loadaddr=01000000\0" \
143 "serverip=192.168.2.99\0" \
144 "gatewayip=10.0.0.79\0" \
145 "user=mu\0" \
146 "target=mecp5200.esd\0" \
147 "script=mecp5200.bat\0" \
148 "image=/tftpboot/vxWorks_mecp5200\0" \
149 "ipaddr=10.0.13.196\0" \
150 "netmask=255.255.0.0\0" \
Stefan Roese8b7d1f02007-01-31 16:37:34 +0100151 ""
152
153#define CONFIG_BOOTCOMMAND "run flash_vxworks0"
154
155#if defined(CONFIG_MPC5200)
156/*
157 * IPB Bus clocking configuration.
158 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200159#undef CONFIG_SYS_IPBSPEED_133 /* define for 133MHz speed */
Stefan Roese8b7d1f02007-01-31 16:37:34 +0100160#endif
161/*
162 * I2C configuration
163 */
164#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200165#define CONFIG_SYS_I2C_MODULE 2 /* Select I2C module #1 or #2 */
Stefan Roese8b7d1f02007-01-31 16:37:34 +0100166
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200167#define CONFIG_SYS_I2C_SPEED 86000 /* 100 kHz */
168#define CONFIG_SYS_I2C_SLAVE 0x7F
Stefan Roese8b7d1f02007-01-31 16:37:34 +0100169
170/*
171 * EEPROM configuration
172 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200173#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* 1010000x */
174#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
175#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5
176#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 20
177#define CONFIG_SYS_I2C_MULTI_EEPROMS 1
Stefan Roese8b7d1f02007-01-31 16:37:34 +0100178/*
179 * Flash configuration
180 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200181#define CONFIG_SYS_FLASH_BASE 0xFFC00000
182#define CONFIG_SYS_FLASH_SIZE 0x00400000
183#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x003E0000)
184#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */
185#define CONFIG_SYS_MAX_FLASH_SECT 512
Stefan Roese8b7d1f02007-01-31 16:37:34 +0100186
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200187#define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
188#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
Stefan Roese8b7d1f02007-01-31 16:37:34 +0100189
190/*
191 * Environment settings
192 */
193#if 1 /* test-only */
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200194#define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200195#define CONFIG_ENV_SIZE 0x10000
196#define CONFIG_ENV_SECT_SIZE 0x10000
Stefan Roese8b7d1f02007-01-31 16:37:34 +0100197#define CONFIG_ENV_OVERWRITE 1
198#else
Jean-Christophe PLAGNIOL-VILLARDbb1f8b42008-09-05 09:19:30 +0200199#define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200200#define CONFIG_ENV_OFFSET 0x0000 /* environment starts at the beginning of the EEPROM */
201#define CONFIG_ENV_SIZE 0x0400 /* 8192 bytes may be used for env vars*/
Stefan Roese8b7d1f02007-01-31 16:37:34 +0100202 /* total size of a CAT24WC32 is 8192 bytes */
203#define CONFIG_ENV_OVERWRITE 1
204#endif
205
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +0200206#define CONFIG_FLASH_CFI_DRIVER 1 /* Flash is CFI conformant */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200207#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */
208#define CONFIG_SYS_FLASH_PROTECTION 1 /* use hardware protection */
Stefan Roese8b7d1f02007-01-31 16:37:34 +0100209#if 0
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200210#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
Stefan Roese8b7d1f02007-01-31 16:37:34 +0100211#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200212#define CONFIG_SYS_FLASH_INCREMENT 0x00400000 /* size of flash bank */
213#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
214#define CONFIG_SYS_FLASH_EMPTY_INFO 1 /* show if bank is empty */
Stefan Roese8b7d1f02007-01-31 16:37:34 +0100215
216
217/*
218 * Memory map
219 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200220#define CONFIG_SYS_MBAR 0xF0000000
221#define CONFIG_SYS_SDRAM_BASE 0x00000000
222#define CONFIG_SYS_DEFAULT_MBAR 0x80000000
Stefan Roese8b7d1f02007-01-31 16:37:34 +0100223
224/* Use SRAM until RAM will be available */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200225#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM
226#define CONFIG_SYS_INIT_RAM_END MPC5XXX_SRAM_SIZE /* End of used area in DPRAM */
Stefan Roese8b7d1f02007-01-31 16:37:34 +0100227
228
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200229#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
230#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
231#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
Stefan Roese8b7d1f02007-01-31 16:37:34 +0100232
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200233#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
234#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
235# define CONFIG_SYS_RAMBOOT 1
Stefan Roese8b7d1f02007-01-31 16:37:34 +0100236#endif
237
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200238#define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
239#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
240#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
Stefan Roese8b7d1f02007-01-31 16:37:34 +0100241
242/*
243 * Ethernet configuration
244 */
245#define CONFIG_MPC5xxx_FEC 1
Ben Warren86321fc2009-02-05 23:58:25 -0800246#define CONFIG_MPC5xxx_FEC_MII100
Stefan Roese8b7d1f02007-01-31 16:37:34 +0100247/*
Ben Warren86321fc2009-02-05 23:58:25 -0800248 * Define CONFIG_MPC5xxx_FEC_MII10 to force FEC at 10Mb
Stefan Roese8b7d1f02007-01-31 16:37:34 +0100249 */
Ben Warren86321fc2009-02-05 23:58:25 -0800250/* #define CONFIG_MPC5xxx_FEC_MII10 */
Stefan Roese8b7d1f02007-01-31 16:37:34 +0100251#define CONFIG_PHY_ADDR 0x00
252#define CONFIG_UDP_CHECKSUM 1
253
254
255/*
256 * GPIO configuration
257 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200258#define CONFIG_SYS_GPS_PORT_CONFIG 0x01052444
Stefan Roese8b7d1f02007-01-31 16:37:34 +0100259
260/*
261 * Miscellaneous configurable options
262 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200263#define CONFIG_SYS_LONGHELP /* undef to save memory */
264#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
Jon Loeligerd794cfe2007-07-04 22:31:15 -0500265#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200266#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
Stefan Roese8b7d1f02007-01-31 16:37:34 +0100267#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200268#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
Stefan Roese8b7d1f02007-01-31 16:37:34 +0100269#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200270#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
271#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
272#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
Stefan Roese8b7d1f02007-01-31 16:37:34 +0100273
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200274#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
275#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
Stefan Roese8b7d1f02007-01-31 16:37:34 +0100276
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200277#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
Stefan Roese8b7d1f02007-01-31 16:37:34 +0100278
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200279#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
Stefan Roese8b7d1f02007-01-31 16:37:34 +0100280
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200281#define CONFIG_SYS_VXWORKS_MAC_PTR 0x00000000 /* Pass Ethernet MAC to VxWorks */
Stefan Roese8b7d1f02007-01-31 16:37:34 +0100282
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200283#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
Jon Loeligerd794cfe2007-07-04 22:31:15 -0500284#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200285# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
Jon Loeligerd794cfe2007-07-04 22:31:15 -0500286#endif
287
Stefan Roese8b7d1f02007-01-31 16:37:34 +0100288/*
289 * Various low-level settings
290 */
291#if defined(CONFIG_MPC5200)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200292#define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI
293#define CONFIG_SYS_HID0_FINAL HID0_ICE
Stefan Roese8b7d1f02007-01-31 16:37:34 +0100294#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200295#define CONFIG_SYS_HID0_INIT 0
296#define CONFIG_SYS_HID0_FINAL 0
Stefan Roese8b7d1f02007-01-31 16:37:34 +0100297#endif
298
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200299#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
300#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE
301#define CONFIG_SYS_BOOTCS_CFG 0x00085d00
Stefan Roese8b7d1f02007-01-31 16:37:34 +0100302
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200303#define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE
304#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE
Stefan Roese8b7d1f02007-01-31 16:37:34 +0100305
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200306#define CONFIG_SYS_CS1_START 0xfd000000
307#define CONFIG_SYS_CS1_SIZE 0x00010000
308#define CONFIG_SYS_CS1_CFG 0x10101410
Stefan Roese8b7d1f02007-01-31 16:37:34 +0100309
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200310#define CONFIG_SYS_CS_BURST 0x00000000
311#define CONFIG_SYS_CS_DEADCYCLE 0x33333333
Stefan Roese8b7d1f02007-01-31 16:37:34 +0100312
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200313#define CONFIG_SYS_RESET_ADDRESS 0xff000000
Stefan Roese8b7d1f02007-01-31 16:37:34 +0100314
315/*-----------------------------------------------------------------------
316 * USB stuff
317 *-----------------------------------------------------------------------
318 */
319#define CONFIG_USB_CLOCK 0x0001BBBB
320#define CONFIG_USB_CONFIG 0x00001000
321
322/*-----------------------------------------------------------------------
323 * IDE/ATA stuff Supports IDE harddisk
324 *-----------------------------------------------------------------------
325 */
326
327#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */
328
329#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
330#undef CONFIG_IDE_LED /* LED for ide not supported */
331
332#define CONFIG_IDE_RESET /* reset for ide supported */
333#define CONFIG_IDE_PREINIT
334
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200335#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
336#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
Stefan Roese8b7d1f02007-01-31 16:37:34 +0100337
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200338#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
Stefan Roese8b7d1f02007-01-31 16:37:34 +0100339
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200340#define CONFIG_SYS_ATA_BASE_ADDR MPC5XXX_ATA
Stefan Roese8b7d1f02007-01-31 16:37:34 +0100341
342/* Offset for data I/O */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200343#define CONFIG_SYS_ATA_DATA_OFFSET (0x0060)
Stefan Roese8b7d1f02007-01-31 16:37:34 +0100344
345/* Offset for normal register accesses */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200346#define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET)
Stefan Roese8b7d1f02007-01-31 16:37:34 +0100347
348/* Offset for alternate registers */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200349#define CONFIG_SYS_ATA_ALT_OFFSET (0x005C)
Stefan Roese8b7d1f02007-01-31 16:37:34 +0100350
Wolfgang Denk74357112007-02-27 14:26:04 +0100351/* Interval between registers */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200352#define CONFIG_SYS_ATA_STRIDE 4
Stefan Roese8b7d1f02007-01-31 16:37:34 +0100353
354#endif /* __CONFIG_H */