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Stefan Roesefeaedfc2005-11-15 10:35:59 +01001/*
2 * (C) Copyright 2005
3 * Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com
4 *
Wolfgang Denk3765b3e2013-10-07 13:07:26 +02005 * SPDX-License-Identifier: GPL-2.0+
Stefan Roesefeaedfc2005-11-15 10:35:59 +01006 */
7
8/*
9 * CMS700.h - configuration options, board specific
10 */
11
12#ifndef __CONFIG_H
13#define __CONFIG_H
14
15/*
16 * High Level Configuration Options
17 * (easy to change)
18 */
19
20#define CONFIG_405EP 1 /* This is a PPC405 CPU */
21#define CONFIG_4xx 1 /* ...member of PPC4xx family */
22#define CONFIG_VOM405 1 /* ...on a VOM405 board */
23
Wolfgang Denk2ae18242010-10-06 09:05:45 +020024#define CONFIG_SYS_TEXT_BASE 0xFFFC8000
25
Stefan Roesefeaedfc2005-11-15 10:35:59 +010026#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */
27#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */
28
29#define CONFIG_SYS_CLK_FREQ 33330000 /* external frequency to pll */
30
31#define CONFIG_BAUDRATE 9600
32#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */
33
34#undef CONFIG_BOOTARGS
35#undef CONFIG_BOOTCOMMAND
36
37#define CONFIG_PREBOOT /* enable preboot variable */
38
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020039#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
Stefan Roesefeaedfc2005-11-15 10:35:59 +010040
Ben Warren96e21f82008-10-27 23:50:15 -070041#define CONFIG_PPC4xx_EMAC
Stefan Roesefeaedfc2005-11-15 10:35:59 +010042#undef CONFIG_HAS_ETH1
43
44#define CONFIG_MII 1 /* MII PHY management */
45#define CONFIG_PHY_ADDR 0 /* PHY address */
46#define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */
47#define CONFIG_RESET_PHY_R 1 /* use reset_phy() to disable phy sleep mode */
48
Jon Loeliger5d2ebe12007-07-09 21:16:53 -050049/*
50 * BOOTP options
51 */
52#define CONFIG_BOOTP_SUBNETMASK
53#define CONFIG_BOOTP_GATEWAY
54#define CONFIG_BOOTP_HOSTNAME
55#define CONFIG_BOOTP_BOOTPATH
56#define CONFIG_BOOTP_DNS
57#define CONFIG_BOOTP_DNS2
58#define CONFIG_BOOTP_SEND_HOSTNAME
Stefan Roesefeaedfc2005-11-15 10:35:59 +010059
Stefan Roesefeaedfc2005-11-15 10:35:59 +010060
Jon Loeliger49cf7e82007-07-05 19:52:35 -050061/*
62 * Command line configuration.
63 */
64#include <config_cmd_default.h>
Stefan Roesefeaedfc2005-11-15 10:35:59 +010065
Jon Loeliger49cf7e82007-07-05 19:52:35 -050066#define CONFIG_CMD_DHCP
67#define CONFIG_CMD_BSP
Jon Loeliger49cf7e82007-07-05 19:52:35 -050068#define CONFIG_CMD_ELF
69#define CONFIG_CMD_NAND
70#define CONFIG_CMD_I2C
71#define CONFIG_CMD_DATE
72#define CONFIG_CMD_MII
73#define CONFIG_CMD_PING
74#define CONFIG_CMD_EEPROM
75
Stefan Roesefeaedfc2005-11-15 10:35:59 +010076
Stefan Roesefeaedfc2005-11-15 10:35:59 +010077#undef CONFIG_WATCHDOG /* watchdog disabled */
78
79#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
80
81#undef CONFIG_PRAM /* no "protected RAM" */
82
83/*
84 * Miscellaneous configurable options
85 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020086#define CONFIG_SYS_LONGHELP /* undef to save memory */
Stefan Roesefeaedfc2005-11-15 10:35:59 +010087
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020088#undef CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
Stefan Roesefeaedfc2005-11-15 10:35:59 +010089
Jon Loeliger49cf7e82007-07-05 19:52:35 -050090#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020091#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
Stefan Roesefeaedfc2005-11-15 10:35:59 +010092#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020093#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
Stefan Roesefeaedfc2005-11-15 10:35:59 +010094#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020095#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
96#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
97#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
Stefan Roesefeaedfc2005-11-15 10:35:59 +010098
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020099#define CONFIG_SYS_DEVICE_NULLDEV 1 /* include nulldev device */
Stefan Roesefeaedfc2005-11-15 10:35:59 +0100100
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200101#define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/
Stefan Roesefeaedfc2005-11-15 10:35:59 +0100102
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200103#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
104#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
Stefan Roesefeaedfc2005-11-15 10:35:59 +0100105
Stefan Roese550650d2010-09-20 16:05:31 +0200106#define CONFIG_CONS_INDEX 2 /* Use UART1 */
107#define CONFIG_SYS_NS16550
108#define CONFIG_SYS_NS16550_SERIAL
109#define CONFIG_SYS_NS16550_REG_SIZE 1
110#define CONFIG_SYS_NS16550_CLK get_serial_clock()
111
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200112#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200113#define CONFIG_SYS_BASE_BAUD 691200
Stefan Roesefeaedfc2005-11-15 10:35:59 +0100114
115/* The following table includes the supported baudrates */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200116#define CONFIG_SYS_BAUDRATE_TABLE \
Stefan Roesefeaedfc2005-11-15 10:35:59 +0100117 { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \
118 57600, 115200, 230400, 460800, 921600 }
119
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200120#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
121#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */
Stefan Roesefeaedfc2005-11-15 10:35:59 +0100122
Stefan Roesefeaedfc2005-11-15 10:35:59 +0100123#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
124
125#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
126
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200127#define CONFIG_SYS_RX_ETH_BUFFER 16 /* use 16 rx buffer on 405 emac */
Stefan Roesefeaedfc2005-11-15 10:35:59 +0100128
129/*-----------------------------------------------------------------------
130 * RTC stuff
131 *-----------------------------------------------------------------------
132 */
133#define CONFIG_RTC_DS1337
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200134#define CONFIG_SYS_I2C_RTC_ADDR 0x68
Stefan Roesefeaedfc2005-11-15 10:35:59 +0100135
136/*-----------------------------------------------------------------------
137 * NAND-FLASH stuff
138 *-----------------------------------------------------------------------
139 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200140#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200141#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
Matthias Fuchsbd84ee42007-07-09 10:10:06 +0200142#define NAND_BIG_DELAY_US 25
Stefan Roesefeaedfc2005-11-15 10:35:59 +0100143
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200144#define CONFIG_SYS_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */
145#define CONFIG_SYS_NAND_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */
146#define CONFIG_SYS_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */
147#define CONFIG_SYS_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */
Stefan Roesefeaedfc2005-11-15 10:35:59 +0100148
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200149#define CONFIG_SYS_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */
150#define CONFIG_SYS_NAND_QUIET 1
Stefan Roesefeaedfc2005-11-15 10:35:59 +0100151
Stefan Roesefeaedfc2005-11-15 10:35:59 +0100152/*
153 * For booting Linux, the board info and command line data
154 * have to be in the first 8 MB of memory, since this is
155 * the maximum mapped by the Linux kernel during initialization.
156 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200157#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
Stefan Roesefeaedfc2005-11-15 10:35:59 +0100158/*-----------------------------------------------------------------------
159 * FLASH organization
160 */
161#define FLASH_BASE0_PRELIM 0xFFC00000 /* FLASH bank #0 */
162
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200163#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
164#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
Stefan Roesefeaedfc2005-11-15 10:35:59 +0100165
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200166#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
167#define CONFIG_SYS_FLASH_WRITE_TOUT 1000 /* Timeout for Flash Write (in ms) */
Stefan Roesefeaedfc2005-11-15 10:35:59 +0100168
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200169#define CONFIG_SYS_FLASH_WORD_SIZE unsigned short /* flash word size (width) */
170#define CONFIG_SYS_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */
171#define CONFIG_SYS_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */
Stefan Roesefeaedfc2005-11-15 10:35:59 +0100172/*
173 * The following defines are added for buggy IOP480 byte interface.
174 * All other boards should use the standard values (CPCI405 etc.)
175 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200176#define CONFIG_SYS_FLASH_READ0 0x0000 /* 0 is standard */
177#define CONFIG_SYS_FLASH_READ1 0x0001 /* 1 is standard */
178#define CONFIG_SYS_FLASH_READ2 0x0002 /* 2 is standard */
Stefan Roesefeaedfc2005-11-15 10:35:59 +0100179
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200180#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
Stefan Roesefeaedfc2005-11-15 10:35:59 +0100181
Stefan Roesefeaedfc2005-11-15 10:35:59 +0100182/*-----------------------------------------------------------------------
183 * Start addresses for the final memory configuration
184 * (Set up by the startup code)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200185 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
Stefan Roesefeaedfc2005-11-15 10:35:59 +0100186 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200187#define CONFIG_SYS_SDRAM_BASE 0x00000000
Matthias Fuchs7cc635f2009-04-29 09:50:57 +0200188#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_MONITOR_BASE
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200189#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
190#define CONFIG_SYS_MONITOR_LEN (~(CONFIG_SYS_TEXT_BASE) + 1)
Matthias Fuchs7cc635f2009-04-29 09:50:57 +0200191#define CONFIG_SYS_MALLOC_LEN (256 * 1024)
Stefan Roesefeaedfc2005-11-15 10:35:59 +0100192
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200193#if (CONFIG_SYS_MONITOR_BASE < FLASH_BASE0_PRELIM)
194# define CONFIG_SYS_RAMBOOT 1
Stefan Roesefeaedfc2005-11-15 10:35:59 +0100195#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200196# undef CONFIG_SYS_RAMBOOT
Stefan Roesefeaedfc2005-11-15 10:35:59 +0100197#endif
198
199/*-----------------------------------------------------------------------
200 * Environment Variable setup
201 */
Jean-Christophe PLAGNIOL-VILLARDbb1f8b42008-09-05 09:19:30 +0200202#define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200203#define CONFIG_ENV_OFFSET 0x100 /* environment starts at the beginning of the EEPROM */
204#define CONFIG_ENV_SIZE 0x700 /* 2048 bytes may be used for env vars*/
Stefan Roesefeaedfc2005-11-15 10:35:59 +0100205 /* total size of a CAT24WC16 is 2048 bytes */
206
207/*-----------------------------------------------------------------------
208 * I2C EEPROM (CAT24WC16) for environment
209 */
Dirk Eibach880540d2013-04-25 02:40:01 +0000210#define CONFIG_SYS_I2C
211#define CONFIG_SYS_I2C_PPC4XX
212#define CONFIG_SYS_I2C_PPC4XX_CH0
213#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 100000
214#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F
Stefan Roesefeaedfc2005-11-15 10:35:59 +0100215
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200216#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */
217#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
Stefan Roesefeaedfc2005-11-15 10:35:59 +0100218/* mask of address bits that overflow into the "EEPROM chip address" */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200219#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07
220#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */
Stefan Roesefeaedfc2005-11-15 10:35:59 +0100221 /* 16 byte page write mode using*/
222 /* last 4 bits of the address */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200223#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
Stefan Roesefeaedfc2005-11-15 10:35:59 +0100224
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200225#define CONFIG_SYS_EEPROM_WREN 1
Stefan Roesefeaedfc2005-11-15 10:35:59 +0100226
227/*-----------------------------------------------------------------------
Stefan Roesefeaedfc2005-11-15 10:35:59 +0100228 * External Bus Controller (EBC) Setup
229 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200230#define CONFIG_SYS_PLD_BASE 0xf0000000
231#define CONFIG_SYS_NAND_BASE 0xF4000000 /* NAND FLASH Base Address */
Stefan Roesefeaedfc2005-11-15 10:35:59 +0100232
233/* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200234#define CONFIG_SYS_EBC_PB0AP 0x92015480
235#define CONFIG_SYS_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
Stefan Roesefeaedfc2005-11-15 10:35:59 +0100236
237/* Memory Bank 1 (Flash Bank 1, NAND-FLASH) initialization */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200238#define CONFIG_SYS_EBC_PB1AP 0x92015480
239#define CONFIG_SYS_EBC_PB1CR 0xF4018000 /* BAS=0xF40,BS=1MB,BU=R/W,BW=8bit */
Stefan Roesefeaedfc2005-11-15 10:35:59 +0100240
241/* Memory Bank 2 (8 Bit Peripheral: CAN, UART, RTC) initialization */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200242#define CONFIG_SYS_EBC_PB2AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
243#define CONFIG_SYS_EBC_PB2CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */
Stefan Roesefeaedfc2005-11-15 10:35:59 +0100244
245/*-----------------------------------------------------------------------
246 * FPGA stuff
247 */
Matthias Fuchs7cc635f2009-04-29 09:50:57 +0200248#define CONFIG_SYS_XSVF_DEFAULT_ADDR 0xfffc0000
Stefan Roesefeaedfc2005-11-15 10:35:59 +0100249
250/* FPGA program pin configuration */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200251#define CONFIG_SYS_FPGA_PRG 0x04000000 /* JTAG TMS pin (ppc output) */
252#define CONFIG_SYS_FPGA_CLK 0x02000000 /* JTAG TCK pin (ppc output) */
253#define CONFIG_SYS_FPGA_DATA 0x01000000 /* JTAG TDO->TDI data pin (ppc output) */
254#define CONFIG_SYS_FPGA_INIT 0x00010000 /* unused (ppc input) */
255#define CONFIG_SYS_FPGA_DONE 0x00008000 /* JTAG TDI->TDO pin (ppc input) */
Stefan Roesefeaedfc2005-11-15 10:35:59 +0100256
257/*-----------------------------------------------------------------------
258 * Definitions for initial stack pointer and data area (in data cache)
259 */
260/* use on chip memory ( OCM ) for temperary stack until sdram is tested */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200261#define CONFIG_SYS_TEMP_STACK_OCM 1
Stefan Roesefeaedfc2005-11-15 10:35:59 +0100262
263/* On Chip Memory location */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200264#define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000
265#define CONFIG_SYS_OCM_DATA_SIZE 0x1000
266#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM */
Wolfgang Denk553f0982010-10-26 13:32:32 +0200267#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM */
Stefan Roesefeaedfc2005-11-15 10:35:59 +0100268
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200269#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200270#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
Stefan Roesefeaedfc2005-11-15 10:35:59 +0100271
272/*-----------------------------------------------------------------------
273 * Definitions for GPIO setup (PPC405EP specific)
274 *
275 * GPIO0[0] - External Bus Controller BLAST output
276 * GPIO0[1-9] - Instruction trace outputs -> GPIO
277 * GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs
278 * GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs -> GPIO
279 * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs
280 * GPIO0[24-27] - UART0 control signal inputs/outputs
281 * GPIO0[28-29] - UART1 data signal input/output
282 * GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs
283 */
284/* GPIO Input: OSR=00, ISR=00, TSR=00, TCR=0 */
285/* GPIO Output: OSR=00, ISR=00, TSR=00, TCR=1 */
286/* Alt. Funtion Input: OSR=00, ISR=01, TSR=00, TCR=0 */
287/* Alt. Funtion Output: OSR=01, ISR=00, TSR=00, TCR=1 */
Stefan Roeseafabb492010-09-12 06:21:37 +0200288#define CONFIG_SYS_GPIO0_OSRL 0x40000500 /* 0 ... 15 */
289#define CONFIG_SYS_GPIO0_OSRH 0x00000110 /* 16 ... 31 */
290#define CONFIG_SYS_GPIO0_ISR1L 0x00000000 /* 0 ... 15 */
291#define CONFIG_SYS_GPIO0_ISR1H 0x14000045 /* 16 ... 31 */
292#define CONFIG_SYS_GPIO0_TSRL 0x00000000 /* 0 ... 15 */
293#define CONFIG_SYS_GPIO0_TSRH 0x00000000 /* 16 ... 31 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200294#define CONFIG_SYS_GPIO0_TCR 0xF7FE0014 /* 0 ... 31 */
Stefan Roesefeaedfc2005-11-15 10:35:59 +0100295
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200296#define CONFIG_SYS_EEPROM_WP (0x80000000 >> 8) /* GPIO8 */
297#define CONFIG_SYS_PLD_RESET (0x80000000 >> 12) /* GPIO12 */
Stefan Roesefeaedfc2005-11-15 10:35:59 +0100298
299/*
Stefan Roesefeaedfc2005-11-15 10:35:59 +0100300 * Default speed selection (cpu_plb_opb_ebc) in mhz.
301 * This value will be set if iic boot eprom is disabled.
302 */
Stefan Roesefeaedfc2005-11-15 10:35:59 +0100303#define PLLMR0_DEFAULT PLLMR0_133_66_66_33
304#define PLLMR1_DEFAULT PLLMR1_133_66_66_33
Stefan Roesefeaedfc2005-11-15 10:35:59 +0100305
306#endif /* __CONFIG_H */