wdenk | 9e3f8cd | 2002-09-15 14:08:13 +0000 | [diff] [blame] | 1 | /* |
wdenk | 414eec3 | 2005-04-02 22:37:54 +0000 | [diff] [blame] | 2 | * (C) Copyright 2001-2005 |
wdenk | 9e3f8cd | 2002-09-15 14:08:13 +0000 | [diff] [blame] | 3 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
| 4 | * |
Wolfgang Denk | 1a45966 | 2013-07-08 09:37:19 +0200 | [diff] [blame] | 5 | * SPDX-License-Identifier: GPL-2.0+ |
wdenk | 9e3f8cd | 2002-09-15 14:08:13 +0000 | [diff] [blame] | 6 | */ |
| 7 | |
| 8 | /* |
| 9 | * board/config.h - configuration options, board specific |
| 10 | */ |
| 11 | |
| 12 | #ifndef __CONFIG_H |
| 13 | #define __CONFIG_H |
| 14 | |
| 15 | #include <mpc8xx_irq.h> |
| 16 | |
| 17 | /* |
| 18 | * High Level Configuration Options |
| 19 | * (easy to change) |
| 20 | */ |
| 21 | #define CONFIG_MPC860 1 |
| 22 | #define CONFIG_MPC860T 1 |
| 23 | #define CONFIG_ICU862 1 |
| 24 | #define CONFIG_MPC862 1 |
| 25 | |
Wolfgang Denk | 2ae1824 | 2010-10-06 09:05:45 +0200 | [diff] [blame] | 26 | #define CONFIG_SYS_TEXT_BASE 0x40F00000 |
| 27 | |
wdenk | 9e3f8cd | 2002-09-15 14:08:13 +0000 | [diff] [blame] | 28 | #define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ |
| 29 | #undef CONFIG_8xx_CONS_SMC2 |
| 30 | #undef CONFIG_8xx_CONS_NONE |
| 31 | #define CONFIG_BAUDRATE 9600 |
| 32 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ |
| 33 | |
| 34 | #ifdef CONFIG_100MHz |
| 35 | #define MPC8XX_FACT 24 /* Multiply by 24 */ |
| 36 | #define MPC8XX_XIN 4165000 /* 4.165 MHz in */ |
| 37 | #define CONFIG_8xx_GCLK_FREQ (MPC8XX_FACT * MPC8XX_XIN) |
| 38 | /* define if cant' use get_gclk_freq */ |
| 39 | #else |
| 40 | #if 1 /* for 50MHz version of processor */ |
| 41 | #define MPC8XX_FACT 12 /* Multiply by 12 */ |
| 42 | #define MPC8XX_XIN 4000000 /* 4 MHz in */ |
| 43 | #define CONFIG_8xx_GCLK_FREQ 48000000 /* define if cant use get_gclk_freq */ |
| 44 | #else /* for 80MHz version of processor */ |
| 45 | #define MPC8XX_FACT 20 /* Multiply by 20 */ |
| 46 | #define MPC8XX_XIN 4000000 /* 4 MHz in */ |
| 47 | #define CONFIG_8xx_GCLK_FREQ 80000000 /* define if cant use get_gclk_freq */ |
| 48 | #endif |
| 49 | #endif |
| 50 | |
wdenk | 9e3f8cd | 2002-09-15 14:08:13 +0000 | [diff] [blame] | 51 | #if 0 |
| 52 | #define CONFIG_BOOTDELAY -1 /* autoboot disabled */ |
| 53 | #else |
| 54 | #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ |
| 55 | #endif |
| 56 | |
Wolfgang Denk | 32bf3d1 | 2008-03-03 12:16:44 +0100 | [diff] [blame] | 57 | #define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo" |
wdenk | 9e3f8cd | 2002-09-15 14:08:13 +0000 | [diff] [blame] | 58 | |
| 59 | #undef CONFIG_BOOTARGS |
| 60 | #define CONFIG_BOOTCOMMAND \ |
Wolfgang Denk | 53677ef | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 61 | "bootp;" \ |
| 62 | "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ |
| 63 | "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \ |
wdenk | 9e3f8cd | 2002-09-15 14:08:13 +0000 | [diff] [blame] | 64 | "bootm" |
| 65 | |
| 66 | #undef CONFIG_WATCHDOG /* watchdog disabled */ |
| 67 | |
| 68 | #define CONFIG_STATUS_LED 1 /* Status LED enabled */ |
| 69 | |
Jon Loeliger | 7be044e | 2007-07-09 21:24:19 -0500 | [diff] [blame] | 70 | /* |
| 71 | * BOOTP options |
| 72 | */ |
| 73 | #define CONFIG_BOOTP_SUBNETMASK |
| 74 | #define CONFIG_BOOTP_GATEWAY |
| 75 | #define CONFIG_BOOTP_HOSTNAME |
| 76 | #define CONFIG_BOOTP_BOOTPATH |
| 77 | #define CONFIG_BOOTP_BOOTFILESIZE |
| 78 | |
wdenk | 9e3f8cd | 2002-09-15 14:08:13 +0000 | [diff] [blame] | 79 | |
| 80 | #undef CONFIG_SCC1_ENET /* disable SCC1 ethernet */ |
| 81 | #define CONFIG_FEC_ENET 1 /* use FEC ethernet */ |
Marian Balakowicz | 63ff004 | 2005-10-28 22:30:33 +0200 | [diff] [blame] | 82 | #define CONFIG_MII 1 |
wdenk | 9e3f8cd | 2002-09-15 14:08:13 +0000 | [diff] [blame] | 83 | #if 1 |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 84 | #define CONFIG_SYS_DISCOVER_PHY 1 |
wdenk | 9e3f8cd | 2002-09-15 14:08:13 +0000 | [diff] [blame] | 85 | #else |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 86 | #undef CONFIG_SYS_DISCOVER_PHY |
wdenk | 9e3f8cd | 2002-09-15 14:08:13 +0000 | [diff] [blame] | 87 | #endif |
| 88 | |
| 89 | #define CONFIG_MAC_PARTITION |
| 90 | #define CONFIG_DOS_PARTITION |
| 91 | |
| 92 | /* enable I2C and select the hardware/software driver */ |
Heiko Schocher | ea818db | 2013-01-29 08:53:15 +0100 | [diff] [blame] | 93 | #define CONFIG_SYS_I2C |
| 94 | #define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */ |
| 95 | #define CONFIG_SYS_I2C_SOFT_SPEED 50000 |
| 96 | #define CONFIG_SYS_I2C_SOFT_SLAVE 0xFE |
wdenk | 9e3f8cd | 2002-09-15 14:08:13 +0000 | [diff] [blame] | 97 | /* |
| 98 | * Software (bit-bang) I2C driver configuration |
| 99 | */ |
| 100 | #define PB_SCL 0x00000020 /* PB 26 */ |
| 101 | #define PB_SDA 0x00000010 /* PB 27 */ |
| 102 | |
| 103 | #define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL) |
| 104 | #define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA) |
| 105 | #define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA) |
| 106 | #define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0) |
| 107 | #define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SDA; \ |
| 108 | else immr->im_cpm.cp_pbdat &= ~PB_SDA |
| 109 | #define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \ |
| 110 | else immr->im_cpm.cp_pbdat &= ~PB_SCL |
| 111 | #define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ |
| 112 | |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 113 | #define CONFIG_SYS_EEPROM_X40430 /* Use a Xicor X40430 EEPROM */ |
| 114 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* 16 bytes page write mode */ |
wdenk | 9e3f8cd | 2002-09-15 14:08:13 +0000 | [diff] [blame] | 115 | |
| 116 | #define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ |
| 117 | |
Heiko Schocher | ea818db | 2013-01-29 08:53:15 +0100 | [diff] [blame] | 118 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 |
| 119 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ |
| 120 | |
wdenk | 9e3f8cd | 2002-09-15 14:08:13 +0000 | [diff] [blame] | 121 | |
Jon Loeliger | 348f258 | 2007-07-08 13:46:18 -0500 | [diff] [blame] | 122 | /* |
| 123 | * Command line configuration. |
| 124 | */ |
| 125 | #include <config_cmd_default.h> |
| 126 | |
| 127 | #define CONFIG_CMD_ASKENV |
| 128 | #define CONFIG_CMD_DATE |
| 129 | #define CONFIG_CMD_DHCP |
| 130 | #define CONFIG_CMD_EEPROM |
| 131 | #define CONFIG_CMD_I2C |
| 132 | #define CONFIG_CMD_IDE |
| 133 | #define CONFIG_CMD_NFS |
| 134 | #define CONFIG_CMD_SNTP |
| 135 | |
wdenk | 9e3f8cd | 2002-09-15 14:08:13 +0000 | [diff] [blame] | 136 | |
| 137 | /* |
| 138 | * Miscellaneous configurable options |
| 139 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 140 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
Jon Loeliger | 348f258 | 2007-07-08 13:46:18 -0500 | [diff] [blame] | 141 | #if defined(CONFIG_CMD_KGDB) |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 142 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
wdenk | 9e3f8cd | 2002-09-15 14:08:13 +0000 | [diff] [blame] | 143 | #else |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 144 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
wdenk | 9e3f8cd | 2002-09-15 14:08:13 +0000 | [diff] [blame] | 145 | #endif |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 146 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
| 147 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ |
| 148 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ |
wdenk | 9e3f8cd | 2002-09-15 14:08:13 +0000 | [diff] [blame] | 149 | |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 150 | #define CONFIG_SYS_MEMTEST_START 0x0100000 /* memtest works on */ |
| 151 | #define CONFIG_SYS_MEMTEST_END 0x0400000 /* 1 ... 4 MB in DRAM */ |
wdenk | 9e3f8cd | 2002-09-15 14:08:13 +0000 | [diff] [blame] | 152 | |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 153 | #define CONFIG_SYS_LOAD_ADDR 0x00100000 |
wdenk | 9e3f8cd | 2002-09-15 14:08:13 +0000 | [diff] [blame] | 154 | |
wdenk | 9e3f8cd | 2002-09-15 14:08:13 +0000 | [diff] [blame] | 155 | /* |
| 156 | * Low Level Configuration Settings |
| 157 | * (address mappings, register initial values, etc.) |
| 158 | * You should know what you are doing if you make changes here. |
| 159 | */ |
| 160 | /*----------------------------------------------------------------------- |
| 161 | * Internal Memory Mapped Register |
| 162 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 163 | #define CONFIG_SYS_IMMR 0xF0000000 |
| 164 | #define CONFIG_SYS_IMMR_SIZE ((uint)(64 * 1024)) |
wdenk | 9e3f8cd | 2002-09-15 14:08:13 +0000 | [diff] [blame] | 165 | |
| 166 | /*----------------------------------------------------------------------- |
| 167 | * Definitions for initial stack pointer and data area (in DPRAM) |
| 168 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 169 | #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR |
Wolfgang Denk | 553f098 | 2010-10-26 13:32:32 +0200 | [diff] [blame] | 170 | #define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */ |
Wolfgang Denk | 25ddd1f | 2010-10-26 14:34:52 +0200 | [diff] [blame] | 171 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 172 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
wdenk | 9e3f8cd | 2002-09-15 14:08:13 +0000 | [diff] [blame] | 173 | |
| 174 | /*----------------------------------------------------------------------- |
| 175 | * Start addresses for the final memory configuration |
| 176 | * (Set up by the startup code) |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 177 | * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 |
wdenk | 9e3f8cd | 2002-09-15 14:08:13 +0000 | [diff] [blame] | 178 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 179 | #define CONFIG_SYS_SDRAM_BASE 0x00000000 |
| 180 | #define CONFIG_SYS_FLASH_BASE 0x40000000 |
| 181 | #define CONFIG_SYS_FLASH_SIZE ((uint)(16 * 1024 * 1024)) /* max 16Mbyte */ |
wdenk | 9e3f8cd | 2002-09-15 14:08:13 +0000 | [diff] [blame] | 182 | |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 183 | #define CONFIG_SYS_RESET_ADDRESS 0xFFF00100 |
wdenk | 9e3f8cd | 2002-09-15 14:08:13 +0000 | [diff] [blame] | 184 | |
| 185 | #if 0 |
| 186 | #if defined(DEBUG) |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 187 | #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ |
wdenk | 9e3f8cd | 2002-09-15 14:08:13 +0000 | [diff] [blame] | 188 | #else |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 189 | #define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */ |
wdenk | 9e3f8cd | 2002-09-15 14:08:13 +0000 | [diff] [blame] | 190 | #endif |
| 191 | #else |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 192 | #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ |
wdenk | 9e3f8cd | 2002-09-15 14:08:13 +0000 | [diff] [blame] | 193 | #endif |
Wolfgang Denk | 14d0a02 | 2010-10-07 21:51:12 +0200 | [diff] [blame] | 194 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 195 | #define CONFIG_SYS_MALLOC_LEN (256 << 10) /* Reserve 256 kB for malloc() */ |
wdenk | 9e3f8cd | 2002-09-15 14:08:13 +0000 | [diff] [blame] | 196 | |
| 197 | /* |
| 198 | * For booting Linux, the board info and command line data |
| 199 | * have to be in the first 8 MB of memory, since this is |
| 200 | * the maximum mapped by the Linux kernel during initialization. |
| 201 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 202 | #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
wdenk | 9e3f8cd | 2002-09-15 14:08:13 +0000 | [diff] [blame] | 203 | /*----------------------------------------------------------------------- |
| 204 | * FLASH organization |
| 205 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 206 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ |
| 207 | #define CONFIG_SYS_MAX_FLASH_SECT 64 /* max number of sectors on one chip */ |
wdenk | 9e3f8cd | 2002-09-15 14:08:13 +0000 | [diff] [blame] | 208 | |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 209 | #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ |
| 210 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ |
wdenk | 9e3f8cd | 2002-09-15 14:08:13 +0000 | [diff] [blame] | 211 | |
| 212 | |
Jean-Christophe PLAGNIOL-VILLARD | 5a1aceb | 2008-09-10 22:48:04 +0200 | [diff] [blame] | 213 | #define CONFIG_ENV_IS_IN_FLASH 1 |
Jean-Christophe PLAGNIOL-VILLARD | 0e8d158 | 2008-09-10 22:48:06 +0200 | [diff] [blame] | 214 | #define CONFIG_ENV_OFFSET 0x00F40000 |
wdenk | 9e3f8cd | 2002-09-15 14:08:13 +0000 | [diff] [blame] | 215 | |
Jean-Christophe PLAGNIOL-VILLARD | 0e8d158 | 2008-09-10 22:48:06 +0200 | [diff] [blame] | 216 | #define CONFIG_ENV_SECT_SIZE 0x40000 /* Total Size of Environment sector */ |
| 217 | #define CONFIG_ENV_SIZE 0x4000 /* Used Size of Environment Sector */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 218 | #define CONFIG_SYS_USE_PPCENV /* Environment embedded in sect .ppcenv */ |
wdenk | 9e3f8cd | 2002-09-15 14:08:13 +0000 | [diff] [blame] | 219 | |
| 220 | /*----------------------------------------------------------------------- |
| 221 | * Cache Configuration |
| 222 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 223 | #define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ |
Jon Loeliger | 348f258 | 2007-07-08 13:46:18 -0500 | [diff] [blame] | 224 | #if defined(CONFIG_CMD_KGDB) |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 225 | #define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ |
wdenk | 9e3f8cd | 2002-09-15 14:08:13 +0000 | [diff] [blame] | 226 | #endif |
| 227 | |
| 228 | /*----------------------------------------------------------------------- |
| 229 | * SYPCR - System Protection Control 11-9 |
| 230 | * SYPCR can only be written once after reset! |
| 231 | *----------------------------------------------------------------------- |
| 232 | * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze |
| 233 | */ |
| 234 | #if defined(CONFIG_WATCHDOG) |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 235 | #define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ |
wdenk | 9e3f8cd | 2002-09-15 14:08:13 +0000 | [diff] [blame] | 236 | SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) |
| 237 | #else |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 238 | #define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) |
wdenk | 9e3f8cd | 2002-09-15 14:08:13 +0000 | [diff] [blame] | 239 | #endif |
| 240 | |
| 241 | /*----------------------------------------------------------------------- |
| 242 | * SIUMCR - SIU Module Configuration 11-6 |
| 243 | *----------------------------------------------------------------------- |
| 244 | * PCMCIA config., multi-function pin tri-state |
| 245 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 246 | #define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) |
wdenk | 9e3f8cd | 2002-09-15 14:08:13 +0000 | [diff] [blame] | 247 | |
| 248 | /*----------------------------------------------------------------------- |
| 249 | * TBSCR - Time Base Status and Control 11-26 |
| 250 | *----------------------------------------------------------------------- |
| 251 | * Clear Reference Interrupt Status, Timebase freezing enabled |
| 252 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 253 | #define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBE) |
wdenk | 9e3f8cd | 2002-09-15 14:08:13 +0000 | [diff] [blame] | 254 | |
| 255 | /*----------------------------------------------------------------------- |
| 256 | * PISCR - Periodic Interrupt Status and Control 11-31 |
| 257 | *----------------------------------------------------------------------- |
| 258 | * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled |
| 259 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 260 | #define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF) |
wdenk | 9e3f8cd | 2002-09-15 14:08:13 +0000 | [diff] [blame] | 261 | |
| 262 | /*----------------------------------------------------------------------- |
| 263 | * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 |
| 264 | *----------------------------------------------------------------------- |
| 265 | * set the PLL, the low-power modes and the reset control (15-29) |
| 266 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 267 | #define CONFIG_SYS_PLPRCR (((MPC8XX_FACT-1) << PLPRCR_MF_SHIFT) | \ |
wdenk | 9e3f8cd | 2002-09-15 14:08:13 +0000 | [diff] [blame] | 268 | PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) |
| 269 | |
| 270 | /*----------------------------------------------------------------------- |
| 271 | * SCCR - System Clock and reset Control Register 15-27 |
| 272 | *----------------------------------------------------------------------- |
| 273 | * Set clock output, timebase and RTC source and divider, |
| 274 | * power management and some other internal clocks |
| 275 | */ |
| 276 | #ifdef CONFIG_100MHz /* for 100 MHz, external bus is half CPU clock */ |
| 277 | #define SCCR_MASK 0 |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 278 | #define CONFIG_SYS_SCCR (SCCR_TBS | SCCR_COM00 | SCCR_DFSYNC00 | \ |
wdenk | 9e3f8cd | 2002-09-15 14:08:13 +0000 | [diff] [blame] | 279 | SCCR_DFBRG00 | SCCR_DFNL000 | SCCR_DFNH000 | \ |
| 280 | SCCR_DFLCD000 |SCCR_DFALCD00 | SCCR_EBDF01) |
| 281 | #else /* up to 50 MHz we use a 1:1 clock */ |
| 282 | #define SCCR_MASK SCCR_EBDF11 |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 283 | #define CONFIG_SYS_SCCR (SCCR_TBS | SCCR_COM00 | SCCR_DFSYNC00 | \ |
wdenk | 9e3f8cd | 2002-09-15 14:08:13 +0000 | [diff] [blame] | 284 | SCCR_DFBRG00 | SCCR_DFNL000 | SCCR_DFNH000 | \ |
| 285 | SCCR_DFLCD000 |SCCR_DFALCD00 ) |
| 286 | #endif /* CONFIG_100MHz */ |
| 287 | |
| 288 | /*----------------------------------------------------------------------- |
| 289 | * RCCR - RISC Controller Configuration Register 19-4 |
| 290 | *----------------------------------------------------------------------- |
| 291 | */ |
| 292 | /* +0x09C4 => DRQP = 10 (IDMA requests have lowest priority) */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 293 | #define CONFIG_SYS_RCCR 0x0020 |
wdenk | 9e3f8cd | 2002-09-15 14:08:13 +0000 | [diff] [blame] | 294 | |
| 295 | /*----------------------------------------------------------------------- |
| 296 | * PCMCIA stuff |
| 297 | *----------------------------------------------------------------------- |
| 298 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 299 | #define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000) |
| 300 | #define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 ) |
| 301 | #define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000) |
| 302 | #define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 ) |
| 303 | #define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000) |
| 304 | #define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 ) |
| 305 | #define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000) |
| 306 | #define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 ) |
wdenk | 9e3f8cd | 2002-09-15 14:08:13 +0000 | [diff] [blame] | 307 | |
| 308 | /*----------------------------------------------------------------------- |
| 309 | * PCMCIA Power Switch |
| 310 | * |
| 311 | * The ICU862 uses a TPS2205 PC-Card Power-Interface Switch to |
| 312 | * control the voltages on the PCMCIA slot which is connected to Port B |
| 313 | *----------------------------------------------------------------------- |
| 314 | */ |
| 315 | /* Output pins */ |
| 316 | #define TPS2205_VCC5 0x00008000 /* PB.16: 5V Voltage Control */ |
| 317 | #define TPS2205_VCC3 0x00004000 /* PB.17: 3V Voltage Control */ |
| 318 | #define TPS2205_VPP_PGM 0x00002000 /* PB.18: PGM Voltage Control */ |
| 319 | #define TPS2205_VPP_VCC 0x00001000 /* PB.19: VPP Voltage Control */ |
| 320 | #define TPS2205_SHDN 0x00000200 /* PB.22: Shutdown */ |
| 321 | #define TPS2205_OUTPUTS ( TPS2205_VCC5 | TPS2205_VCC3 | \ |
| 322 | TPS2205_VPP_PGM | TPS2205_VPP_VCC | \ |
| 323 | TPS2205_SHDN) |
| 324 | |
| 325 | /* Input pins */ |
| 326 | #define TPS2205_OC 0x00000100 /* PB.23: Over-Current */ |
| 327 | #define TPS2205_INPUTS ( TPS2205_OC ) |
| 328 | |
| 329 | /*----------------------------------------------------------------------- |
| 330 | * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter) |
| 331 | *----------------------------------------------------------------------- |
| 332 | */ |
| 333 | |
Pavel Herrmann | 8d1165e11a | 2012-10-09 07:01:56 +0000 | [diff] [blame] | 334 | #define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */ |
wdenk | 9e3f8cd | 2002-09-15 14:08:13 +0000 | [diff] [blame] | 335 | #define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ |
| 336 | |
| 337 | #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ |
| 338 | #undef CONFIG_IDE_LED /* LED for ide not supported */ |
| 339 | #undef CONFIG_IDE_RESET /* reset for ide not supported */ |
| 340 | |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 341 | #define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */ |
| 342 | #define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ |
wdenk | 9e3f8cd | 2002-09-15 14:08:13 +0000 | [diff] [blame] | 343 | |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 344 | #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 |
wdenk | 9e3f8cd | 2002-09-15 14:08:13 +0000 | [diff] [blame] | 345 | |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 346 | #define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR |
wdenk | 9e3f8cd | 2002-09-15 14:08:13 +0000 | [diff] [blame] | 347 | |
| 348 | /* Offset for data I/O */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 349 | #define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) |
wdenk | 9e3f8cd | 2002-09-15 14:08:13 +0000 | [diff] [blame] | 350 | |
| 351 | /* Offset for normal register accesses */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 352 | #define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) |
wdenk | 9e3f8cd | 2002-09-15 14:08:13 +0000 | [diff] [blame] | 353 | |
| 354 | /* Offset for alternate registers */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 355 | #define CONFIG_SYS_ATA_ALT_OFFSET 0x0100 |
wdenk | 9e3f8cd | 2002-09-15 14:08:13 +0000 | [diff] [blame] | 356 | |
| 357 | |
| 358 | /*----------------------------------------------------------------------- |
| 359 | * |
| 360 | *----------------------------------------------------------------------- |
| 361 | * |
| 362 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 363 | #define CONFIG_SYS_DER 0 |
wdenk | 9e3f8cd | 2002-09-15 14:08:13 +0000 | [diff] [blame] | 364 | |
| 365 | /* Because of the way the 860 starts up and assigns CS0 the |
| 366 | * entire address space, we have to set the memory controller |
| 367 | * differently. Normally, you write the option register |
| 368 | * first, and then enable the chip select by writing the |
| 369 | * base register. For CS0, you must write the base register |
| 370 | * first, followed by the option register. |
| 371 | */ |
| 372 | |
| 373 | /* |
| 374 | * Init Memory Controller: |
| 375 | * |
| 376 | * BR0 and OR0 (FLASH) |
| 377 | */ |
| 378 | |
| 379 | #define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ |
| 380 | #define FLASH_BASE1_PRELIM 0x0 /* FLASH bank #1 */ |
| 381 | |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 382 | #define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */ |
| 383 | #define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ |
wdenk | 9e3f8cd | 2002-09-15 14:08:13 +0000 | [diff] [blame] | 384 | |
| 385 | /* FLASH timing: ACS = 10, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 0 */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 386 | #define CONFIG_SYS_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_DIV4 | OR_BI | OR_SCY_3_CLK | OR_TRLX) |
wdenk | 9e3f8cd | 2002-09-15 14:08:13 +0000 | [diff] [blame] | 387 | |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 388 | #define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) |
wdenk | 9e3f8cd | 2002-09-15 14:08:13 +0000 | [diff] [blame] | 389 | |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 390 | #define CONFIG_SYS_OR0_PRELIM 0xFF000954 /* Real values for the board */ |
| 391 | #define CONFIG_SYS_BR0_PRELIM 0x40000001 /* Real values for the board */ |
wdenk | 9e3f8cd | 2002-09-15 14:08:13 +0000 | [diff] [blame] | 392 | |
| 393 | /* |
| 394 | * BR1 and OR1 (SDRAM) |
| 395 | */ |
| 396 | #define SDRAM_BASE1_PRELIM 0x00000000 /* SDRAM bank */ |
| 397 | #define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */ |
| 398 | |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 399 | #define CONFIG_SYS_OR_TIMING_SDRAM 0x00000800 /* BIH is not set */ |
wdenk | 9e3f8cd | 2002-09-15 14:08:13 +0000 | [diff] [blame] | 400 | |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 401 | #define CONFIG_SYS_OR1_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM) |
| 402 | #define CONFIG_SYS_BR1_PRELIM ((SDRAM_BASE1_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V) |
wdenk | 9e3f8cd | 2002-09-15 14:08:13 +0000 | [diff] [blame] | 403 | |
| 404 | /* |
| 405 | * Memory Periodic Timer Prescaler |
| 406 | */ |
| 407 | |
| 408 | /* periodic timer for refresh */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 409 | #define CONFIG_SYS_MAMR_PTA 97 /* start with divider for 100 MHz */ |
wdenk | 9e3f8cd | 2002-09-15 14:08:13 +0000 | [diff] [blame] | 410 | |
| 411 | /* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 412 | #define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ |
| 413 | #define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ |
wdenk | 9e3f8cd | 2002-09-15 14:08:13 +0000 | [diff] [blame] | 414 | |
| 415 | /* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 416 | #define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ |
| 417 | #define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ |
wdenk | 9e3f8cd | 2002-09-15 14:08:13 +0000 | [diff] [blame] | 418 | |
| 419 | /* |
| 420 | * MAMR settings for SDRAM |
| 421 | */ |
| 422 | |
| 423 | /* 8 column SDRAM */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 424 | #define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ |
wdenk | 9e3f8cd | 2002-09-15 14:08:13 +0000 | [diff] [blame] | 425 | MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ |
| 426 | MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) |
| 427 | /* 9 column SDRAM */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 428 | #define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ |
wdenk | 9e3f8cd | 2002-09-15 14:08:13 +0000 | [diff] [blame] | 429 | MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ |
| 430 | MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) |
| 431 | |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 432 | #define CONFIG_SYS_MAMR 0x13a01114 |
wdenk | 9e3f8cd | 2002-09-15 14:08:13 +0000 | [diff] [blame] | 433 | |
| 434 | #ifdef CONFIG_MPC860T |
| 435 | |
| 436 | /* Interrupt level assignments. |
| 437 | */ |
| 438 | #define FEC_INTERRUPT SIU_LEVEL1 /* FEC interrupt */ |
| 439 | |
| 440 | #endif /* CONFIG_MPC860T */ |
| 441 | |
| 442 | |
| 443 | #endif /* __CONFIG_H */ |